1 #ifndef ARCH_X86_CPU_H 2 #define ARCH_X86_CPU_H 3 4 /* attempt to consolidate cpu attributes */ 5 struct cpu_dev { 6 const char *c_vendor; 7 8 /* some have two possibilities for cpuid string */ 9 const char *c_ident[2]; 10 11 void (*c_early_init)(struct cpuinfo_x86 *); 12 void (*c_bsp_init)(struct cpuinfo_x86 *); 13 void (*c_init)(struct cpuinfo_x86 *); 14 void (*c_identify)(struct cpuinfo_x86 *); 15 void (*c_detect_tlb)(struct cpuinfo_x86 *); 16 void (*c_bsp_resume)(struct cpuinfo_x86 *); 17 int c_x86_vendor; 18 #ifdef CONFIG_X86_32 19 /* Optional vendor specific routine to obtain the cache size. */ 20 unsigned int (*legacy_cache_size)(struct cpuinfo_x86 *, 21 unsigned int); 22 23 /* Family/stepping-based lookup table for model names. */ 24 struct legacy_cpu_model_info { 25 int family; 26 const char *model_names[16]; 27 } legacy_models[5]; 28 #endif 29 }; 30 31 struct _tlb_table { 32 unsigned char descriptor; 33 char tlb_type; 34 unsigned int entries; 35 /* unsigned int ways; */ 36 char info[128]; 37 }; 38 39 #define cpu_dev_register(cpu_devX) \ 40 static const struct cpu_dev *const __cpu_dev_##cpu_devX __used \ 41 __attribute__((__section__(".x86_cpu_dev.init"))) = \ 42 &cpu_devX; 43 44 extern const struct cpu_dev *const __x86_cpu_dev_start[], 45 *const __x86_cpu_dev_end[]; 46 47 #ifdef CONFIG_CPU_SUP_INTEL 48 enum tsx_ctrl_states { 49 TSX_CTRL_ENABLE, 50 TSX_CTRL_DISABLE, 51 TSX_CTRL_NOT_SUPPORTED, 52 }; 53 54 extern enum tsx_ctrl_states tsx_ctrl_state; 55 56 extern void __init tsx_init(void); 57 extern void tsx_enable(void); 58 extern void tsx_disable(void); 59 #else tsx_init(void)60static inline void tsx_init(void) { } 61 #endif /* CONFIG_CPU_SUP_INTEL */ 62 63 extern void get_cpu_cap(struct cpuinfo_x86 *c); 64 extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c); 65 66 extern void x86_spec_ctrl_setup_ap(void); 67 extern void update_srbds_msr(void); 68 69 extern u64 x86_read_arch_cap_msr(void); 70 71 #endif /* ARCH_X86_CPU_H */ 72