1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 */
11 #ifndef _ASM_PROCESSOR_H
12 #define _ASM_PROCESSOR_H
13
14 #include <linux/atomic.h>
15 #include <linux/cpumask.h>
16 #include <linux/threads.h>
17
18 #include <asm/cachectl.h>
19 #include <asm/cpu.h>
20 #include <asm/cpu-info.h>
21 #include <asm/dsemul.h>
22 #include <asm/mipsregs.h>
23 #include <asm/prefetch.h>
24
25 /*
26 * Return current * instruction pointer ("program counter").
27 */
28 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
29
30 /*
31 * System setup and hardware flags..
32 */
33
34 extern unsigned int vced_count, vcei_count;
35
36 /*
37 * MIPS does have an arch_pick_mmap_layout()
38 */
39 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
40
41 #ifdef CONFIG_32BIT
42 #ifdef CONFIG_KVM_GUEST
43 /* User space process size is limited to 1GB in KVM Guest Mode */
44 #define TASK_SIZE 0x3fff8000UL
45 #else
46 /*
47 * User space process size: 2GB. This is hardcoded into a few places,
48 * so don't change it unless you know what you are doing.
49 */
50 #define TASK_SIZE 0x80000000UL
51 #endif
52
53 #define STACK_TOP_MAX TASK_SIZE
54
55 #define TASK_IS_32BIT_ADDR 1
56
57 #endif
58
59 #ifdef CONFIG_64BIT
60 /*
61 * User space process size: 1TB. This is hardcoded into a few places,
62 * so don't change it unless you know what you are doing. TASK_SIZE
63 * is limited to 1TB by the R4000 architecture; R10000 and better can
64 * support 16TB; the architectural reserve for future expansion is
65 * 8192EB ...
66 */
67 #define TASK_SIZE32 0x7fff8000UL
68 #define TASK_SIZE64 0x10000000000UL
69 #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
70 #define STACK_TOP_MAX TASK_SIZE64
71
72 #define TASK_SIZE_OF(tsk) \
73 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
74
75 #define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
76
77 #endif
78
79 /*
80 * One page above the stack is used for branch delay slot "emulation".
81 * See dsemul.c for details.
82 */
83 #define STACK_TOP ((TASK_SIZE & PAGE_MASK) - PAGE_SIZE)
84
85 /*
86 * This decides where the kernel will search for a free chunk of vm
87 * space during mmap's.
88 */
89 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
90
91
92 #define NUM_FPU_REGS 32
93
94 #ifdef CONFIG_CPU_HAS_MSA
95 # define FPU_REG_WIDTH 128
96 #else
97 # define FPU_REG_WIDTH 64
98 #endif
99
100 union fpureg {
101 __u32 val32[FPU_REG_WIDTH / 32];
102 __u64 val64[FPU_REG_WIDTH / 64];
103 };
104
105 #ifdef CONFIG_CPU_LITTLE_ENDIAN
106 # define FPR_IDX(width, idx) (idx)
107 #else
108 # define FPR_IDX(width, idx) ((idx) ^ ((64 / (width)) - 1))
109 #endif
110
111 #define BUILD_FPR_ACCESS(width) \
112 static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx) \
113 { \
114 return fpr->val##width[FPR_IDX(width, idx)]; \
115 } \
116 \
117 static inline void set_fpr##width(union fpureg *fpr, unsigned idx, \
118 u##width val) \
119 { \
120 fpr->val##width[FPR_IDX(width, idx)] = val; \
121 }
122
123 BUILD_FPR_ACCESS(32)
124 BUILD_FPR_ACCESS(64)
125
126 /*
127 * It would be nice to add some more fields for emulator statistics,
128 * the additional information is private to the FPU emulator for now.
129 * See arch/mips/include/asm/fpu_emulator.h.
130 */
131
132 struct mips_fpu_struct {
133 union fpureg fpr[NUM_FPU_REGS];
134 unsigned int fcr31;
135 unsigned int msacsr;
136 };
137
138 #define NUM_DSP_REGS 6
139
140 typedef unsigned long dspreg_t;
141
142 struct mips_dsp_state {
143 dspreg_t dspr[NUM_DSP_REGS];
144 unsigned int dspcontrol;
145 };
146
147 #define INIT_CPUMASK { \
148 {0,} \
149 }
150
151 struct mips3264_watch_reg_state {
152 /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
153 64 bit kernel. We use unsigned long as it has the same
154 property. */
155 unsigned long watchlo[NUM_WATCH_REGS];
156 /* Only the mask and IRW bits from watchhi. */
157 u16 watchhi[NUM_WATCH_REGS];
158 };
159
160 union mips_watch_reg_state {
161 struct mips3264_watch_reg_state mips3264;
162 };
163
164 #if defined(CONFIG_CPU_CAVIUM_OCTEON)
165
166 struct octeon_cop2_state {
167 /* DMFC2 rt, 0x0201 */
168 unsigned long cop2_crc_iv;
169 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
170 unsigned long cop2_crc_length;
171 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
172 unsigned long cop2_crc_poly;
173 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
174 unsigned long cop2_llm_dat[2];
175 /* DMFC2 rt, 0x0084 */
176 unsigned long cop2_3des_iv;
177 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
178 unsigned long cop2_3des_key[3];
179 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
180 unsigned long cop2_3des_result;
181 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
182 unsigned long cop2_aes_inp0;
183 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
184 unsigned long cop2_aes_iv[2];
185 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
186 * rt, 0x0107 */
187 unsigned long cop2_aes_key[4];
188 /* DMFC2 rt, 0x0110 */
189 unsigned long cop2_aes_keylen;
190 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
191 unsigned long cop2_aes_result[2];
192 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
193 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
194 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
195 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
196 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
197 unsigned long cop2_hsh_datw[15];
198 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
199 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
200 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
201 unsigned long cop2_hsh_ivw[8];
202 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
203 unsigned long cop2_gfm_mult[2];
204 /* DMFC2 rt, 0x025E - Pass2 */
205 unsigned long cop2_gfm_poly;
206 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
207 unsigned long cop2_gfm_result[2];
208 /* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */
209 unsigned long cop2_sha3[2];
210 };
211 #define COP2_INIT \
212 .cp2 = {0,},
213
214 struct octeon_cvmseg_state {
215 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
216 [cpu_dcache_line_size() / sizeof(unsigned long)];
217 };
218
219 #elif defined(CONFIG_CPU_XLP)
220 struct nlm_cop2_state {
221 u64 rx[4];
222 u64 tx[4];
223 u32 tx_msg_status;
224 u32 rx_msg_status;
225 };
226
227 #define COP2_INIT \
228 .cp2 = {{0}, {0}, 0, 0},
229 #else
230 #define COP2_INIT
231 #endif
232
233 typedef struct {
234 unsigned long seg;
235 } mm_segment_t;
236
237 #ifdef CONFIG_CPU_HAS_MSA
238 # define ARCH_MIN_TASKALIGN 16
239 # define FPU_ALIGN __aligned(16)
240 #else
241 # define ARCH_MIN_TASKALIGN 8
242 # define FPU_ALIGN
243 #endif
244
245 struct mips_abi;
246
247 /*
248 * If you change thread_struct remember to change the #defines below too!
249 */
250 struct thread_struct {
251 /* Saved main processor registers. */
252 unsigned long reg16;
253 unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
254 unsigned long reg29, reg30, reg31;
255
256 /* Saved cp0 stuff. */
257 unsigned long cp0_status;
258
259 /* Saved fpu/fpu emulator stuff. */
260 struct mips_fpu_struct fpu FPU_ALIGN;
261 /* Assigned branch delay slot 'emulation' frame */
262 atomic_t bd_emu_frame;
263 /* PC of the branch from a branch delay slot 'emulation' */
264 unsigned long bd_emu_branch_pc;
265 /* PC to continue from following a branch delay slot 'emulation' */
266 unsigned long bd_emu_cont_pc;
267 #ifdef CONFIG_MIPS_MT_FPAFF
268 /* Emulated instruction count */
269 unsigned long emulated_fp;
270 /* Saved per-thread scheduler affinity mask */
271 cpumask_t user_cpus_allowed;
272 #endif /* CONFIG_MIPS_MT_FPAFF */
273
274 /* Saved state of the DSP ASE, if available. */
275 struct mips_dsp_state dsp;
276
277 /* Saved watch register state, if available. */
278 union mips_watch_reg_state watch;
279
280 /* Other stuff associated with the thread. */
281 unsigned long cp0_badvaddr; /* Last user fault */
282 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
283 unsigned long error_code;
284 unsigned long trap_nr;
285 #ifdef CONFIG_CPU_CAVIUM_OCTEON
286 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
287 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
288 #endif
289 #ifdef CONFIG_CPU_XLP
290 struct nlm_cop2_state cp2;
291 #endif
292 struct mips_abi *abi;
293 };
294
295 #ifdef CONFIG_MIPS_MT_FPAFF
296 #define FPAFF_INIT \
297 .emulated_fp = 0, \
298 .user_cpus_allowed = INIT_CPUMASK,
299 #else
300 #define FPAFF_INIT
301 #endif /* CONFIG_MIPS_MT_FPAFF */
302
303 #define INIT_THREAD { \
304 /* \
305 * Saved main processor registers \
306 */ \
307 .reg16 = 0, \
308 .reg17 = 0, \
309 .reg18 = 0, \
310 .reg19 = 0, \
311 .reg20 = 0, \
312 .reg21 = 0, \
313 .reg22 = 0, \
314 .reg23 = 0, \
315 .reg29 = 0, \
316 .reg30 = 0, \
317 .reg31 = 0, \
318 /* \
319 * Saved cp0 stuff \
320 */ \
321 .cp0_status = 0, \
322 /* \
323 * Saved FPU/FPU emulator stuff \
324 */ \
325 .fpu = { \
326 .fpr = {{{0,},},}, \
327 .fcr31 = 0, \
328 .msacsr = 0, \
329 }, \
330 /* \
331 * FPU affinity state (null if not FPAFF) \
332 */ \
333 FPAFF_INIT \
334 /* Delay slot emulation */ \
335 .bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE), \
336 .bd_emu_branch_pc = 0, \
337 .bd_emu_cont_pc = 0, \
338 /* \
339 * Saved DSP stuff \
340 */ \
341 .dsp = { \
342 .dspr = {0, }, \
343 .dspcontrol = 0, \
344 }, \
345 /* \
346 * saved watch register stuff \
347 */ \
348 .watch = {{{0,},},}, \
349 /* \
350 * Other stuff associated with the process \
351 */ \
352 .cp0_badvaddr = 0, \
353 .cp0_baduaddr = 0, \
354 .error_code = 0, \
355 .trap_nr = 0, \
356 /* \
357 * Platform specific cop2 registers(null if no COP2) \
358 */ \
359 COP2_INIT \
360 }
361
362 struct task_struct;
363
364 /* Free all resources held by a thread. */
365 #define release_thread(thread) do { } while(0)
366
367 extern unsigned long thread_saved_pc(struct task_struct *tsk);
368
369 /*
370 * Do necessary setup to start up a newly executed thread.
371 */
372 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
373
flush_thread(void)374 static inline void flush_thread(void)
375 {
376 }
377
378 unsigned long get_wchan(struct task_struct *p);
379
380 #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
381 THREAD_SIZE - 32 - sizeof(struct pt_regs))
382 #define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
383 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
384 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
385 #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
386
387 #define cpu_relax() barrier()
388 #define cpu_relax_lowlatency() cpu_relax()
389
390 /*
391 * Return_address is a replacement for __builtin_return_address(count)
392 * which on certain architectures cannot reasonably be implemented in GCC
393 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
394 * Note that __builtin_return_address(x>=1) is forbidden because GCC
395 * aborts compilation on some CPUs. It's simply not possible to unwind
396 * some CPU's stackframes.
397 *
398 * __builtin_return_address works only for non-leaf functions. We avoid the
399 * overhead of a function call by forcing the compiler to save the return
400 * address register on the stack.
401 */
402 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
403
404 #ifdef CONFIG_CPU_HAS_PREFETCH
405
406 #define ARCH_HAS_PREFETCH
407 #define prefetch(x) __builtin_prefetch((x), 0, 1)
408
409 #define ARCH_HAS_PREFETCHW
410 #define prefetchw(x) __builtin_prefetch((x), 1, 1)
411
412 #endif
413
414 /*
415 * Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options
416 * to the prctl syscall.
417 */
418 extern int mips_get_process_fp_mode(struct task_struct *task);
419 extern int mips_set_process_fp_mode(struct task_struct *task,
420 unsigned int value);
421
422 #define GET_FP_MODE(task) mips_get_process_fp_mode(task)
423 #define SET_FP_MODE(task,value) mips_set_process_fp_mode(task, value)
424
425 #endif /* _ASM_PROCESSOR_H */
426