1 /*
2 * Copyright (c) 2014-2015 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10 #include "hns_dsaf_misc.h"
11 #include "hns_dsaf_mac.h"
12 #include "hns_dsaf_reg.h"
13 #include "hns_dsaf_ppe.h"
14
hns_cpld_set_led(struct hns_mac_cb * mac_cb,int link_status,u16 speed,int data)15 void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
16 u16 speed, int data)
17 {
18 int speed_reg = 0;
19 u8 value;
20
21 if (!mac_cb) {
22 pr_err("sfp_led_opt mac_dev is null!\n");
23 return;
24 }
25 if (!mac_cb->cpld_vaddr) {
26 dev_err(mac_cb->dev, "mac_id=%d, cpld_vaddr is null !\n",
27 mac_cb->mac_id);
28 return;
29 }
30
31 if (speed == MAC_SPEED_10000)
32 speed_reg = 1;
33
34 value = mac_cb->cpld_led_value;
35
36 if (link_status) {
37 dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
38 dsaf_set_field(value, DSAF_LED_SPEED_M,
39 DSAF_LED_SPEED_S, speed_reg);
40 dsaf_set_bit(value, DSAF_LED_DATA_B, data);
41
42 if (value != mac_cb->cpld_led_value) {
43 dsaf_write_b(mac_cb->cpld_vaddr, value);
44 mac_cb->cpld_led_value = value;
45 }
46 } else {
47 dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
48 mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
49 }
50 }
51
cpld_led_reset(struct hns_mac_cb * mac_cb)52 void cpld_led_reset(struct hns_mac_cb *mac_cb)
53 {
54 if (!mac_cb || !mac_cb->cpld_vaddr)
55 return;
56
57 dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
58 mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
59 }
60
cpld_set_led_id(struct hns_mac_cb * mac_cb,enum hnae_led_state status)61 int cpld_set_led_id(struct hns_mac_cb *mac_cb,
62 enum hnae_led_state status)
63 {
64 switch (status) {
65 case HNAE_LED_ACTIVE:
66 mac_cb->cpld_led_value = dsaf_read_b(mac_cb->cpld_vaddr);
67 dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
68 CPLD_LED_ON_VALUE);
69 dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
70 return 2;
71 case HNAE_LED_INACTIVE:
72 dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
73 CPLD_LED_DEFAULT_VALUE);
74 dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
75 break;
76 default:
77 break;
78 }
79
80 return 0;
81 }
82
83 #define RESET_REQ_OR_DREQ 1
84
hns_dsaf_rst(struct dsaf_device * dsaf_dev,u32 val)85 void hns_dsaf_rst(struct dsaf_device *dsaf_dev, u32 val)
86 {
87 u32 xbar_reg_addr;
88 u32 nt_reg_addr;
89
90 if (!val) {
91 xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
92 nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
93 } else {
94 xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
95 nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
96 }
97
98 dsaf_write_reg(dsaf_dev->sc_base, xbar_reg_addr,
99 RESET_REQ_OR_DREQ);
100 dsaf_write_reg(dsaf_dev->sc_base, nt_reg_addr,
101 RESET_REQ_OR_DREQ);
102 }
103
hns_dsaf_xge_srst_by_port(struct dsaf_device * dsaf_dev,u32 port,u32 val)104 void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
105 {
106 u32 reg_val = 0;
107 u32 reg_addr;
108
109 if (port >= DSAF_XGE_NUM)
110 return;
111
112 reg_val |= RESET_REQ_OR_DREQ;
113 reg_val |= 0x2082082 << port;
114
115 if (val == 0)
116 reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
117 else
118 reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
119
120 dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
121 }
122
hns_dsaf_xge_core_srst_by_port(struct dsaf_device * dsaf_dev,u32 port,u32 val)123 void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
124 u32 port, u32 val)
125 {
126 u32 reg_val = 0;
127 u32 reg_addr;
128
129 if (port >= DSAF_XGE_NUM)
130 return;
131
132 reg_val |= XGMAC_TRX_CORE_SRST_M << port;
133
134 if (val == 0)
135 reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
136 else
137 reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
138
139 dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
140 }
141
hns_dsaf_ge_srst_by_port(struct dsaf_device * dsaf_dev,u32 port,u32 val)142 void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
143 {
144 u32 reg_val_1;
145 u32 reg_val_2;
146
147 if (port >= DSAF_GE_NUM)
148 return;
149
150 if (port < DSAF_SERVICE_NW_NUM) {
151 reg_val_1 = 0x1 << port;
152 reg_val_2 = 0x1041041 << port;
153
154 if (val == 0) {
155 dsaf_write_reg(dsaf_dev->sc_base,
156 DSAF_SUB_SC_GE_RESET_REQ1_REG,
157 reg_val_1);
158
159 dsaf_write_reg(dsaf_dev->sc_base,
160 DSAF_SUB_SC_GE_RESET_REQ0_REG,
161 reg_val_2);
162 } else {
163 dsaf_write_reg(dsaf_dev->sc_base,
164 DSAF_SUB_SC_GE_RESET_DREQ0_REG,
165 reg_val_2);
166
167 dsaf_write_reg(dsaf_dev->sc_base,
168 DSAF_SUB_SC_GE_RESET_DREQ1_REG,
169 reg_val_1);
170 }
171 } else {
172 reg_val_1 = 0x15540 << (port - 6);
173 reg_val_2 = 0x100 << (port - 6);
174
175 if (val == 0) {
176 dsaf_write_reg(dsaf_dev->sc_base,
177 DSAF_SUB_SC_GE_RESET_REQ1_REG,
178 reg_val_1);
179
180 dsaf_write_reg(dsaf_dev->sc_base,
181 DSAF_SUB_SC_PPE_RESET_REQ_REG,
182 reg_val_2);
183 } else {
184 dsaf_write_reg(dsaf_dev->sc_base,
185 DSAF_SUB_SC_GE_RESET_DREQ1_REG,
186 reg_val_1);
187
188 dsaf_write_reg(dsaf_dev->sc_base,
189 DSAF_SUB_SC_PPE_RESET_DREQ_REG,
190 reg_val_2);
191 }
192 }
193 }
194
hns_ppe_srst_by_port(struct dsaf_device * dsaf_dev,u32 port,u32 val)195 void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
196 {
197 u32 reg_val = 0;
198 u32 reg_addr;
199
200 reg_val |= RESET_REQ_OR_DREQ << port;
201
202 if (val == 0)
203 reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
204 else
205 reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
206
207 dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
208 }
209
hns_ppe_com_srst(struct ppe_common_cb * ppe_common,u32 val)210 void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val)
211 {
212 int comm_index = ppe_common->comm_index;
213 struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
214 u32 reg_val;
215 u32 reg_addr;
216
217 if (comm_index == HNS_DSAF_COMM_SERVICE_NW_IDX) {
218 reg_val = RESET_REQ_OR_DREQ;
219 if (val == 0)
220 reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
221 else
222 reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;
223
224 } else {
225 reg_val = 0x100 << (comm_index - 1);
226
227 if (val == 0)
228 reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
229 else
230 reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
231 }
232
233 dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
234 }
235
236 /**
237 * hns_mac_get_sds_mode - get phy ifterface form serdes mode
238 * @mac_cb: mac control block
239 * retuen phy interface
240 */
hns_mac_get_phy_if(struct hns_mac_cb * mac_cb)241 phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
242 {
243 u32 hilink3_mode;
244 u32 hilink4_mode;
245 void __iomem *sys_ctl_vaddr = mac_cb->sys_ctl_vaddr;
246 int dev_id = mac_cb->mac_id;
247 phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;
248
249 hilink3_mode = dsaf_read_reg(sys_ctl_vaddr, HNS_MAC_HILINK3_REG);
250 hilink4_mode = dsaf_read_reg(sys_ctl_vaddr, HNS_MAC_HILINK4_REG);
251 if (dev_id >= 0 && dev_id <= 3) {
252 if (hilink4_mode == 0)
253 phy_if = PHY_INTERFACE_MODE_SGMII;
254 else
255 phy_if = PHY_INTERFACE_MODE_XGMII;
256 } else if (dev_id >= 4 && dev_id <= 5) {
257 if (hilink3_mode == 0)
258 phy_if = PHY_INTERFACE_MODE_SGMII;
259 else
260 phy_if = PHY_INTERFACE_MODE_XGMII;
261 } else {
262 phy_if = PHY_INTERFACE_MODE_SGMII;
263 }
264
265 dev_dbg(mac_cb->dev,
266 "hilink3_mode=%d, hilink4_mode=%d dev_id=%d, phy_if=%d\n",
267 hilink3_mode, hilink4_mode, dev_id, phy_if);
268 return phy_if;
269 }
270
271 /**
272 * hns_mac_config_sds_loopback - set loop back for serdes
273 * @mac_cb: mac control block
274 * retuen 0 == success
275 */
hns_mac_config_sds_loopback(struct hns_mac_cb * mac_cb,u8 en)276 int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, u8 en)
277 {
278 /* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
279 * port 4-7 hilink3 base is serdes_vaddr + 0x00200000
280 */
281 u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
282 (mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
283 const u8 lane_id[] = {
284 0, /* mac 0 -> lane 0 */
285 1, /* mac 1 -> lane 1 */
286 2, /* mac 2 -> lane 2 */
287 3, /* mac 3 -> lane 3 */
288 2, /* mac 4 -> lane 2 */
289 3, /* mac 5 -> lane 3 */
290 0, /* mac 6 -> lane 0 */
291 1 /* mac 7 -> lane 1 */
292 };
293 #define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
294 u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);
295
296 int sfp_prsnt;
297 int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);
298
299 if (!mac_cb->phy_node) {
300 if (ret)
301 pr_info("please confirm sfp is present or not\n");
302 else
303 if (!sfp_prsnt)
304 pr_info("no sfp in this eth\n");
305 }
306
307 dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, !!en);
308
309 return 0;
310 }
311