1 /*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14 #include <linux/clkdev.h>
15 #include <linux/gpio.h>
16 #include <linux/init.h>
17 #include <linux/clk.h>
18 #include <linux/platform_device.h>
19 #include <linux/cpufreq.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/platform_data/gpio-davinci.h>
22
23 #include <asm/mach/map.h>
24
25 #include <mach/psc.h>
26 #include <mach/irqs.h>
27 #include <mach/cputype.h>
28 #include <mach/common.h>
29 #include <mach/time.h>
30 #include <mach/da8xx.h>
31 #include <mach/cpufreq.h>
32 #include <mach/pm.h>
33
34 #include "clock.h"
35 #include "mux.h"
36
37 /* SoC specific clock flags */
38 #define DA850_CLK_ASYNC3 BIT(16)
39
40 #define DA850_PLL1_BASE 0x01e1a000
41 #define DA850_TIMER64P2_BASE 0x01f0c000
42 #define DA850_TIMER64P3_BASE 0x01f0d000
43
44 #define DA850_REF_FREQ 24000000
45
46 #define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
47 #define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
48 #define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
49
50 static int da850_set_armrate(struct clk *clk, unsigned long rate);
51 static int da850_round_armrate(struct clk *clk, unsigned long rate);
52 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
53
54 static struct pll_data pll0_data = {
55 .num = 1,
56 .phys_base = DA8XX_PLL0_BASE,
57 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
58 };
59
60 static struct clk ref_clk = {
61 .name = "ref_clk",
62 .rate = DA850_REF_FREQ,
63 .set_rate = davinci_simple_set_rate,
64 };
65
66 static struct clk pll0_clk = {
67 .name = "pll0",
68 .parent = &ref_clk,
69 .pll_data = &pll0_data,
70 .flags = CLK_PLL,
71 .set_rate = da850_set_pll0rate,
72 };
73
74 static struct clk pll0_aux_clk = {
75 .name = "pll0_aux_clk",
76 .parent = &pll0_clk,
77 .flags = CLK_PLL | PRE_PLL,
78 };
79
80 static struct clk pll0_sysclk1 = {
81 .name = "pll0_sysclk1",
82 .parent = &pll0_clk,
83 .flags = CLK_PLL,
84 .div_reg = PLLDIV1,
85 };
86
87 static struct clk pll0_sysclk2 = {
88 .name = "pll0_sysclk2",
89 .parent = &pll0_clk,
90 .flags = CLK_PLL,
91 .div_reg = PLLDIV2,
92 };
93
94 static struct clk pll0_sysclk3 = {
95 .name = "pll0_sysclk3",
96 .parent = &pll0_clk,
97 .flags = CLK_PLL,
98 .div_reg = PLLDIV3,
99 .set_rate = davinci_set_sysclk_rate,
100 .maxrate = 100000000,
101 };
102
103 static struct clk pll0_sysclk4 = {
104 .name = "pll0_sysclk4",
105 .parent = &pll0_clk,
106 .flags = CLK_PLL,
107 .div_reg = PLLDIV4,
108 };
109
110 static struct clk pll0_sysclk5 = {
111 .name = "pll0_sysclk5",
112 .parent = &pll0_clk,
113 .flags = CLK_PLL,
114 .div_reg = PLLDIV5,
115 };
116
117 static struct clk pll0_sysclk6 = {
118 .name = "pll0_sysclk6",
119 .parent = &pll0_clk,
120 .flags = CLK_PLL,
121 .div_reg = PLLDIV6,
122 };
123
124 static struct clk pll0_sysclk7 = {
125 .name = "pll0_sysclk7",
126 .parent = &pll0_clk,
127 .flags = CLK_PLL,
128 .div_reg = PLLDIV7,
129 };
130
131 static struct pll_data pll1_data = {
132 .num = 2,
133 .phys_base = DA850_PLL1_BASE,
134 .flags = PLL_HAS_POSTDIV,
135 };
136
137 static struct clk pll1_clk = {
138 .name = "pll1",
139 .parent = &ref_clk,
140 .pll_data = &pll1_data,
141 .flags = CLK_PLL,
142 };
143
144 static struct clk pll1_aux_clk = {
145 .name = "pll1_aux_clk",
146 .parent = &pll1_clk,
147 .flags = CLK_PLL | PRE_PLL,
148 };
149
150 static struct clk pll1_sysclk2 = {
151 .name = "pll1_sysclk2",
152 .parent = &pll1_clk,
153 .flags = CLK_PLL,
154 .div_reg = PLLDIV2,
155 };
156
157 static struct clk pll1_sysclk3 = {
158 .name = "pll1_sysclk3",
159 .parent = &pll1_clk,
160 .flags = CLK_PLL,
161 .div_reg = PLLDIV3,
162 };
163
164 static struct clk i2c0_clk = {
165 .name = "i2c0",
166 .parent = &pll0_aux_clk,
167 };
168
169 static struct clk timerp64_0_clk = {
170 .name = "timer0",
171 .parent = &pll0_aux_clk,
172 };
173
174 static struct clk timerp64_1_clk = {
175 .name = "timer1",
176 .parent = &pll0_aux_clk,
177 };
178
179 static struct clk arm_rom_clk = {
180 .name = "arm_rom",
181 .parent = &pll0_sysclk2,
182 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
183 .flags = ALWAYS_ENABLED,
184 };
185
186 static struct clk tpcc0_clk = {
187 .name = "tpcc0",
188 .parent = &pll0_sysclk2,
189 .lpsc = DA8XX_LPSC0_TPCC,
190 .flags = ALWAYS_ENABLED | CLK_PSC,
191 };
192
193 static struct clk tptc0_clk = {
194 .name = "tptc0",
195 .parent = &pll0_sysclk2,
196 .lpsc = DA8XX_LPSC0_TPTC0,
197 .flags = ALWAYS_ENABLED,
198 };
199
200 static struct clk tptc1_clk = {
201 .name = "tptc1",
202 .parent = &pll0_sysclk2,
203 .lpsc = DA8XX_LPSC0_TPTC1,
204 .flags = ALWAYS_ENABLED,
205 };
206
207 static struct clk tpcc1_clk = {
208 .name = "tpcc1",
209 .parent = &pll0_sysclk2,
210 .lpsc = DA850_LPSC1_TPCC1,
211 .gpsc = 1,
212 .flags = CLK_PSC | ALWAYS_ENABLED,
213 };
214
215 static struct clk tptc2_clk = {
216 .name = "tptc2",
217 .parent = &pll0_sysclk2,
218 .lpsc = DA850_LPSC1_TPTC2,
219 .gpsc = 1,
220 .flags = ALWAYS_ENABLED,
221 };
222
223 static struct clk pruss_clk = {
224 .name = "pruss",
225 .parent = &pll0_sysclk2,
226 .lpsc = DA8XX_LPSC0_PRUSS,
227 };
228
229 static struct clk uart0_clk = {
230 .name = "uart0",
231 .parent = &pll0_sysclk2,
232 .lpsc = DA8XX_LPSC0_UART0,
233 };
234
235 static struct clk uart1_clk = {
236 .name = "uart1",
237 .parent = &pll0_sysclk2,
238 .lpsc = DA8XX_LPSC1_UART1,
239 .gpsc = 1,
240 .flags = DA850_CLK_ASYNC3,
241 };
242
243 static struct clk uart2_clk = {
244 .name = "uart2",
245 .parent = &pll0_sysclk2,
246 .lpsc = DA8XX_LPSC1_UART2,
247 .gpsc = 1,
248 .flags = DA850_CLK_ASYNC3,
249 };
250
251 static struct clk aintc_clk = {
252 .name = "aintc",
253 .parent = &pll0_sysclk4,
254 .lpsc = DA8XX_LPSC0_AINTC,
255 .flags = ALWAYS_ENABLED,
256 };
257
258 static struct clk gpio_clk = {
259 .name = "gpio",
260 .parent = &pll0_sysclk4,
261 .lpsc = DA8XX_LPSC1_GPIO,
262 .gpsc = 1,
263 };
264
265 static struct clk i2c1_clk = {
266 .name = "i2c1",
267 .parent = &pll0_sysclk4,
268 .lpsc = DA8XX_LPSC1_I2C,
269 .gpsc = 1,
270 };
271
272 static struct clk emif3_clk = {
273 .name = "emif3",
274 .parent = &pll0_sysclk5,
275 .lpsc = DA8XX_LPSC1_EMIF3C,
276 .gpsc = 1,
277 .flags = ALWAYS_ENABLED,
278 };
279
280 static struct clk arm_clk = {
281 .name = "arm",
282 .parent = &pll0_sysclk6,
283 .lpsc = DA8XX_LPSC0_ARM,
284 .flags = ALWAYS_ENABLED,
285 .set_rate = da850_set_armrate,
286 .round_rate = da850_round_armrate,
287 };
288
289 static struct clk rmii_clk = {
290 .name = "rmii",
291 .parent = &pll0_sysclk7,
292 };
293
294 static struct clk emac_clk = {
295 .name = "emac",
296 .parent = &pll0_sysclk4,
297 .lpsc = DA8XX_LPSC1_CPGMAC,
298 .gpsc = 1,
299 };
300
301 /*
302 * In order to avoid adding the emac_clk to the clock lookup table twice (and
303 * screwing up the linked list in the process) create a separate clock for
304 * mdio inheriting the rate from emac_clk.
305 */
306 static struct clk mdio_clk = {
307 .name = "mdio",
308 .parent = &emac_clk,
309 };
310
311 static struct clk mcasp_clk = {
312 .name = "mcasp",
313 .parent = &pll0_sysclk2,
314 .lpsc = DA8XX_LPSC1_McASP0,
315 .gpsc = 1,
316 .flags = DA850_CLK_ASYNC3,
317 };
318
319 static struct clk lcdc_clk = {
320 .name = "lcdc",
321 .parent = &pll0_sysclk2,
322 .lpsc = DA8XX_LPSC1_LCDC,
323 .gpsc = 1,
324 };
325
326 static struct clk mmcsd0_clk = {
327 .name = "mmcsd0",
328 .parent = &pll0_sysclk2,
329 .lpsc = DA8XX_LPSC0_MMC_SD,
330 };
331
332 static struct clk mmcsd1_clk = {
333 .name = "mmcsd1",
334 .parent = &pll0_sysclk2,
335 .lpsc = DA850_LPSC1_MMC_SD1,
336 .gpsc = 1,
337 };
338
339 static struct clk aemif_clk = {
340 .name = "aemif",
341 .parent = &pll0_sysclk3,
342 .lpsc = DA8XX_LPSC0_EMIF25,
343 .flags = ALWAYS_ENABLED,
344 };
345
346 static struct clk usb11_clk = {
347 .name = "usb11",
348 .parent = &pll0_sysclk4,
349 .lpsc = DA8XX_LPSC1_USB11,
350 .gpsc = 1,
351 };
352
353 static struct clk usb20_clk = {
354 .name = "usb20",
355 .parent = &pll0_sysclk2,
356 .lpsc = DA8XX_LPSC1_USB20,
357 .gpsc = 1,
358 };
359
360 static struct clk spi0_clk = {
361 .name = "spi0",
362 .parent = &pll0_sysclk2,
363 .lpsc = DA8XX_LPSC0_SPI0,
364 };
365
366 static struct clk spi1_clk = {
367 .name = "spi1",
368 .parent = &pll0_sysclk2,
369 .lpsc = DA8XX_LPSC1_SPI1,
370 .gpsc = 1,
371 .flags = DA850_CLK_ASYNC3,
372 };
373
374 static struct clk vpif_clk = {
375 .name = "vpif",
376 .parent = &pll0_sysclk2,
377 .lpsc = DA850_LPSC1_VPIF,
378 .gpsc = 1,
379 };
380
381 static struct clk sata_clk = {
382 .name = "sata",
383 .parent = &pll0_sysclk2,
384 .lpsc = DA850_LPSC1_SATA,
385 .gpsc = 1,
386 .flags = PSC_FORCE,
387 };
388
389 static struct clk dsp_clk = {
390 .name = "dsp",
391 .parent = &pll0_sysclk1,
392 .domain = DAVINCI_GPSC_DSPDOMAIN,
393 .lpsc = DA8XX_LPSC0_GEM,
394 .flags = PSC_LRST | PSC_FORCE,
395 };
396
397 static struct clk ehrpwm_clk = {
398 .name = "ehrpwm",
399 .parent = &pll0_sysclk2,
400 .lpsc = DA8XX_LPSC1_PWM,
401 .gpsc = 1,
402 .flags = DA850_CLK_ASYNC3,
403 };
404
405 #define DA8XX_EHRPWM_TBCLKSYNC BIT(12)
406
ehrpwm_tblck_enable(struct clk * clk)407 static void ehrpwm_tblck_enable(struct clk *clk)
408 {
409 u32 val;
410
411 val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
412 val |= DA8XX_EHRPWM_TBCLKSYNC;
413 writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
414 }
415
ehrpwm_tblck_disable(struct clk * clk)416 static void ehrpwm_tblck_disable(struct clk *clk)
417 {
418 u32 val;
419
420 val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
421 val &= ~DA8XX_EHRPWM_TBCLKSYNC;
422 writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
423 }
424
425 static struct clk ehrpwm_tbclk = {
426 .name = "ehrpwm_tbclk",
427 .parent = &ehrpwm_clk,
428 .clk_enable = ehrpwm_tblck_enable,
429 .clk_disable = ehrpwm_tblck_disable,
430 };
431
432 static struct clk ecap_clk = {
433 .name = "ecap",
434 .parent = &pll0_sysclk2,
435 .lpsc = DA8XX_LPSC1_ECAP,
436 .gpsc = 1,
437 .flags = DA850_CLK_ASYNC3,
438 };
439
440 static struct clk_lookup da850_clks[] = {
441 CLK(NULL, "ref", &ref_clk),
442 CLK(NULL, "pll0", &pll0_clk),
443 CLK(NULL, "pll0_aux", &pll0_aux_clk),
444 CLK(NULL, "pll0_sysclk1", &pll0_sysclk1),
445 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
446 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
447 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
448 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
449 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
450 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
451 CLK(NULL, "pll1", &pll1_clk),
452 CLK(NULL, "pll1_aux", &pll1_aux_clk),
453 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
454 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
455 CLK("i2c_davinci.1", NULL, &i2c0_clk),
456 CLK(NULL, "timer0", &timerp64_0_clk),
457 CLK("davinci-wdt", NULL, &timerp64_1_clk),
458 CLK(NULL, "arm_rom", &arm_rom_clk),
459 CLK(NULL, "tpcc0", &tpcc0_clk),
460 CLK(NULL, "tptc0", &tptc0_clk),
461 CLK(NULL, "tptc1", &tptc1_clk),
462 CLK(NULL, "tpcc1", &tpcc1_clk),
463 CLK(NULL, "tptc2", &tptc2_clk),
464 CLK("pruss_uio", "pruss", &pruss_clk),
465 CLK("serial8250.0", NULL, &uart0_clk),
466 CLK("serial8250.1", NULL, &uart1_clk),
467 CLK("serial8250.2", NULL, &uart2_clk),
468 CLK(NULL, "aintc", &aintc_clk),
469 CLK(NULL, "gpio", &gpio_clk),
470 CLK("i2c_davinci.2", NULL, &i2c1_clk),
471 CLK(NULL, "emif3", &emif3_clk),
472 CLK(NULL, "arm", &arm_clk),
473 CLK(NULL, "rmii", &rmii_clk),
474 CLK("davinci_emac.1", NULL, &emac_clk),
475 CLK("davinci_mdio.0", "fck", &mdio_clk),
476 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
477 CLK("da8xx_lcdc.0", "fck", &lcdc_clk),
478 CLK("da830-mmc.0", NULL, &mmcsd0_clk),
479 CLK("da830-mmc.1", NULL, &mmcsd1_clk),
480 CLK(NULL, "aemif", &aemif_clk),
481 CLK(NULL, "usb11", &usb11_clk),
482 CLK(NULL, "usb20", &usb20_clk),
483 CLK("spi_davinci.0", NULL, &spi0_clk),
484 CLK("spi_davinci.1", NULL, &spi1_clk),
485 CLK("vpif", NULL, &vpif_clk),
486 CLK("ahci_da850", NULL, &sata_clk),
487 CLK("davinci-rproc.0", NULL, &dsp_clk),
488 CLK("ehrpwm", "fck", &ehrpwm_clk),
489 CLK("ehrpwm", "tbclk", &ehrpwm_tbclk),
490 CLK("ecap", "fck", &ecap_clk),
491 CLK(NULL, NULL, NULL),
492 };
493
494 /*
495 * Device specific mux setup
496 *
497 * soc description mux mode mode mux dbg
498 * reg offset mask mode
499 */
500 static const struct mux_config da850_pins[] = {
501 #ifdef CONFIG_DAVINCI_MUX
502 /* UART0 function */
503 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
504 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
505 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
506 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
507 /* UART1 function */
508 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
509 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
510 /* UART2 function */
511 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
512 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
513 /* I2C1 function */
514 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
515 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
516 /* I2C0 function */
517 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
518 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
519 /* EMAC function */
520 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
521 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
522 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
523 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
524 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
525 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
526 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
527 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
528 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
529 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
530 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
531 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
532 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
533 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
534 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
535 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
536 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
537 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
538 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
539 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
540 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
541 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
542 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
543 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
544 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
545 /* McASP function */
546 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
547 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
548 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
549 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
550 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
551 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
552 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
553 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
554 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
555 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
556 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
557 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
558 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
559 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
560 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
561 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
562 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
563 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
564 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
565 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
566 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
567 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
568 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
569 /* LCD function */
570 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
571 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
572 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
573 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
574 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
575 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
576 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
577 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
578 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
579 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
580 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
581 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
582 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
583 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
584 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
585 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
586 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
587 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
588 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
589 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
590 /* MMC/SD0 function */
591 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
592 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
593 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
594 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
595 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
596 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
597 /* MMC/SD1 function */
598 MUX_CFG(DA850, MMCSD1_DAT_0, 18, 8, 15, 2, false)
599 MUX_CFG(DA850, MMCSD1_DAT_1, 19, 16, 15, 2, false)
600 MUX_CFG(DA850, MMCSD1_DAT_2, 19, 12, 15, 2, false)
601 MUX_CFG(DA850, MMCSD1_DAT_3, 19, 8, 15, 2, false)
602 MUX_CFG(DA850, MMCSD1_CLK, 18, 12, 15, 2, false)
603 MUX_CFG(DA850, MMCSD1_CMD, 18, 16, 15, 2, false)
604 /* EMIF2.5/EMIFA function */
605 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
606 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
607 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
608 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
609 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
610 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
611 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
612 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
613 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
614 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
615 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
616 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
617 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
618 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
619 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
620 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
621 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
622 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
623 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
624 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
625 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
626 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
627 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
628 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
629 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
630 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
631 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
632 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
633 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
634 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
635 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
636 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
637 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
638 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
639 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
640 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
641 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
642 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
643 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
644 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
645 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
646 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
647 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
648 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
649 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
650 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
651 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
652 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
653 /* GPIO function */
654 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false)
655 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
656 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
657 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
658 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false)
659 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false)
660 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
661 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
662 MUX_CFG(DA850, GPIO6_9, 13, 24, 15, 8, false)
663 MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false)
664 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false)
665 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
666 /* VPIF Capture */
667 MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false)
668 MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false)
669 MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false)
670 MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false)
671 MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false)
672 MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false)
673 MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false)
674 MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false)
675 MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false)
676 MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false)
677 MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false)
678 MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false)
679 MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false)
680 MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false)
681 MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false)
682 MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false)
683 MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false)
684 MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false)
685 MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false)
686 MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false)
687 /* VPIF Display */
688 MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false)
689 MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false)
690 MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false)
691 MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false)
692 MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false)
693 MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false)
694 MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false)
695 MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false)
696 MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false)
697 MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false)
698 MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false)
699 MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false)
700 MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false)
701 MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false)
702 MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false)
703 MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false)
704 MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false)
705 MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false)
706 #endif
707 };
708
709 const short da850_i2c0_pins[] __initconst = {
710 DA850_I2C0_SDA, DA850_I2C0_SCL,
711 -1
712 };
713
714 const short da850_i2c1_pins[] __initconst = {
715 DA850_I2C1_SCL, DA850_I2C1_SDA,
716 -1
717 };
718
719 const short da850_lcdcntl_pins[] __initconst = {
720 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
721 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
722 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
723 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
724 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
725 -1
726 };
727
728 const short da850_vpif_capture_pins[] __initconst = {
729 DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
730 DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
731 DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
732 DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
733 DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
734 DA850_VPIF_CLKIN3,
735 -1
736 };
737
738 const short da850_vpif_display_pins[] __initconst = {
739 DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
740 DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
741 DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
742 DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
743 DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
744 DA850_VPIF_CLKO3,
745 -1
746 };
747
748 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
749 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
750 [IRQ_DA8XX_COMMTX] = 7,
751 [IRQ_DA8XX_COMMRX] = 7,
752 [IRQ_DA8XX_NINT] = 7,
753 [IRQ_DA8XX_EVTOUT0] = 7,
754 [IRQ_DA8XX_EVTOUT1] = 7,
755 [IRQ_DA8XX_EVTOUT2] = 7,
756 [IRQ_DA8XX_EVTOUT3] = 7,
757 [IRQ_DA8XX_EVTOUT4] = 7,
758 [IRQ_DA8XX_EVTOUT5] = 7,
759 [IRQ_DA8XX_EVTOUT6] = 7,
760 [IRQ_DA8XX_EVTOUT7] = 7,
761 [IRQ_DA8XX_CCINT0] = 7,
762 [IRQ_DA8XX_CCERRINT] = 7,
763 [IRQ_DA8XX_TCERRINT0] = 7,
764 [IRQ_DA8XX_AEMIFINT] = 7,
765 [IRQ_DA8XX_I2CINT0] = 7,
766 [IRQ_DA8XX_MMCSDINT0] = 7,
767 [IRQ_DA8XX_MMCSDINT1] = 7,
768 [IRQ_DA8XX_ALLINT0] = 7,
769 [IRQ_DA8XX_RTC] = 7,
770 [IRQ_DA8XX_SPINT0] = 7,
771 [IRQ_DA8XX_TINT12_0] = 7,
772 [IRQ_DA8XX_TINT34_0] = 7,
773 [IRQ_DA8XX_TINT12_1] = 7,
774 [IRQ_DA8XX_TINT34_1] = 7,
775 [IRQ_DA8XX_UARTINT0] = 7,
776 [IRQ_DA8XX_KEYMGRINT] = 7,
777 [IRQ_DA850_MPUADDRERR0] = 7,
778 [IRQ_DA8XX_CHIPINT0] = 7,
779 [IRQ_DA8XX_CHIPINT1] = 7,
780 [IRQ_DA8XX_CHIPINT2] = 7,
781 [IRQ_DA8XX_CHIPINT3] = 7,
782 [IRQ_DA8XX_TCERRINT1] = 7,
783 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
784 [IRQ_DA8XX_C0_RX_PULSE] = 7,
785 [IRQ_DA8XX_C0_TX_PULSE] = 7,
786 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
787 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
788 [IRQ_DA8XX_C1_RX_PULSE] = 7,
789 [IRQ_DA8XX_C1_TX_PULSE] = 7,
790 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
791 [IRQ_DA8XX_MEMERR] = 7,
792 [IRQ_DA8XX_GPIO0] = 7,
793 [IRQ_DA8XX_GPIO1] = 7,
794 [IRQ_DA8XX_GPIO2] = 7,
795 [IRQ_DA8XX_GPIO3] = 7,
796 [IRQ_DA8XX_GPIO4] = 7,
797 [IRQ_DA8XX_GPIO5] = 7,
798 [IRQ_DA8XX_GPIO6] = 7,
799 [IRQ_DA8XX_GPIO7] = 7,
800 [IRQ_DA8XX_GPIO8] = 7,
801 [IRQ_DA8XX_I2CINT1] = 7,
802 [IRQ_DA8XX_LCDINT] = 7,
803 [IRQ_DA8XX_UARTINT1] = 7,
804 [IRQ_DA8XX_MCASPINT] = 7,
805 [IRQ_DA8XX_ALLINT1] = 7,
806 [IRQ_DA8XX_SPINT1] = 7,
807 [IRQ_DA8XX_UHPI_INT1] = 7,
808 [IRQ_DA8XX_USB_INT] = 7,
809 [IRQ_DA8XX_IRQN] = 7,
810 [IRQ_DA8XX_RWAKEUP] = 7,
811 [IRQ_DA8XX_UARTINT2] = 7,
812 [IRQ_DA8XX_DFTSSINT] = 7,
813 [IRQ_DA8XX_EHRPWM0] = 7,
814 [IRQ_DA8XX_EHRPWM0TZ] = 7,
815 [IRQ_DA8XX_EHRPWM1] = 7,
816 [IRQ_DA8XX_EHRPWM1TZ] = 7,
817 [IRQ_DA850_SATAINT] = 7,
818 [IRQ_DA850_TINTALL_2] = 7,
819 [IRQ_DA8XX_ECAP0] = 7,
820 [IRQ_DA8XX_ECAP1] = 7,
821 [IRQ_DA8XX_ECAP2] = 7,
822 [IRQ_DA850_MMCSDINT0_1] = 7,
823 [IRQ_DA850_MMCSDINT1_1] = 7,
824 [IRQ_DA850_T12CMPINT0_2] = 7,
825 [IRQ_DA850_T12CMPINT1_2] = 7,
826 [IRQ_DA850_T12CMPINT2_2] = 7,
827 [IRQ_DA850_T12CMPINT3_2] = 7,
828 [IRQ_DA850_T12CMPINT4_2] = 7,
829 [IRQ_DA850_T12CMPINT5_2] = 7,
830 [IRQ_DA850_T12CMPINT6_2] = 7,
831 [IRQ_DA850_T12CMPINT7_2] = 7,
832 [IRQ_DA850_T12CMPINT0_3] = 7,
833 [IRQ_DA850_T12CMPINT1_3] = 7,
834 [IRQ_DA850_T12CMPINT2_3] = 7,
835 [IRQ_DA850_T12CMPINT3_3] = 7,
836 [IRQ_DA850_T12CMPINT4_3] = 7,
837 [IRQ_DA850_T12CMPINT5_3] = 7,
838 [IRQ_DA850_T12CMPINT6_3] = 7,
839 [IRQ_DA850_T12CMPINT7_3] = 7,
840 [IRQ_DA850_RPIINT] = 7,
841 [IRQ_DA850_VPIFINT] = 7,
842 [IRQ_DA850_CCINT1] = 7,
843 [IRQ_DA850_CCERRINT1] = 7,
844 [IRQ_DA850_TCERRINT2] = 7,
845 [IRQ_DA850_TINTALL_3] = 7,
846 [IRQ_DA850_MCBSP0RINT] = 7,
847 [IRQ_DA850_MCBSP0XINT] = 7,
848 [IRQ_DA850_MCBSP1RINT] = 7,
849 [IRQ_DA850_MCBSP1XINT] = 7,
850 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
851 };
852
853 static struct map_desc da850_io_desc[] = {
854 {
855 .virtual = IO_VIRT,
856 .pfn = __phys_to_pfn(IO_PHYS),
857 .length = IO_SIZE,
858 .type = MT_DEVICE
859 },
860 {
861 .virtual = DA8XX_CP_INTC_VIRT,
862 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
863 .length = DA8XX_CP_INTC_SIZE,
864 .type = MT_DEVICE
865 },
866 };
867
868 static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
869
870 /* Contents of JTAG ID register used to identify exact cpu type */
871 static struct davinci_id da850_ids[] = {
872 {
873 .variant = 0x0,
874 .part_no = 0xb7d1,
875 .manufacturer = 0x017, /* 0x02f >> 1 */
876 .cpu_id = DAVINCI_CPU_ID_DA850,
877 .name = "da850/omap-l138",
878 },
879 {
880 .variant = 0x1,
881 .part_no = 0xb7d1,
882 .manufacturer = 0x017, /* 0x02f >> 1 */
883 .cpu_id = DAVINCI_CPU_ID_DA850,
884 .name = "da850/omap-l138/am18x",
885 },
886 };
887
888 static struct davinci_timer_instance da850_timer_instance[4] = {
889 {
890 .base = DA8XX_TIMER64P0_BASE,
891 .bottom_irq = IRQ_DA8XX_TINT12_0,
892 .top_irq = IRQ_DA8XX_TINT34_0,
893 },
894 {
895 .base = DA8XX_TIMER64P1_BASE,
896 .bottom_irq = IRQ_DA8XX_TINT12_1,
897 .top_irq = IRQ_DA8XX_TINT34_1,
898 },
899 {
900 .base = DA850_TIMER64P2_BASE,
901 .bottom_irq = IRQ_DA850_TINT12_2,
902 .top_irq = IRQ_DA850_TINT34_2,
903 },
904 {
905 .base = DA850_TIMER64P3_BASE,
906 .bottom_irq = IRQ_DA850_TINT12_3,
907 .top_irq = IRQ_DA850_TINT34_3,
908 },
909 };
910
911 /*
912 * T0_BOT: Timer 0, bottom : Used for clock_event
913 * T0_TOP: Timer 0, top : Used for clocksource
914 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
915 */
916 static struct davinci_timer_info da850_timer_info = {
917 .timers = da850_timer_instance,
918 .clockevent_id = T0_BOT,
919 .clocksource_id = T0_TOP,
920 };
921
da850_set_async3_src(int pllnum)922 static void da850_set_async3_src(int pllnum)
923 {
924 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
925 struct clk_lookup *c;
926 unsigned int v;
927 int ret;
928
929 for (c = da850_clks; c->clk; c++) {
930 clk = c->clk;
931 if (clk->flags & DA850_CLK_ASYNC3) {
932 ret = clk_set_parent(clk, newparent);
933 WARN(ret, "DA850: unable to re-parent clock %s",
934 clk->name);
935 }
936 }
937
938 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
939 if (pllnum)
940 v |= CFGCHIP3_ASYNC3_CLKSRC;
941 else
942 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
943 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
944 }
945
946 #ifdef CONFIG_CPU_FREQ
947 /*
948 * Notes:
949 * According to the TRM, minimum PLLM results in maximum power savings.
950 * The OPP definitions below should keep the PLLM as low as possible.
951 *
952 * The output of the PLLM must be between 300 to 600 MHz.
953 */
954 struct da850_opp {
955 unsigned int freq; /* in KHz */
956 unsigned int prediv;
957 unsigned int mult;
958 unsigned int postdiv;
959 unsigned int cvdd_min; /* in uV */
960 unsigned int cvdd_max; /* in uV */
961 };
962
963 static const struct da850_opp da850_opp_456 = {
964 .freq = 456000,
965 .prediv = 1,
966 .mult = 19,
967 .postdiv = 1,
968 .cvdd_min = 1300000,
969 .cvdd_max = 1350000,
970 };
971
972 static const struct da850_opp da850_opp_408 = {
973 .freq = 408000,
974 .prediv = 1,
975 .mult = 17,
976 .postdiv = 1,
977 .cvdd_min = 1300000,
978 .cvdd_max = 1350000,
979 };
980
981 static const struct da850_opp da850_opp_372 = {
982 .freq = 372000,
983 .prediv = 2,
984 .mult = 31,
985 .postdiv = 1,
986 .cvdd_min = 1200000,
987 .cvdd_max = 1320000,
988 };
989
990 static const struct da850_opp da850_opp_300 = {
991 .freq = 300000,
992 .prediv = 1,
993 .mult = 25,
994 .postdiv = 2,
995 .cvdd_min = 1200000,
996 .cvdd_max = 1320000,
997 };
998
999 static const struct da850_opp da850_opp_200 = {
1000 .freq = 200000,
1001 .prediv = 1,
1002 .mult = 25,
1003 .postdiv = 3,
1004 .cvdd_min = 1100000,
1005 .cvdd_max = 1160000,
1006 };
1007
1008 static const struct da850_opp da850_opp_96 = {
1009 .freq = 96000,
1010 .prediv = 1,
1011 .mult = 20,
1012 .postdiv = 5,
1013 .cvdd_min = 1000000,
1014 .cvdd_max = 1050000,
1015 };
1016
1017 #define OPP(freq) \
1018 { \
1019 .driver_data = (unsigned int) &da850_opp_##freq, \
1020 .frequency = freq * 1000, \
1021 }
1022
1023 static struct cpufreq_frequency_table da850_freq_table[] = {
1024 OPP(456),
1025 OPP(408),
1026 OPP(372),
1027 OPP(300),
1028 OPP(200),
1029 OPP(96),
1030 {
1031 .driver_data = 0,
1032 .frequency = CPUFREQ_TABLE_END,
1033 },
1034 };
1035
1036 #ifdef CONFIG_REGULATOR
1037 static int da850_set_voltage(unsigned int index);
1038 static int da850_regulator_init(void);
1039 #endif
1040
1041 static struct davinci_cpufreq_config cpufreq_info = {
1042 .freq_table = da850_freq_table,
1043 #ifdef CONFIG_REGULATOR
1044 .init = da850_regulator_init,
1045 .set_voltage = da850_set_voltage,
1046 #endif
1047 };
1048
1049 #ifdef CONFIG_REGULATOR
1050 static struct regulator *cvdd;
1051
da850_set_voltage(unsigned int index)1052 static int da850_set_voltage(unsigned int index)
1053 {
1054 struct da850_opp *opp;
1055
1056 if (!cvdd)
1057 return -ENODEV;
1058
1059 opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
1060
1061 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
1062 }
1063
da850_regulator_init(void)1064 static int da850_regulator_init(void)
1065 {
1066 cvdd = regulator_get(NULL, "cvdd");
1067 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
1068 " voltage scaling unsupported\n")) {
1069 return PTR_ERR(cvdd);
1070 }
1071
1072 return 0;
1073 }
1074 #endif
1075
1076 static struct platform_device da850_cpufreq_device = {
1077 .name = "cpufreq-davinci",
1078 .dev = {
1079 .platform_data = &cpufreq_info,
1080 },
1081 .id = -1,
1082 };
1083
1084 unsigned int da850_max_speed = 300000;
1085
da850_register_cpufreq(char * async_clk)1086 int da850_register_cpufreq(char *async_clk)
1087 {
1088 int i;
1089
1090 /* cpufreq driver can help keep an "async" clock constant */
1091 if (async_clk)
1092 clk_add_alias("async", da850_cpufreq_device.name,
1093 async_clk, NULL);
1094 for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
1095 if (da850_freq_table[i].frequency <= da850_max_speed) {
1096 cpufreq_info.freq_table = &da850_freq_table[i];
1097 break;
1098 }
1099 }
1100
1101 return platform_device_register(&da850_cpufreq_device);
1102 }
1103
da850_round_armrate(struct clk * clk,unsigned long rate)1104 static int da850_round_armrate(struct clk *clk, unsigned long rate)
1105 {
1106 int ret = 0, diff;
1107 unsigned int best = (unsigned int) -1;
1108 struct cpufreq_frequency_table *table = cpufreq_info.freq_table;
1109 struct cpufreq_frequency_table *pos;
1110
1111 rate /= 1000; /* convert to kHz */
1112
1113 cpufreq_for_each_entry(pos, table) {
1114 diff = pos->frequency - rate;
1115 if (diff < 0)
1116 diff = -diff;
1117
1118 if (diff < best) {
1119 best = diff;
1120 ret = pos->frequency;
1121 }
1122 }
1123
1124 return ret * 1000;
1125 }
1126
da850_set_armrate(struct clk * clk,unsigned long index)1127 static int da850_set_armrate(struct clk *clk, unsigned long index)
1128 {
1129 struct clk *pllclk = &pll0_clk;
1130
1131 return clk_set_rate(pllclk, index);
1132 }
1133
da850_set_pll0rate(struct clk * clk,unsigned long index)1134 static int da850_set_pll0rate(struct clk *clk, unsigned long index)
1135 {
1136 unsigned int prediv, mult, postdiv;
1137 struct da850_opp *opp;
1138 struct pll_data *pll = clk->pll_data;
1139 int ret;
1140
1141 opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
1142 prediv = opp->prediv;
1143 mult = opp->mult;
1144 postdiv = opp->postdiv;
1145
1146 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1147 if (WARN_ON(ret))
1148 return ret;
1149
1150 return 0;
1151 }
1152 #else
da850_register_cpufreq(char * async_clk)1153 int __init da850_register_cpufreq(char *async_clk)
1154 {
1155 return 0;
1156 }
1157
da850_set_armrate(struct clk * clk,unsigned long rate)1158 static int da850_set_armrate(struct clk *clk, unsigned long rate)
1159 {
1160 return -EINVAL;
1161 }
1162
da850_set_pll0rate(struct clk * clk,unsigned long armrate)1163 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
1164 {
1165 return -EINVAL;
1166 }
1167
da850_round_armrate(struct clk * clk,unsigned long rate)1168 static int da850_round_armrate(struct clk *clk, unsigned long rate)
1169 {
1170 return clk->rate;
1171 }
1172 #endif
1173
da850_register_pm(struct platform_device * pdev)1174 int __init da850_register_pm(struct platform_device *pdev)
1175 {
1176 int ret;
1177 struct davinci_pm_config *pdata = pdev->dev.platform_data;
1178
1179 ret = davinci_cfg_reg(DA850_RTC_ALARM);
1180 if (ret)
1181 return ret;
1182
1183 pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
1184 pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
1185 pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
1186
1187 pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
1188 if (!pdata->cpupll_reg_base)
1189 return -ENOMEM;
1190
1191 pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
1192 if (!pdata->ddrpll_reg_base) {
1193 ret = -ENOMEM;
1194 goto no_ddrpll_mem;
1195 }
1196
1197 pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
1198 if (!pdata->ddrpsc_reg_base) {
1199 ret = -ENOMEM;
1200 goto no_ddrpsc_mem;
1201 }
1202
1203 return platform_device_register(pdev);
1204
1205 no_ddrpsc_mem:
1206 iounmap(pdata->ddrpll_reg_base);
1207 no_ddrpll_mem:
1208 iounmap(pdata->cpupll_reg_base);
1209 return ret;
1210 }
1211
1212 /* VPIF resource, platform data */
1213 static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
1214
1215 static struct resource da850_vpif_resource[] = {
1216 {
1217 .start = DA8XX_VPIF_BASE,
1218 .end = DA8XX_VPIF_BASE + 0xfff,
1219 .flags = IORESOURCE_MEM,
1220 }
1221 };
1222
1223 static struct platform_device da850_vpif_dev = {
1224 .name = "vpif",
1225 .id = -1,
1226 .dev = {
1227 .dma_mask = &da850_vpif_dma_mask,
1228 .coherent_dma_mask = DMA_BIT_MASK(32),
1229 },
1230 .resource = da850_vpif_resource,
1231 .num_resources = ARRAY_SIZE(da850_vpif_resource),
1232 };
1233
1234 static struct resource da850_vpif_display_resource[] = {
1235 {
1236 .start = IRQ_DA850_VPIFINT,
1237 .end = IRQ_DA850_VPIFINT,
1238 .flags = IORESOURCE_IRQ,
1239 },
1240 };
1241
1242 static struct platform_device da850_vpif_display_dev = {
1243 .name = "vpif_display",
1244 .id = -1,
1245 .dev = {
1246 .dma_mask = &da850_vpif_dma_mask,
1247 .coherent_dma_mask = DMA_BIT_MASK(32),
1248 },
1249 .resource = da850_vpif_display_resource,
1250 .num_resources = ARRAY_SIZE(da850_vpif_display_resource),
1251 };
1252
1253 static struct resource da850_vpif_capture_resource[] = {
1254 {
1255 .start = IRQ_DA850_VPIFINT,
1256 .end = IRQ_DA850_VPIFINT,
1257 .flags = IORESOURCE_IRQ,
1258 },
1259 {
1260 .start = IRQ_DA850_VPIFINT,
1261 .end = IRQ_DA850_VPIFINT,
1262 .flags = IORESOURCE_IRQ,
1263 },
1264 };
1265
1266 static struct platform_device da850_vpif_capture_dev = {
1267 .name = "vpif_capture",
1268 .id = -1,
1269 .dev = {
1270 .dma_mask = &da850_vpif_dma_mask,
1271 .coherent_dma_mask = DMA_BIT_MASK(32),
1272 },
1273 .resource = da850_vpif_capture_resource,
1274 .num_resources = ARRAY_SIZE(da850_vpif_capture_resource),
1275 };
1276
da850_register_vpif(void)1277 int __init da850_register_vpif(void)
1278 {
1279 return platform_device_register(&da850_vpif_dev);
1280 }
1281
da850_register_vpif_display(struct vpif_display_config * display_config)1282 int __init da850_register_vpif_display(struct vpif_display_config
1283 *display_config)
1284 {
1285 da850_vpif_display_dev.dev.platform_data = display_config;
1286 return platform_device_register(&da850_vpif_display_dev);
1287 }
1288
da850_register_vpif_capture(struct vpif_capture_config * capture_config)1289 int __init da850_register_vpif_capture(struct vpif_capture_config
1290 *capture_config)
1291 {
1292 da850_vpif_capture_dev.dev.platform_data = capture_config;
1293 return platform_device_register(&da850_vpif_capture_dev);
1294 }
1295
1296 static struct davinci_gpio_platform_data da850_gpio_platform_data = {
1297 .ngpio = 144,
1298 };
1299
da850_register_gpio(void)1300 int __init da850_register_gpio(void)
1301 {
1302 return da8xx_register_gpio(&da850_gpio_platform_data);
1303 }
1304
1305 static struct davinci_soc_info davinci_soc_info_da850 = {
1306 .io_desc = da850_io_desc,
1307 .io_desc_num = ARRAY_SIZE(da850_io_desc),
1308 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
1309 .ids = da850_ids,
1310 .ids_num = ARRAY_SIZE(da850_ids),
1311 .cpu_clks = da850_clks,
1312 .psc_bases = da850_psc_bases,
1313 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
1314 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
1315 .pinmux_pins = da850_pins,
1316 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
1317 .intc_base = DA8XX_CP_INTC_BASE,
1318 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1319 .intc_irq_prios = da850_default_priorities,
1320 .intc_irq_num = DA850_N_CP_INTC_IRQ,
1321 .timer_info = &da850_timer_info,
1322 .emac_pdata = &da8xx_emac_pdata,
1323 .sram_dma = DA8XX_SHARED_RAM_BASE,
1324 .sram_len = SZ_128K,
1325 };
1326
da850_init(void)1327 void __init da850_init(void)
1328 {
1329 unsigned int v;
1330
1331 davinci_common_init(&davinci_soc_info_da850);
1332
1333 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1334 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1335 return;
1336
1337 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1338 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
1339 return;
1340
1341 /*
1342 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1343 * This helps keeping the peripherals on this domain insulated
1344 * from CPU frequency changes caused by DVFS. The firmware sets
1345 * both PLL0 and PLL1 to the same frequency so, there should not
1346 * be any noticeable change even in non-DVFS use cases.
1347 */
1348 da850_set_async3_src(1);
1349
1350 /* Unlock writing to PLL0 registers */
1351 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1352 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1353 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1354
1355 /* Unlock writing to PLL1 registers */
1356 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1357 v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1358 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1359 }
1360