1 /*
2 * DA8XX/OMAP L1XX platform device data
3 *
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-contiguous.h>
16 #include <linux/serial_8250.h>
17 #include <linux/ahci_platform.h>
18 #include <linux/clk.h>
19 #include <linux/reboot.h>
20
21 #include <mach/cputype.h>
22 #include <mach/common.h>
23 #include <mach/time.h>
24 #include <mach/da8xx.h>
25 #include <mach/cpuidle.h>
26 #include <mach/sram.h>
27
28 #include "clock.h"
29 #include "asp.h"
30
31 #define DA8XX_TPCC_BASE 0x01c00000
32 #define DA8XX_TPTC0_BASE 0x01c08000
33 #define DA8XX_TPTC1_BASE 0x01c08400
34 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
35 #define DA8XX_I2C0_BASE 0x01c22000
36 #define DA8XX_RTC_BASE 0x01c23000
37 #define DA8XX_PRUSS_MEM_BASE 0x01c30000
38 #define DA8XX_MMCSD0_BASE 0x01c40000
39 #define DA8XX_SPI0_BASE 0x01c41000
40 #define DA830_SPI1_BASE 0x01e12000
41 #define DA8XX_LCD_CNTRL_BASE 0x01e13000
42 #define DA850_SATA_BASE 0x01e18000
43 #define DA850_MMCSD1_BASE 0x01e1b000
44 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
45 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
46 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
47 #define DA8XX_EMAC_MDIO_BASE 0x01e24000
48 #define DA8XX_I2C1_BASE 0x01e28000
49 #define DA850_TPCC1_BASE 0x01e30000
50 #define DA850_TPTC2_BASE 0x01e38000
51 #define DA850_SPI1_BASE 0x01f0e000
52 #define DA8XX_DDR2_CTL_BASE 0xb0000000
53
54 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
55 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
56 #define DA8XX_EMAC_RAM_OFFSET 0x0000
57 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
58
59 #define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14)
60 #define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15)
61 #define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16)
62 #define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17)
63 #define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18)
64 #define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19)
65 #define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28)
66 #define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29)
67
68 void __iomem *da8xx_syscfg0_base;
69 void __iomem *da8xx_syscfg1_base;
70
71 static struct plat_serial8250_port da8xx_serial0_pdata[] = {
72 {
73 .mapbase = DA8XX_UART0_BASE,
74 .irq = IRQ_DA8XX_UARTINT0,
75 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
76 UPF_IOREMAP,
77 .iotype = UPIO_MEM,
78 .regshift = 2,
79 },
80 {
81 .flags = 0,
82 }
83 };
84 static struct plat_serial8250_port da8xx_serial1_pdata[] = {
85 {
86 .mapbase = DA8XX_UART1_BASE,
87 .irq = IRQ_DA8XX_UARTINT1,
88 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
89 UPF_IOREMAP,
90 .iotype = UPIO_MEM,
91 .regshift = 2,
92 },
93 {
94 .flags = 0,
95 }
96 };
97 static struct plat_serial8250_port da8xx_serial2_pdata[] = {
98 {
99 .mapbase = DA8XX_UART2_BASE,
100 .irq = IRQ_DA8XX_UARTINT2,
101 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
102 UPF_IOREMAP,
103 .iotype = UPIO_MEM,
104 .regshift = 2,
105 },
106 {
107 .flags = 0,
108 }
109 };
110
111 struct platform_device da8xx_serial_device[] = {
112 {
113 .name = "serial8250",
114 .id = PLAT8250_DEV_PLATFORM,
115 .dev = {
116 .platform_data = da8xx_serial0_pdata,
117 }
118 },
119 {
120 .name = "serial8250",
121 .id = PLAT8250_DEV_PLATFORM1,
122 .dev = {
123 .platform_data = da8xx_serial1_pdata,
124 }
125 },
126 {
127 .name = "serial8250",
128 .id = PLAT8250_DEV_PLATFORM2,
129 .dev = {
130 .platform_data = da8xx_serial2_pdata,
131 }
132 },
133 {
134 }
135 };
136
137 static s8 da8xx_queue_priority_mapping[][2] = {
138 /* {event queue no, Priority} */
139 {0, 3},
140 {1, 7},
141 {-1, -1}
142 };
143
144 static s8 da850_queue_priority_mapping[][2] = {
145 /* {event queue no, Priority} */
146 {0, 3},
147 {-1, -1}
148 };
149
150 static struct edma_soc_info da8xx_edma0_pdata = {
151 .queue_priority_mapping = da8xx_queue_priority_mapping,
152 .default_queue = EVENTQ_1,
153 };
154
155 static struct edma_soc_info da850_edma1_pdata = {
156 .queue_priority_mapping = da850_queue_priority_mapping,
157 .default_queue = EVENTQ_0,
158 };
159
160 static struct resource da8xx_edma0_resources[] = {
161 {
162 .name = "edma3_cc",
163 .start = DA8XX_TPCC_BASE,
164 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
165 .flags = IORESOURCE_MEM,
166 },
167 {
168 .name = "edma3_tc0",
169 .start = DA8XX_TPTC0_BASE,
170 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
171 .flags = IORESOURCE_MEM,
172 },
173 {
174 .name = "edma3_tc1",
175 .start = DA8XX_TPTC1_BASE,
176 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
177 .flags = IORESOURCE_MEM,
178 },
179 {
180 .name = "edma3_ccint",
181 .start = IRQ_DA8XX_CCINT0,
182 .flags = IORESOURCE_IRQ,
183 },
184 {
185 .name = "edma3_ccerrint",
186 .start = IRQ_DA8XX_CCERRINT,
187 .flags = IORESOURCE_IRQ,
188 },
189 };
190
191 static struct resource da850_edma1_resources[] = {
192 {
193 .name = "edma3_cc",
194 .start = DA850_TPCC1_BASE,
195 .end = DA850_TPCC1_BASE + SZ_32K - 1,
196 .flags = IORESOURCE_MEM,
197 },
198 {
199 .name = "edma3_tc0",
200 .start = DA850_TPTC2_BASE,
201 .end = DA850_TPTC2_BASE + SZ_1K - 1,
202 .flags = IORESOURCE_MEM,
203 },
204 {
205 .name = "edma3_ccint",
206 .start = IRQ_DA850_CCINT1,
207 .flags = IORESOURCE_IRQ,
208 },
209 {
210 .name = "edma3_ccerrint",
211 .start = IRQ_DA850_CCERRINT1,
212 .flags = IORESOURCE_IRQ,
213 },
214 };
215
216 static const struct platform_device_info da8xx_edma0_device __initconst = {
217 .name = "edma",
218 .id = 0,
219 .dma_mask = DMA_BIT_MASK(32),
220 .res = da8xx_edma0_resources,
221 .num_res = ARRAY_SIZE(da8xx_edma0_resources),
222 .data = &da8xx_edma0_pdata,
223 .size_data = sizeof(da8xx_edma0_pdata),
224 };
225
226 static const struct platform_device_info da850_edma1_device __initconst = {
227 .name = "edma",
228 .id = 1,
229 .dma_mask = DMA_BIT_MASK(32),
230 .res = da850_edma1_resources,
231 .num_res = ARRAY_SIZE(da850_edma1_resources),
232 .data = &da850_edma1_pdata,
233 .size_data = sizeof(da850_edma1_pdata),
234 };
235
da830_register_edma(struct edma_rsv_info * rsv)236 int __init da830_register_edma(struct edma_rsv_info *rsv)
237 {
238 struct platform_device *edma_pdev;
239
240 da8xx_edma0_pdata.rsv = rsv;
241
242 edma_pdev = platform_device_register_full(&da8xx_edma0_device);
243 return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
244 }
245
da850_register_edma(struct edma_rsv_info * rsv[2])246 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
247 {
248 struct platform_device *edma_pdev;
249
250 if (rsv) {
251 da8xx_edma0_pdata.rsv = rsv[0];
252 da850_edma1_pdata.rsv = rsv[1];
253 }
254
255 edma_pdev = platform_device_register_full(&da8xx_edma0_device);
256 if (IS_ERR(edma_pdev)) {
257 pr_warn("%s: Failed to register eDMA0\n", __func__);
258 return PTR_ERR(edma_pdev);
259 }
260 edma_pdev = platform_device_register_full(&da850_edma1_device);
261 return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
262 }
263
264 static struct resource da8xx_i2c_resources0[] = {
265 {
266 .start = DA8XX_I2C0_BASE,
267 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
268 .flags = IORESOURCE_MEM,
269 },
270 {
271 .start = IRQ_DA8XX_I2CINT0,
272 .end = IRQ_DA8XX_I2CINT0,
273 .flags = IORESOURCE_IRQ,
274 },
275 };
276
277 static struct platform_device da8xx_i2c_device0 = {
278 .name = "i2c_davinci",
279 .id = 1,
280 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
281 .resource = da8xx_i2c_resources0,
282 };
283
284 static struct resource da8xx_i2c_resources1[] = {
285 {
286 .start = DA8XX_I2C1_BASE,
287 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
288 .flags = IORESOURCE_MEM,
289 },
290 {
291 .start = IRQ_DA8XX_I2CINT1,
292 .end = IRQ_DA8XX_I2CINT1,
293 .flags = IORESOURCE_IRQ,
294 },
295 };
296
297 static struct platform_device da8xx_i2c_device1 = {
298 .name = "i2c_davinci",
299 .id = 2,
300 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
301 .resource = da8xx_i2c_resources1,
302 };
303
da8xx_register_i2c(int instance,struct davinci_i2c_platform_data * pdata)304 int __init da8xx_register_i2c(int instance,
305 struct davinci_i2c_platform_data *pdata)
306 {
307 struct platform_device *pdev;
308
309 if (instance == 0)
310 pdev = &da8xx_i2c_device0;
311 else if (instance == 1)
312 pdev = &da8xx_i2c_device1;
313 else
314 return -EINVAL;
315
316 pdev->dev.platform_data = pdata;
317 return platform_device_register(pdev);
318 }
319
320 static struct resource da8xx_watchdog_resources[] = {
321 {
322 .start = DA8XX_WDOG_BASE,
323 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
324 .flags = IORESOURCE_MEM,
325 },
326 };
327
328 static struct platform_device da8xx_wdt_device = {
329 .name = "davinci-wdt",
330 .id = -1,
331 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
332 .resource = da8xx_watchdog_resources,
333 };
334
da8xx_restart(enum reboot_mode mode,const char * cmd)335 void da8xx_restart(enum reboot_mode mode, const char *cmd)
336 {
337 struct device *dev;
338
339 dev = bus_find_device_by_name(&platform_bus_type, NULL, "davinci-wdt");
340 if (!dev) {
341 pr_err("%s: failed to find watchdog device\n", __func__);
342 return;
343 }
344
345 davinci_watchdog_reset(to_platform_device(dev));
346 }
347
da8xx_register_watchdog(void)348 int __init da8xx_register_watchdog(void)
349 {
350 return platform_device_register(&da8xx_wdt_device);
351 }
352
353 static struct resource da8xx_emac_resources[] = {
354 {
355 .start = DA8XX_EMAC_CPPI_PORT_BASE,
356 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
357 .flags = IORESOURCE_MEM,
358 },
359 {
360 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
361 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
362 .flags = IORESOURCE_IRQ,
363 },
364 {
365 .start = IRQ_DA8XX_C0_RX_PULSE,
366 .end = IRQ_DA8XX_C0_RX_PULSE,
367 .flags = IORESOURCE_IRQ,
368 },
369 {
370 .start = IRQ_DA8XX_C0_TX_PULSE,
371 .end = IRQ_DA8XX_C0_TX_PULSE,
372 .flags = IORESOURCE_IRQ,
373 },
374 {
375 .start = IRQ_DA8XX_C0_MISC_PULSE,
376 .end = IRQ_DA8XX_C0_MISC_PULSE,
377 .flags = IORESOURCE_IRQ,
378 },
379 };
380
381 struct emac_platform_data da8xx_emac_pdata = {
382 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
383 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
384 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
385 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
386 .version = EMAC_VERSION_2,
387 };
388
389 static struct platform_device da8xx_emac_device = {
390 .name = "davinci_emac",
391 .id = 1,
392 .dev = {
393 .platform_data = &da8xx_emac_pdata,
394 },
395 .num_resources = ARRAY_SIZE(da8xx_emac_resources),
396 .resource = da8xx_emac_resources,
397 };
398
399 static struct resource da8xx_mdio_resources[] = {
400 {
401 .start = DA8XX_EMAC_MDIO_BASE,
402 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
403 .flags = IORESOURCE_MEM,
404 },
405 };
406
407 static struct platform_device da8xx_mdio_device = {
408 .name = "davinci_mdio",
409 .id = 0,
410 .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
411 .resource = da8xx_mdio_resources,
412 };
413
da8xx_register_emac(void)414 int __init da8xx_register_emac(void)
415 {
416 int ret;
417
418 ret = platform_device_register(&da8xx_mdio_device);
419 if (ret < 0)
420 return ret;
421
422 return platform_device_register(&da8xx_emac_device);
423 }
424
425 static struct resource da830_mcasp1_resources[] = {
426 {
427 .name = "mpu",
428 .start = DAVINCI_DA830_MCASP1_REG_BASE,
429 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
430 .flags = IORESOURCE_MEM,
431 },
432 /* TX event */
433 {
434 .name = "tx",
435 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
436 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
437 .flags = IORESOURCE_DMA,
438 },
439 /* RX event */
440 {
441 .name = "rx",
442 .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
443 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
444 .flags = IORESOURCE_DMA,
445 },
446 {
447 .name = "common",
448 .start = IRQ_DA8XX_MCASPINT,
449 .flags = IORESOURCE_IRQ,
450 },
451 };
452
453 static struct platform_device da830_mcasp1_device = {
454 .name = "davinci-mcasp",
455 .id = 1,
456 .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
457 .resource = da830_mcasp1_resources,
458 };
459
460 static struct resource da830_mcasp2_resources[] = {
461 {
462 .name = "mpu",
463 .start = DAVINCI_DA830_MCASP2_REG_BASE,
464 .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
465 .flags = IORESOURCE_MEM,
466 },
467 /* TX event */
468 {
469 .name = "tx",
470 .start = DAVINCI_DA830_DMA_MCASP2_AXEVT,
471 .end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
472 .flags = IORESOURCE_DMA,
473 },
474 /* RX event */
475 {
476 .name = "rx",
477 .start = DAVINCI_DA830_DMA_MCASP2_AREVT,
478 .end = DAVINCI_DA830_DMA_MCASP2_AREVT,
479 .flags = IORESOURCE_DMA,
480 },
481 {
482 .name = "common",
483 .start = IRQ_DA8XX_MCASPINT,
484 .flags = IORESOURCE_IRQ,
485 },
486 };
487
488 static struct platform_device da830_mcasp2_device = {
489 .name = "davinci-mcasp",
490 .id = 2,
491 .num_resources = ARRAY_SIZE(da830_mcasp2_resources),
492 .resource = da830_mcasp2_resources,
493 };
494
495 static struct resource da850_mcasp_resources[] = {
496 {
497 .name = "mpu",
498 .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
499 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
500 .flags = IORESOURCE_MEM,
501 },
502 /* TX event */
503 {
504 .name = "tx",
505 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
506 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
507 .flags = IORESOURCE_DMA,
508 },
509 /* RX event */
510 {
511 .name = "rx",
512 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
513 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
514 .flags = IORESOURCE_DMA,
515 },
516 {
517 .name = "common",
518 .start = IRQ_DA8XX_MCASPINT,
519 .flags = IORESOURCE_IRQ,
520 },
521 };
522
523 static struct platform_device da850_mcasp_device = {
524 .name = "davinci-mcasp",
525 .id = 0,
526 .num_resources = ARRAY_SIZE(da850_mcasp_resources),
527 .resource = da850_mcasp_resources,
528 };
529
da8xx_register_mcasp(int id,struct snd_platform_data * pdata)530 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
531 {
532 struct platform_device *pdev;
533
534 switch (id) {
535 case 0:
536 /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
537 pdev = &da850_mcasp_device;
538 break;
539 case 1:
540 /* Valid for DA830/OMAP-L137 only */
541 if (!cpu_is_davinci_da830())
542 return;
543 pdev = &da830_mcasp1_device;
544 break;
545 case 2:
546 /* Valid for DA830/OMAP-L137 only */
547 if (!cpu_is_davinci_da830())
548 return;
549 pdev = &da830_mcasp2_device;
550 break;
551 default:
552 return;
553 }
554
555 pdev->dev.platform_data = pdata;
556 platform_device_register(pdev);
557 }
558
559 static struct resource da8xx_pruss_resources[] = {
560 {
561 .start = DA8XX_PRUSS_MEM_BASE,
562 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
563 .flags = IORESOURCE_MEM,
564 },
565 {
566 .start = IRQ_DA8XX_EVTOUT0,
567 .end = IRQ_DA8XX_EVTOUT0,
568 .flags = IORESOURCE_IRQ,
569 },
570 {
571 .start = IRQ_DA8XX_EVTOUT1,
572 .end = IRQ_DA8XX_EVTOUT1,
573 .flags = IORESOURCE_IRQ,
574 },
575 {
576 .start = IRQ_DA8XX_EVTOUT2,
577 .end = IRQ_DA8XX_EVTOUT2,
578 .flags = IORESOURCE_IRQ,
579 },
580 {
581 .start = IRQ_DA8XX_EVTOUT3,
582 .end = IRQ_DA8XX_EVTOUT3,
583 .flags = IORESOURCE_IRQ,
584 },
585 {
586 .start = IRQ_DA8XX_EVTOUT4,
587 .end = IRQ_DA8XX_EVTOUT4,
588 .flags = IORESOURCE_IRQ,
589 },
590 {
591 .start = IRQ_DA8XX_EVTOUT5,
592 .end = IRQ_DA8XX_EVTOUT5,
593 .flags = IORESOURCE_IRQ,
594 },
595 {
596 .start = IRQ_DA8XX_EVTOUT6,
597 .end = IRQ_DA8XX_EVTOUT6,
598 .flags = IORESOURCE_IRQ,
599 },
600 {
601 .start = IRQ_DA8XX_EVTOUT7,
602 .end = IRQ_DA8XX_EVTOUT7,
603 .flags = IORESOURCE_IRQ,
604 },
605 };
606
607 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
608 .pintc_base = 0x4000,
609 };
610
611 static struct platform_device da8xx_uio_pruss_dev = {
612 .name = "pruss_uio",
613 .id = -1,
614 .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
615 .resource = da8xx_pruss_resources,
616 .dev = {
617 .coherent_dma_mask = DMA_BIT_MASK(32),
618 .platform_data = &da8xx_uio_pruss_pdata,
619 }
620 };
621
da8xx_register_uio_pruss(void)622 int __init da8xx_register_uio_pruss(void)
623 {
624 da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
625 return platform_device_register(&da8xx_uio_pruss_dev);
626 }
627
628 static struct lcd_ctrl_config lcd_cfg = {
629 .panel_shade = COLOR_ACTIVE,
630 .bpp = 16,
631 };
632
633 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
634 .manu_name = "sharp",
635 .controller_data = &lcd_cfg,
636 .type = "Sharp_LCD035Q3DG01",
637 };
638
639 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
640 .manu_name = "sharp",
641 .controller_data = &lcd_cfg,
642 .type = "Sharp_LK043T1DG01",
643 };
644
645 static struct resource da8xx_lcdc_resources[] = {
646 [0] = { /* registers */
647 .start = DA8XX_LCD_CNTRL_BASE,
648 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
649 .flags = IORESOURCE_MEM,
650 },
651 [1] = { /* interrupt */
652 .start = IRQ_DA8XX_LCDINT,
653 .end = IRQ_DA8XX_LCDINT,
654 .flags = IORESOURCE_IRQ,
655 },
656 };
657
658 static struct platform_device da8xx_lcdc_device = {
659 .name = "da8xx_lcdc",
660 .id = 0,
661 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
662 .resource = da8xx_lcdc_resources,
663 .dev = {
664 .coherent_dma_mask = DMA_BIT_MASK(32),
665 }
666 };
667
da8xx_register_lcdc(struct da8xx_lcdc_platform_data * pdata)668 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
669 {
670 da8xx_lcdc_device.dev.platform_data = pdata;
671 return platform_device_register(&da8xx_lcdc_device);
672 }
673
674 static struct resource da8xx_gpio_resources[] = {
675 { /* registers */
676 .start = DA8XX_GPIO_BASE,
677 .end = DA8XX_GPIO_BASE + SZ_4K - 1,
678 .flags = IORESOURCE_MEM,
679 },
680 { /* interrupt */
681 .start = IRQ_DA8XX_GPIO0,
682 .end = IRQ_DA8XX_GPIO8,
683 .flags = IORESOURCE_IRQ,
684 },
685 };
686
687 static struct platform_device da8xx_gpio_device = {
688 .name = "davinci_gpio",
689 .id = -1,
690 .num_resources = ARRAY_SIZE(da8xx_gpio_resources),
691 .resource = da8xx_gpio_resources,
692 };
693
da8xx_register_gpio(void * pdata)694 int __init da8xx_register_gpio(void *pdata)
695 {
696 da8xx_gpio_device.dev.platform_data = pdata;
697 return platform_device_register(&da8xx_gpio_device);
698 }
699
700 static struct resource da8xx_mmcsd0_resources[] = {
701 { /* registers */
702 .start = DA8XX_MMCSD0_BASE,
703 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
704 .flags = IORESOURCE_MEM,
705 },
706 { /* interrupt */
707 .start = IRQ_DA8XX_MMCSDINT0,
708 .end = IRQ_DA8XX_MMCSDINT0,
709 .flags = IORESOURCE_IRQ,
710 },
711 { /* DMA RX */
712 .start = DA8XX_DMA_MMCSD0_RX,
713 .end = DA8XX_DMA_MMCSD0_RX,
714 .flags = IORESOURCE_DMA,
715 },
716 { /* DMA TX */
717 .start = DA8XX_DMA_MMCSD0_TX,
718 .end = DA8XX_DMA_MMCSD0_TX,
719 .flags = IORESOURCE_DMA,
720 },
721 };
722
723 static struct platform_device da8xx_mmcsd0_device = {
724 .name = "da830-mmc",
725 .id = 0,
726 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
727 .resource = da8xx_mmcsd0_resources,
728 };
729
da8xx_register_mmcsd0(struct davinci_mmc_config * config)730 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
731 {
732 da8xx_mmcsd0_device.dev.platform_data = config;
733 return platform_device_register(&da8xx_mmcsd0_device);
734 }
735
736 #ifdef CONFIG_ARCH_DAVINCI_DA850
737 static struct resource da850_mmcsd1_resources[] = {
738 { /* registers */
739 .start = DA850_MMCSD1_BASE,
740 .end = DA850_MMCSD1_BASE + SZ_4K - 1,
741 .flags = IORESOURCE_MEM,
742 },
743 { /* interrupt */
744 .start = IRQ_DA850_MMCSDINT0_1,
745 .end = IRQ_DA850_MMCSDINT0_1,
746 .flags = IORESOURCE_IRQ,
747 },
748 { /* DMA RX */
749 .start = DA850_DMA_MMCSD1_RX,
750 .end = DA850_DMA_MMCSD1_RX,
751 .flags = IORESOURCE_DMA,
752 },
753 { /* DMA TX */
754 .start = DA850_DMA_MMCSD1_TX,
755 .end = DA850_DMA_MMCSD1_TX,
756 .flags = IORESOURCE_DMA,
757 },
758 };
759
760 static struct platform_device da850_mmcsd1_device = {
761 .name = "da830-mmc",
762 .id = 1,
763 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
764 .resource = da850_mmcsd1_resources,
765 };
766
da850_register_mmcsd1(struct davinci_mmc_config * config)767 int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
768 {
769 da850_mmcsd1_device.dev.platform_data = config;
770 return platform_device_register(&da850_mmcsd1_device);
771 }
772 #endif
773
774 static struct resource da8xx_rproc_resources[] = {
775 { /* DSP boot address */
776 .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
777 .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
778 .flags = IORESOURCE_MEM,
779 },
780 { /* DSP interrupt registers */
781 .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
782 .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
783 .flags = IORESOURCE_MEM,
784 },
785 { /* dsp irq */
786 .start = IRQ_DA8XX_CHIPINT0,
787 .end = IRQ_DA8XX_CHIPINT0,
788 .flags = IORESOURCE_IRQ,
789 },
790 };
791
792 static struct platform_device da8xx_dsp = {
793 .name = "davinci-rproc",
794 .dev = {
795 .coherent_dma_mask = DMA_BIT_MASK(32),
796 },
797 .num_resources = ARRAY_SIZE(da8xx_rproc_resources),
798 .resource = da8xx_rproc_resources,
799 };
800
801 static bool rproc_mem_inited __initdata;
802
803 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
804
805 static phys_addr_t rproc_base __initdata;
806 static unsigned long rproc_size __initdata;
807
early_rproc_mem(char * p)808 static int __init early_rproc_mem(char *p)
809 {
810 char *endp;
811
812 if (p == NULL)
813 return 0;
814
815 rproc_size = memparse(p, &endp);
816 if (*endp == '@')
817 rproc_base = memparse(endp + 1, NULL);
818
819 return 0;
820 }
821 early_param("rproc_mem", early_rproc_mem);
822
da8xx_rproc_reserve_cma(void)823 void __init da8xx_rproc_reserve_cma(void)
824 {
825 int ret;
826
827 if (!rproc_base || !rproc_size) {
828 pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
829 " 'nn' and 'address' must both be non-zero\n",
830 __func__);
831
832 return;
833 }
834
835 pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
836 __func__, rproc_size, (unsigned long)rproc_base);
837
838 ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
839 if (ret)
840 pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
841 else
842 rproc_mem_inited = true;
843 }
844
845 #else
846
da8xx_rproc_reserve_cma(void)847 void __init da8xx_rproc_reserve_cma(void)
848 {
849 }
850
851 #endif
852
da8xx_register_rproc(void)853 int __init da8xx_register_rproc(void)
854 {
855 int ret;
856
857 if (!rproc_mem_inited) {
858 pr_warn("%s: memory not reserved for DSP, not registering DSP device\n",
859 __func__);
860 return -ENOMEM;
861 }
862
863 ret = platform_device_register(&da8xx_dsp);
864 if (ret)
865 pr_err("%s: can't register DSP device: %d\n", __func__, ret);
866
867 return ret;
868 };
869
870 static struct resource da8xx_rtc_resources[] = {
871 {
872 .start = DA8XX_RTC_BASE,
873 .end = DA8XX_RTC_BASE + SZ_4K - 1,
874 .flags = IORESOURCE_MEM,
875 },
876 { /* timer irq */
877 .start = IRQ_DA8XX_RTC,
878 .end = IRQ_DA8XX_RTC,
879 .flags = IORESOURCE_IRQ,
880 },
881 { /* alarm irq */
882 .start = IRQ_DA8XX_RTC,
883 .end = IRQ_DA8XX_RTC,
884 .flags = IORESOURCE_IRQ,
885 },
886 };
887
888 static struct platform_device da8xx_rtc_device = {
889 .name = "da830-rtc",
890 .id = -1,
891 .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
892 .resource = da8xx_rtc_resources,
893 };
894
da8xx_register_rtc(void)895 int da8xx_register_rtc(void)
896 {
897 return platform_device_register(&da8xx_rtc_device);
898 }
899
900 static void __iomem *da8xx_ddr2_ctlr_base;
da8xx_get_mem_ctlr(void)901 void __iomem * __init da8xx_get_mem_ctlr(void)
902 {
903 if (da8xx_ddr2_ctlr_base)
904 return da8xx_ddr2_ctlr_base;
905
906 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
907 if (!da8xx_ddr2_ctlr_base)
908 pr_warn("%s: Unable to map DDR2 controller", __func__);
909
910 return da8xx_ddr2_ctlr_base;
911 }
912
913 static struct resource da8xx_cpuidle_resources[] = {
914 {
915 .start = DA8XX_DDR2_CTL_BASE,
916 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
917 .flags = IORESOURCE_MEM,
918 },
919 };
920
921 /* DA8XX devices support DDR2 power down */
922 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
923 .ddr2_pdown = 1,
924 };
925
926
927 static struct platform_device da8xx_cpuidle_device = {
928 .name = "cpuidle-davinci",
929 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
930 .resource = da8xx_cpuidle_resources,
931 .dev = {
932 .platform_data = &da8xx_cpuidle_pdata,
933 },
934 };
935
da8xx_register_cpuidle(void)936 int __init da8xx_register_cpuidle(void)
937 {
938 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
939
940 return platform_device_register(&da8xx_cpuidle_device);
941 }
942
943 static struct resource da8xx_spi0_resources[] = {
944 [0] = {
945 .start = DA8XX_SPI0_BASE,
946 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
947 .flags = IORESOURCE_MEM,
948 },
949 [1] = {
950 .start = IRQ_DA8XX_SPINT0,
951 .end = IRQ_DA8XX_SPINT0,
952 .flags = IORESOURCE_IRQ,
953 },
954 [2] = {
955 .start = DA8XX_DMA_SPI0_RX,
956 .end = DA8XX_DMA_SPI0_RX,
957 .flags = IORESOURCE_DMA,
958 },
959 [3] = {
960 .start = DA8XX_DMA_SPI0_TX,
961 .end = DA8XX_DMA_SPI0_TX,
962 .flags = IORESOURCE_DMA,
963 },
964 };
965
966 static struct resource da8xx_spi1_resources[] = {
967 [0] = {
968 .start = DA830_SPI1_BASE,
969 .end = DA830_SPI1_BASE + SZ_4K - 1,
970 .flags = IORESOURCE_MEM,
971 },
972 [1] = {
973 .start = IRQ_DA8XX_SPINT1,
974 .end = IRQ_DA8XX_SPINT1,
975 .flags = IORESOURCE_IRQ,
976 },
977 [2] = {
978 .start = DA8XX_DMA_SPI1_RX,
979 .end = DA8XX_DMA_SPI1_RX,
980 .flags = IORESOURCE_DMA,
981 },
982 [3] = {
983 .start = DA8XX_DMA_SPI1_TX,
984 .end = DA8XX_DMA_SPI1_TX,
985 .flags = IORESOURCE_DMA,
986 },
987 };
988
989 static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
990 [0] = {
991 .version = SPI_VERSION_2,
992 .intr_line = 1,
993 .dma_event_q = EVENTQ_0,
994 .prescaler_limit = 2,
995 },
996 [1] = {
997 .version = SPI_VERSION_2,
998 .intr_line = 1,
999 .dma_event_q = EVENTQ_0,
1000 .prescaler_limit = 2,
1001 },
1002 };
1003
1004 static struct platform_device da8xx_spi_device[] = {
1005 [0] = {
1006 .name = "spi_davinci",
1007 .id = 0,
1008 .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
1009 .resource = da8xx_spi0_resources,
1010 .dev = {
1011 .platform_data = &da8xx_spi_pdata[0],
1012 },
1013 },
1014 [1] = {
1015 .name = "spi_davinci",
1016 .id = 1,
1017 .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
1018 .resource = da8xx_spi1_resources,
1019 .dev = {
1020 .platform_data = &da8xx_spi_pdata[1],
1021 },
1022 },
1023 };
1024
da8xx_register_spi_bus(int instance,unsigned num_chipselect)1025 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
1026 {
1027 if (instance < 0 || instance > 1)
1028 return -EINVAL;
1029
1030 da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
1031
1032 if (instance == 1 && cpu_is_davinci_da850()) {
1033 da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
1034 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
1035 }
1036
1037 return platform_device_register(&da8xx_spi_device[instance]);
1038 }
1039
1040 #ifdef CONFIG_ARCH_DAVINCI_DA850
1041 static struct resource da850_sata_resources[] = {
1042 {
1043 .start = DA850_SATA_BASE,
1044 .end = DA850_SATA_BASE + 0x1fff,
1045 .flags = IORESOURCE_MEM,
1046 },
1047 {
1048 .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
1049 .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
1050 .flags = IORESOURCE_MEM,
1051 },
1052 {
1053 .start = IRQ_DA850_SATAINT,
1054 .flags = IORESOURCE_IRQ,
1055 },
1056 };
1057
1058 static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
1059
1060 static struct platform_device da850_sata_device = {
1061 .name = "ahci_da850",
1062 .id = -1,
1063 .dev = {
1064 .dma_mask = &da850_sata_dmamask,
1065 .coherent_dma_mask = DMA_BIT_MASK(32),
1066 },
1067 .num_resources = ARRAY_SIZE(da850_sata_resources),
1068 .resource = da850_sata_resources,
1069 };
1070
da850_register_sata(unsigned long refclkpn)1071 int __init da850_register_sata(unsigned long refclkpn)
1072 {
1073 /* please see comment in drivers/ata/ahci_da850.c */
1074 BUG_ON(refclkpn != 100 * 1000 * 1000);
1075
1076 return platform_device_register(&da850_sata_device);
1077 }
1078 #endif
1079