1 /*
2 * Clock and PLL control for DaVinci devices
3 *
4 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/mutex.h>
20 #include <linux/io.h>
21 #include <linux/delay.h>
22
23 #include <mach/hardware.h>
24
25 #include <mach/clock.h>
26 #include <mach/psc.h>
27 #include <mach/cputype.h>
28 #include "clock.h"
29
30 static LIST_HEAD(clocks);
31 static DEFINE_MUTEX(clocks_mutex);
32 static DEFINE_SPINLOCK(clockfw_lock);
33
__clk_enable(struct clk * clk)34 static void __clk_enable(struct clk *clk)
35 {
36 if (clk->parent)
37 __clk_enable(clk->parent);
38 if (clk->usecount++ == 0) {
39 if (clk->flags & CLK_PSC)
40 davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
41 true, clk->flags);
42 else if (clk->clk_enable)
43 clk->clk_enable(clk);
44 }
45 }
46
__clk_disable(struct clk * clk)47 static void __clk_disable(struct clk *clk)
48 {
49 if (WARN_ON(clk->usecount == 0))
50 return;
51 if (--clk->usecount == 0) {
52 if (!(clk->flags & CLK_PLL) && (clk->flags & CLK_PSC))
53 davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
54 false, clk->flags);
55 else if (clk->clk_disable)
56 clk->clk_disable(clk);
57 }
58 if (clk->parent)
59 __clk_disable(clk->parent);
60 }
61
davinci_clk_reset(struct clk * clk,bool reset)62 int davinci_clk_reset(struct clk *clk, bool reset)
63 {
64 unsigned long flags;
65
66 if (clk == NULL || IS_ERR(clk))
67 return -EINVAL;
68
69 spin_lock_irqsave(&clockfw_lock, flags);
70 if (clk->flags & CLK_PSC)
71 davinci_psc_reset(clk->gpsc, clk->lpsc, reset);
72 spin_unlock_irqrestore(&clockfw_lock, flags);
73
74 return 0;
75 }
76 EXPORT_SYMBOL(davinci_clk_reset);
77
davinci_clk_reset_assert(struct clk * clk)78 int davinci_clk_reset_assert(struct clk *clk)
79 {
80 if (clk == NULL || IS_ERR(clk) || !clk->reset)
81 return -EINVAL;
82
83 return clk->reset(clk, true);
84 }
85 EXPORT_SYMBOL(davinci_clk_reset_assert);
86
davinci_clk_reset_deassert(struct clk * clk)87 int davinci_clk_reset_deassert(struct clk *clk)
88 {
89 if (clk == NULL || IS_ERR(clk) || !clk->reset)
90 return -EINVAL;
91
92 return clk->reset(clk, false);
93 }
94 EXPORT_SYMBOL(davinci_clk_reset_deassert);
95
clk_enable(struct clk * clk)96 int clk_enable(struct clk *clk)
97 {
98 unsigned long flags;
99
100 if (!clk)
101 return 0;
102 else if (IS_ERR(clk))
103 return -EINVAL;
104
105 spin_lock_irqsave(&clockfw_lock, flags);
106 __clk_enable(clk);
107 spin_unlock_irqrestore(&clockfw_lock, flags);
108
109 return 0;
110 }
111 EXPORT_SYMBOL(clk_enable);
112
clk_disable(struct clk * clk)113 void clk_disable(struct clk *clk)
114 {
115 unsigned long flags;
116
117 if (clk == NULL || IS_ERR(clk))
118 return;
119
120 spin_lock_irqsave(&clockfw_lock, flags);
121 __clk_disable(clk);
122 spin_unlock_irqrestore(&clockfw_lock, flags);
123 }
124 EXPORT_SYMBOL(clk_disable);
125
clk_get_rate(struct clk * clk)126 unsigned long clk_get_rate(struct clk *clk)
127 {
128 if (clk == NULL || IS_ERR(clk))
129 return 0;
130
131 return clk->rate;
132 }
133 EXPORT_SYMBOL(clk_get_rate);
134
clk_round_rate(struct clk * clk,unsigned long rate)135 long clk_round_rate(struct clk *clk, unsigned long rate)
136 {
137 if (clk == NULL || IS_ERR(clk))
138 return 0;
139
140 if (clk->round_rate)
141 return clk->round_rate(clk, rate);
142
143 return clk->rate;
144 }
145 EXPORT_SYMBOL(clk_round_rate);
146
147 /* Propagate rate to children */
propagate_rate(struct clk * root)148 static void propagate_rate(struct clk *root)
149 {
150 struct clk *clk;
151
152 list_for_each_entry(clk, &root->children, childnode) {
153 if (clk->recalc)
154 clk->rate = clk->recalc(clk);
155 propagate_rate(clk);
156 }
157 }
158
clk_set_rate(struct clk * clk,unsigned long rate)159 int clk_set_rate(struct clk *clk, unsigned long rate)
160 {
161 unsigned long flags;
162 int ret = -EINVAL;
163
164 if (!clk)
165 return 0;
166 else if (IS_ERR(clk))
167 return -EINVAL;
168
169 if (clk->set_rate)
170 ret = clk->set_rate(clk, rate);
171
172 spin_lock_irqsave(&clockfw_lock, flags);
173 if (ret == 0) {
174 if (clk->recalc)
175 clk->rate = clk->recalc(clk);
176 propagate_rate(clk);
177 }
178 spin_unlock_irqrestore(&clockfw_lock, flags);
179
180 return ret;
181 }
182 EXPORT_SYMBOL(clk_set_rate);
183
clk_set_parent(struct clk * clk,struct clk * parent)184 int clk_set_parent(struct clk *clk, struct clk *parent)
185 {
186 unsigned long flags;
187
188 if (!clk)
189 return 0;
190 else if (IS_ERR(clk))
191 return -EINVAL;
192
193 /* Cannot change parent on enabled clock */
194 if (WARN_ON(clk->usecount))
195 return -EINVAL;
196
197 mutex_lock(&clocks_mutex);
198 clk->parent = parent;
199 list_del_init(&clk->childnode);
200 list_add(&clk->childnode, &clk->parent->children);
201 mutex_unlock(&clocks_mutex);
202
203 spin_lock_irqsave(&clockfw_lock, flags);
204 if (clk->recalc)
205 clk->rate = clk->recalc(clk);
206 propagate_rate(clk);
207 spin_unlock_irqrestore(&clockfw_lock, flags);
208
209 return 0;
210 }
211 EXPORT_SYMBOL(clk_set_parent);
212
clk_register(struct clk * clk)213 int clk_register(struct clk *clk)
214 {
215 if (clk == NULL || IS_ERR(clk))
216 return -EINVAL;
217
218 if (WARN(clk->parent && !clk->parent->rate,
219 "CLK: %s parent %s has no rate!\n",
220 clk->name, clk->parent->name))
221 return -EINVAL;
222
223 INIT_LIST_HEAD(&clk->children);
224
225 mutex_lock(&clocks_mutex);
226 list_add_tail(&clk->node, &clocks);
227 if (clk->parent)
228 list_add_tail(&clk->childnode, &clk->parent->children);
229 mutex_unlock(&clocks_mutex);
230
231 /* If rate is already set, use it */
232 if (clk->rate)
233 return 0;
234
235 /* Else, see if there is a way to calculate it */
236 if (clk->recalc)
237 clk->rate = clk->recalc(clk);
238
239 /* Otherwise, default to parent rate */
240 else if (clk->parent)
241 clk->rate = clk->parent->rate;
242
243 return 0;
244 }
245 EXPORT_SYMBOL(clk_register);
246
clk_unregister(struct clk * clk)247 void clk_unregister(struct clk *clk)
248 {
249 if (clk == NULL || IS_ERR(clk))
250 return;
251
252 mutex_lock(&clocks_mutex);
253 list_del(&clk->node);
254 list_del(&clk->childnode);
255 mutex_unlock(&clocks_mutex);
256 }
257 EXPORT_SYMBOL(clk_unregister);
258
259 #ifdef CONFIG_DAVINCI_RESET_CLOCKS
260 /*
261 * Disable any unused clocks left on by the bootloader
262 */
davinci_clk_disable_unused(void)263 int __init davinci_clk_disable_unused(void)
264 {
265 struct clk *ck;
266
267 spin_lock_irq(&clockfw_lock);
268 list_for_each_entry(ck, &clocks, node) {
269 if (ck->usecount > 0)
270 continue;
271 if (!(ck->flags & CLK_PSC))
272 continue;
273
274 /* ignore if in Disabled or SwRstDisable states */
275 if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc))
276 continue;
277
278 pr_debug("Clocks: disable unused %s\n", ck->name);
279
280 davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc,
281 false, ck->flags);
282 }
283 spin_unlock_irq(&clockfw_lock);
284
285 return 0;
286 }
287 #endif
288
clk_sysclk_recalc(struct clk * clk)289 static unsigned long clk_sysclk_recalc(struct clk *clk)
290 {
291 u32 v, plldiv;
292 struct pll_data *pll;
293 unsigned long rate = clk->rate;
294
295 /* If this is the PLL base clock, no more calculations needed */
296 if (clk->pll_data)
297 return rate;
298
299 if (WARN_ON(!clk->parent))
300 return rate;
301
302 rate = clk->parent->rate;
303
304 /* Otherwise, the parent must be a PLL */
305 if (WARN_ON(!clk->parent->pll_data))
306 return rate;
307
308 pll = clk->parent->pll_data;
309
310 /* If pre-PLL, source clock is before the multiplier and divider(s) */
311 if (clk->flags & PRE_PLL)
312 rate = pll->input_rate;
313
314 if (!clk->div_reg)
315 return rate;
316
317 v = __raw_readl(pll->base + clk->div_reg);
318 if (v & PLLDIV_EN) {
319 plldiv = (v & pll->div_ratio_mask) + 1;
320 if (plldiv)
321 rate /= plldiv;
322 }
323
324 return rate;
325 }
326
davinci_set_sysclk_rate(struct clk * clk,unsigned long rate)327 int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
328 {
329 unsigned v;
330 struct pll_data *pll;
331 unsigned long input;
332 unsigned ratio = 0;
333
334 /* If this is the PLL base clock, wrong function to call */
335 if (clk->pll_data)
336 return -EINVAL;
337
338 /* There must be a parent... */
339 if (WARN_ON(!clk->parent))
340 return -EINVAL;
341
342 /* ... the parent must be a PLL... */
343 if (WARN_ON(!clk->parent->pll_data))
344 return -EINVAL;
345
346 /* ... and this clock must have a divider. */
347 if (WARN_ON(!clk->div_reg))
348 return -EINVAL;
349
350 pll = clk->parent->pll_data;
351
352 input = clk->parent->rate;
353
354 /* If pre-PLL, source clock is before the multiplier and divider(s) */
355 if (clk->flags & PRE_PLL)
356 input = pll->input_rate;
357
358 if (input > rate) {
359 /*
360 * Can afford to provide an output little higher than requested
361 * only if maximum rate supported by hardware on this sysclk
362 * is known.
363 */
364 if (clk->maxrate) {
365 ratio = DIV_ROUND_CLOSEST(input, rate);
366 if (input / ratio > clk->maxrate)
367 ratio = 0;
368 }
369
370 if (ratio == 0)
371 ratio = DIV_ROUND_UP(input, rate);
372
373 ratio--;
374 }
375
376 if (ratio > pll->div_ratio_mask)
377 return -EINVAL;
378
379 do {
380 v = __raw_readl(pll->base + PLLSTAT);
381 } while (v & PLLSTAT_GOSTAT);
382
383 v = __raw_readl(pll->base + clk->div_reg);
384 v &= ~pll->div_ratio_mask;
385 v |= ratio | PLLDIV_EN;
386 __raw_writel(v, pll->base + clk->div_reg);
387
388 v = __raw_readl(pll->base + PLLCMD);
389 v |= PLLCMD_GOSET;
390 __raw_writel(v, pll->base + PLLCMD);
391
392 do {
393 v = __raw_readl(pll->base + PLLSTAT);
394 } while (v & PLLSTAT_GOSTAT);
395
396 return 0;
397 }
398 EXPORT_SYMBOL(davinci_set_sysclk_rate);
399
clk_leafclk_recalc(struct clk * clk)400 static unsigned long clk_leafclk_recalc(struct clk *clk)
401 {
402 if (WARN_ON(!clk->parent))
403 return clk->rate;
404
405 return clk->parent->rate;
406 }
407
davinci_simple_set_rate(struct clk * clk,unsigned long rate)408 int davinci_simple_set_rate(struct clk *clk, unsigned long rate)
409 {
410 clk->rate = rate;
411 return 0;
412 }
413
clk_pllclk_recalc(struct clk * clk)414 static unsigned long clk_pllclk_recalc(struct clk *clk)
415 {
416 u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
417 u8 bypass;
418 struct pll_data *pll = clk->pll_data;
419 unsigned long rate = clk->rate;
420
421 ctrl = __raw_readl(pll->base + PLLCTL);
422 rate = pll->input_rate = clk->parent->rate;
423
424 if (ctrl & PLLCTL_PLLEN) {
425 bypass = 0;
426 mult = __raw_readl(pll->base + PLLM);
427 if (cpu_is_davinci_dm365())
428 mult = 2 * (mult & PLLM_PLLM_MASK);
429 else
430 mult = (mult & PLLM_PLLM_MASK) + 1;
431 } else
432 bypass = 1;
433
434 if (pll->flags & PLL_HAS_PREDIV) {
435 prediv = __raw_readl(pll->base + PREDIV);
436 if (prediv & PLLDIV_EN)
437 prediv = (prediv & pll->div_ratio_mask) + 1;
438 else
439 prediv = 1;
440 }
441
442 /* pre-divider is fixed, but (some?) chips won't report that */
443 if (cpu_is_davinci_dm355() && pll->num == 1)
444 prediv = 8;
445
446 if (pll->flags & PLL_HAS_POSTDIV) {
447 postdiv = __raw_readl(pll->base + POSTDIV);
448 if (postdiv & PLLDIV_EN)
449 postdiv = (postdiv & pll->div_ratio_mask) + 1;
450 else
451 postdiv = 1;
452 }
453
454 if (!bypass) {
455 rate /= prediv;
456 rate *= mult;
457 rate /= postdiv;
458 }
459
460 pr_debug("PLL%d: input = %lu MHz [ ",
461 pll->num, clk->parent->rate / 1000000);
462 if (bypass)
463 pr_debug("bypass ");
464 if (prediv > 1)
465 pr_debug("/ %d ", prediv);
466 if (mult > 1)
467 pr_debug("* %d ", mult);
468 if (postdiv > 1)
469 pr_debug("/ %d ", postdiv);
470 pr_debug("] --> %lu MHz output.\n", rate / 1000000);
471
472 return rate;
473 }
474
475 /**
476 * davinci_set_pllrate - set the output rate of a given PLL.
477 *
478 * Note: Currently tested to work with OMAP-L138 only.
479 *
480 * @pll: pll whose rate needs to be changed.
481 * @prediv: The pre divider value. Passing 0 disables the pre-divider.
482 * @pllm: The multiplier value. Passing 0 leads to multiply-by-one.
483 * @postdiv: The post divider value. Passing 0 disables the post-divider.
484 */
davinci_set_pllrate(struct pll_data * pll,unsigned int prediv,unsigned int mult,unsigned int postdiv)485 int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
486 unsigned int mult, unsigned int postdiv)
487 {
488 u32 ctrl;
489 unsigned int locktime;
490 unsigned long flags;
491
492 if (pll->base == NULL)
493 return -EINVAL;
494
495 /*
496 * PLL lock time required per OMAP-L138 datasheet is
497 * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm)
498 * as 4 and OSCIN cycle as 25 MHz.
499 */
500 if (prediv) {
501 locktime = ((2000 * prediv) / 100);
502 prediv = (prediv - 1) | PLLDIV_EN;
503 } else {
504 locktime = PLL_LOCK_TIME;
505 }
506 if (postdiv)
507 postdiv = (postdiv - 1) | PLLDIV_EN;
508 if (mult)
509 mult = mult - 1;
510
511 /* Protect against simultaneous calls to PLL setting seqeunce */
512 spin_lock_irqsave(&clockfw_lock, flags);
513
514 ctrl = __raw_readl(pll->base + PLLCTL);
515
516 /* Switch the PLL to bypass mode */
517 ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
518 __raw_writel(ctrl, pll->base + PLLCTL);
519
520 udelay(PLL_BYPASS_TIME);
521
522 /* Reset and enable PLL */
523 ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
524 __raw_writel(ctrl, pll->base + PLLCTL);
525
526 if (pll->flags & PLL_HAS_PREDIV)
527 __raw_writel(prediv, pll->base + PREDIV);
528
529 __raw_writel(mult, pll->base + PLLM);
530
531 if (pll->flags & PLL_HAS_POSTDIV)
532 __raw_writel(postdiv, pll->base + POSTDIV);
533
534 udelay(PLL_RESET_TIME);
535
536 /* Bring PLL out of reset */
537 ctrl |= PLLCTL_PLLRST;
538 __raw_writel(ctrl, pll->base + PLLCTL);
539
540 udelay(locktime);
541
542 /* Remove PLL from bypass mode */
543 ctrl |= PLLCTL_PLLEN;
544 __raw_writel(ctrl, pll->base + PLLCTL);
545
546 spin_unlock_irqrestore(&clockfw_lock, flags);
547
548 return 0;
549 }
550 EXPORT_SYMBOL(davinci_set_pllrate);
551
552 /**
553 * davinci_set_refclk_rate() - Set the reference clock rate
554 * @rate: The new rate.
555 *
556 * Sets the reference clock rate to a given value. This will most likely
557 * result in the entire clock tree getting updated.
558 *
559 * This is used to support boards which use a reference clock different
560 * than that used by default in <soc>.c file. The reference clock rate
561 * should be updated early in the boot process; ideally soon after the
562 * clock tree has been initialized once with the default reference clock
563 * rate (davinci_common_init()).
564 *
565 * Returns 0 on success, error otherwise.
566 */
davinci_set_refclk_rate(unsigned long rate)567 int davinci_set_refclk_rate(unsigned long rate)
568 {
569 struct clk *refclk;
570
571 refclk = clk_get(NULL, "ref");
572 if (IS_ERR(refclk)) {
573 pr_err("%s: failed to get reference clock\n", __func__);
574 return PTR_ERR(refclk);
575 }
576
577 clk_set_rate(refclk, rate);
578
579 clk_put(refclk);
580
581 return 0;
582 }
583
davinci_clk_init(struct clk_lookup * clocks)584 int __init davinci_clk_init(struct clk_lookup *clocks)
585 {
586 struct clk_lookup *c;
587 struct clk *clk;
588 size_t num_clocks = 0;
589
590 for (c = clocks; c->clk; c++) {
591 clk = c->clk;
592
593 if (!clk->recalc) {
594
595 /* Check if clock is a PLL */
596 if (clk->pll_data)
597 clk->recalc = clk_pllclk_recalc;
598
599 /* Else, if it is a PLL-derived clock */
600 else if (clk->flags & CLK_PLL)
601 clk->recalc = clk_sysclk_recalc;
602
603 /* Otherwise, it is a leaf clock (PSC clock) */
604 else if (clk->parent)
605 clk->recalc = clk_leafclk_recalc;
606 }
607
608 if (clk->pll_data) {
609 struct pll_data *pll = clk->pll_data;
610
611 if (!pll->div_ratio_mask)
612 pll->div_ratio_mask = PLLDIV_RATIO_MASK;
613
614 if (pll->phys_base && !pll->base) {
615 pll->base = ioremap(pll->phys_base, SZ_4K);
616 WARN_ON(!pll->base);
617 }
618 }
619
620 if (clk->recalc)
621 clk->rate = clk->recalc(clk);
622
623 if (clk->lpsc)
624 clk->flags |= CLK_PSC;
625
626 if (clk->flags & PSC_LRST)
627 clk->reset = davinci_clk_reset;
628
629 clk_register(clk);
630 num_clocks++;
631
632 /* Turn on clocks that Linux doesn't otherwise manage */
633 if (clk->flags & ALWAYS_ENABLED)
634 clk_enable(clk);
635 }
636
637 clkdev_add_table(clocks, num_clocks);
638
639 return 0;
640 }
641
642 #ifdef CONFIG_DEBUG_FS
643
644 #include <linux/debugfs.h>
645 #include <linux/seq_file.h>
646
647 #define CLKNAME_MAX 10 /* longest clock name */
648 #define NEST_DELTA 2
649 #define NEST_MAX 4
650
651 static void
dump_clock(struct seq_file * s,unsigned nest,struct clk * parent)652 dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
653 {
654 char *state;
655 char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
656 struct clk *clk;
657 unsigned i;
658
659 if (parent->flags & CLK_PLL)
660 state = "pll";
661 else if (parent->flags & CLK_PSC)
662 state = "psc";
663 else
664 state = "";
665
666 /* <nest spaces> name <pad to end> */
667 memset(buf, ' ', sizeof(buf) - 1);
668 buf[sizeof(buf) - 1] = 0;
669 i = strlen(parent->name);
670 memcpy(buf + nest, parent->name,
671 min(i, (unsigned)(sizeof(buf) - 1 - nest)));
672
673 seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
674 buf, parent->usecount, state, clk_get_rate(parent));
675 /* REVISIT show device associations too */
676
677 /* cost is now small, but not linear... */
678 list_for_each_entry(clk, &parent->children, childnode) {
679 dump_clock(s, nest + NEST_DELTA, clk);
680 }
681 }
682
davinci_ck_show(struct seq_file * m,void * v)683 static int davinci_ck_show(struct seq_file *m, void *v)
684 {
685 struct clk *clk;
686
687 /*
688 * Show clock tree; We trust nonzero usecounts equate to PSC enables...
689 */
690 mutex_lock(&clocks_mutex);
691 list_for_each_entry(clk, &clocks, node)
692 if (!clk->parent)
693 dump_clock(m, 0, clk);
694 mutex_unlock(&clocks_mutex);
695
696 return 0;
697 }
698
davinci_ck_open(struct inode * inode,struct file * file)699 static int davinci_ck_open(struct inode *inode, struct file *file)
700 {
701 return single_open(file, davinci_ck_show, NULL);
702 }
703
704 static const struct file_operations davinci_ck_operations = {
705 .open = davinci_ck_open,
706 .read = seq_read,
707 .llseek = seq_lseek,
708 .release = single_release,
709 };
710
davinci_clk_debugfs_init(void)711 static int __init davinci_clk_debugfs_init(void)
712 {
713 debugfs_create_file("davinci_clocks", S_IFREG | S_IRUGO, NULL, NULL,
714 &davinci_ck_operations);
715 return 0;
716
717 }
718 device_initcall(davinci_clk_debugfs_init);
719 #endif /* CONFIG_DEBUG_FS */
720