1 /*
2 * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
3 * <benh@kernel.crashing.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
13 * the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #ifndef _ASM_POWERPC_DCR_NATIVE_H
21 #define _ASM_POWERPC_DCR_NATIVE_H
22 #ifdef __KERNEL__
23 #ifndef __ASSEMBLY__
24
25 #include <linux/spinlock.h>
26 #include <asm/cputable.h>
27
28 typedef struct {
29 unsigned int base;
30 } dcr_host_native_t;
31
dcr_map_ok_native(dcr_host_native_t host)32 static inline bool dcr_map_ok_native(dcr_host_native_t host)
33 {
34 return true;
35 }
36
37 #define dcr_map_native(dev, dcr_n, dcr_c) \
38 ((dcr_host_native_t){ .base = (dcr_n) })
39 #define dcr_unmap_native(host, dcr_c) do {} while (0)
40 #define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base)
41 #define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
42
43 /* Table based DCR accessors */
44 extern void __mtdcr(unsigned int reg, unsigned int val);
45 extern unsigned int __mfdcr(unsigned int reg);
46
47 /* mfdcrx/mtdcrx instruction based accessors. We hand code
48 * the opcodes in order not to depend on newer binutils
49 */
mfdcrx(unsigned int reg)50 static inline unsigned int mfdcrx(unsigned int reg)
51 {
52 unsigned int ret;
53 asm volatile(".long 0x7c000206 | (%0 << 21) | (%1 << 16)"
54 : "=r" (ret) : "r" (reg));
55 return ret;
56 }
57
mtdcrx(unsigned int reg,unsigned int val)58 static inline void mtdcrx(unsigned int reg, unsigned int val)
59 {
60 asm volatile(".long 0x7c000306 | (%0 << 21) | (%1 << 16)"
61 : : "r" (val), "r" (reg));
62 }
63
64 #define mfdcr(rn) \
65 ({unsigned int rval; \
66 if (__builtin_constant_p(rn) && rn < 1024) \
67 asm volatile("mfdcr %0, %1" : "=r" (rval) \
68 : "n" (rn)); \
69 else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR))) \
70 rval = mfdcrx(rn); \
71 else \
72 rval = __mfdcr(rn); \
73 rval;})
74
75 #define mtdcr(rn, v) \
76 do { \
77 if (__builtin_constant_p(rn) && rn < 1024) \
78 asm volatile("mtdcr %0, %1" \
79 : : "n" (rn), "r" (v)); \
80 else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR))) \
81 mtdcrx(rn, v); \
82 else \
83 __mtdcr(rn, v); \
84 } while (0)
85
86 /* R/W of indirect DCRs make use of standard naming conventions for DCRs */
87 extern spinlock_t dcr_ind_lock;
88
__mfdcri(int base_addr,int base_data,int reg)89 static inline unsigned __mfdcri(int base_addr, int base_data, int reg)
90 {
91 unsigned long flags;
92 unsigned int val;
93
94 spin_lock_irqsave(&dcr_ind_lock, flags);
95 if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
96 mtdcrx(base_addr, reg);
97 val = mfdcrx(base_data);
98 } else {
99 __mtdcr(base_addr, reg);
100 val = __mfdcr(base_data);
101 }
102 spin_unlock_irqrestore(&dcr_ind_lock, flags);
103 return val;
104 }
105
__mtdcri(int base_addr,int base_data,int reg,unsigned val)106 static inline void __mtdcri(int base_addr, int base_data, int reg,
107 unsigned val)
108 {
109 unsigned long flags;
110
111 spin_lock_irqsave(&dcr_ind_lock, flags);
112 if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
113 mtdcrx(base_addr, reg);
114 mtdcrx(base_data, val);
115 } else {
116 __mtdcr(base_addr, reg);
117 __mtdcr(base_data, val);
118 }
119 spin_unlock_irqrestore(&dcr_ind_lock, flags);
120 }
121
__dcri_clrset(int base_addr,int base_data,int reg,unsigned clr,unsigned set)122 static inline void __dcri_clrset(int base_addr, int base_data, int reg,
123 unsigned clr, unsigned set)
124 {
125 unsigned long flags;
126 unsigned int val;
127
128 spin_lock_irqsave(&dcr_ind_lock, flags);
129 if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
130 mtdcrx(base_addr, reg);
131 val = (mfdcrx(base_data) & ~clr) | set;
132 mtdcrx(base_data, val);
133 } else {
134 __mtdcr(base_addr, reg);
135 val = (__mfdcr(base_data) & ~clr) | set;
136 __mtdcr(base_data, val);
137 }
138 spin_unlock_irqrestore(&dcr_ind_lock, flags);
139 }
140
141 #define mfdcri(base, reg) __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \
142 DCRN_ ## base ## _CONFIG_DATA, \
143 reg)
144
145 #define mtdcri(base, reg, data) __mtdcri(DCRN_ ## base ## _CONFIG_ADDR, \
146 DCRN_ ## base ## _CONFIG_DATA, \
147 reg, data)
148
149 #define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \
150 DCRN_ ## base ## _CONFIG_DATA, \
151 reg, clr, set)
152
153 #endif /* __ASSEMBLY__ */
154 #endif /* __KERNEL__ */
155 #endif /* _ASM_POWERPC_DCR_NATIVE_H */
156