1 /*
2 * Copyright © 2009 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/delay.h>
26 #include <linux/init.h>
27 #include <linux/errno.h>
28 #include <linux/sched.h>
29 #include <linux/i2c.h>
30 #include <drm/drm_dp_helper.h>
31 #include <drm/drmP.h>
32
33 /**
34 * DOC: dp helpers
35 *
36 * These functions contain some common logic and helpers at various abstraction
37 * levels to deal with Display Port sink devices and related things like DP aux
38 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
39 * blocks, ...
40 */
41
42 /* Helpers for DP link training */
dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE],int r)43 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
44 {
45 return link_status[r - DP_LANE0_1_STATUS];
46 }
47
dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],int lane)48 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
49 int lane)
50 {
51 int i = DP_LANE0_1_STATUS + (lane >> 1);
52 int s = (lane & 1) * 4;
53 u8 l = dp_link_status(link_status, i);
54 return (l >> s) & 0xf;
55 }
56
drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],int lane_count)57 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
58 int lane_count)
59 {
60 u8 lane_align;
61 u8 lane_status;
62 int lane;
63
64 lane_align = dp_link_status(link_status,
65 DP_LANE_ALIGN_STATUS_UPDATED);
66 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
67 return false;
68 for (lane = 0; lane < lane_count; lane++) {
69 lane_status = dp_get_lane_status(link_status, lane);
70 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
71 return false;
72 }
73 return true;
74 }
75 EXPORT_SYMBOL(drm_dp_channel_eq_ok);
76
drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],int lane_count)77 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
78 int lane_count)
79 {
80 int lane;
81 u8 lane_status;
82
83 for (lane = 0; lane < lane_count; lane++) {
84 lane_status = dp_get_lane_status(link_status, lane);
85 if ((lane_status & DP_LANE_CR_DONE) == 0)
86 return false;
87 }
88 return true;
89 }
90 EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
91
drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],int lane)92 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
93 int lane)
94 {
95 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
96 int s = ((lane & 1) ?
97 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
98 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
99 u8 l = dp_link_status(link_status, i);
100
101 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
102 }
103 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
104
drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],int lane)105 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
106 int lane)
107 {
108 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
109 int s = ((lane & 1) ?
110 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
111 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
112 u8 l = dp_link_status(link_status, i);
113
114 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
115 }
116 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
117
drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])118 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
119 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
120 udelay(100);
121 else
122 mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
123 }
124 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
125
drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])126 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
127 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
128 udelay(400);
129 else
130 mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
131 }
132 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
133
drm_dp_link_rate_to_bw_code(int link_rate)134 u8 drm_dp_link_rate_to_bw_code(int link_rate)
135 {
136 switch (link_rate) {
137 case 162000:
138 default:
139 return DP_LINK_BW_1_62;
140 case 270000:
141 return DP_LINK_BW_2_7;
142 case 540000:
143 return DP_LINK_BW_5_4;
144 }
145 }
146 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
147
drm_dp_bw_code_to_link_rate(u8 link_bw)148 int drm_dp_bw_code_to_link_rate(u8 link_bw)
149 {
150 switch (link_bw) {
151 case DP_LINK_BW_1_62:
152 default:
153 return 162000;
154 case DP_LINK_BW_2_7:
155 return 270000;
156 case DP_LINK_BW_5_4:
157 return 540000;
158 }
159 }
160 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
161
162 #define AUX_RETRY_INTERVAL 500 /* us */
163
164 /**
165 * DOC: dp helpers
166 *
167 * The DisplayPort AUX channel is an abstraction to allow generic, driver-
168 * independent access to AUX functionality. Drivers can take advantage of
169 * this by filling in the fields of the drm_dp_aux structure.
170 *
171 * Transactions are described using a hardware-independent drm_dp_aux_msg
172 * structure, which is passed into a driver's .transfer() implementation.
173 * Both native and I2C-over-AUX transactions are supported.
174 */
175
drm_dp_dpcd_access(struct drm_dp_aux * aux,u8 request,unsigned int offset,void * buffer,size_t size)176 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
177 unsigned int offset, void *buffer, size_t size)
178 {
179 struct drm_dp_aux_msg msg;
180 unsigned int retry;
181 int err = 0;
182
183 memset(&msg, 0, sizeof(msg));
184 msg.address = offset;
185 msg.request = request;
186 msg.buffer = buffer;
187 msg.size = size;
188
189 mutex_lock(&aux->hw_mutex);
190
191 /*
192 * The specification doesn't give any recommendation on how often to
193 * retry native transactions. We used to retry 7 times like for
194 * aux i2c transactions but real world devices this wasn't
195 * sufficient, bump to 32 which makes Dell 4k monitors happier.
196 */
197 for (retry = 0; retry < 32; retry++) {
198
199 err = aux->transfer(aux, &msg);
200 if (err < 0) {
201 if (err == -EBUSY)
202 continue;
203
204 goto unlock;
205 }
206
207
208 switch (msg.reply & DP_AUX_NATIVE_REPLY_MASK) {
209 case DP_AUX_NATIVE_REPLY_ACK:
210 if (err < size)
211 err = -EPROTO;
212 goto unlock;
213
214 case DP_AUX_NATIVE_REPLY_NACK:
215 err = -EIO;
216 goto unlock;
217
218 case DP_AUX_NATIVE_REPLY_DEFER:
219 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
220 break;
221 }
222 }
223
224 DRM_DEBUG_KMS("too many retries, giving up\n");
225 err = -EIO;
226
227 unlock:
228 mutex_unlock(&aux->hw_mutex);
229 return err;
230 }
231
232 /**
233 * drm_dp_dpcd_read() - read a series of bytes from the DPCD
234 * @aux: DisplayPort AUX channel
235 * @offset: address of the (first) register to read
236 * @buffer: buffer to store the register values
237 * @size: number of bytes in @buffer
238 *
239 * Returns the number of bytes transferred on success, or a negative error
240 * code on failure. -EIO is returned if the request was NAKed by the sink or
241 * if the retry count was exceeded. If not all bytes were transferred, this
242 * function returns -EPROTO. Errors from the underlying AUX channel transfer
243 * function, with the exception of -EBUSY (which causes the transaction to
244 * be retried), are propagated to the caller.
245 */
drm_dp_dpcd_read(struct drm_dp_aux * aux,unsigned int offset,void * buffer,size_t size)246 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
247 void *buffer, size_t size)
248 {
249 return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer,
250 size);
251 }
252 EXPORT_SYMBOL(drm_dp_dpcd_read);
253
254 /**
255 * drm_dp_dpcd_write() - write a series of bytes to the DPCD
256 * @aux: DisplayPort AUX channel
257 * @offset: address of the (first) register to write
258 * @buffer: buffer containing the values to write
259 * @size: number of bytes in @buffer
260 *
261 * Returns the number of bytes transferred on success, or a negative error
262 * code on failure. -EIO is returned if the request was NAKed by the sink or
263 * if the retry count was exceeded. If not all bytes were transferred, this
264 * function returns -EPROTO. Errors from the underlying AUX channel transfer
265 * function, with the exception of -EBUSY (which causes the transaction to
266 * be retried), are propagated to the caller.
267 */
drm_dp_dpcd_write(struct drm_dp_aux * aux,unsigned int offset,void * buffer,size_t size)268 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
269 void *buffer, size_t size)
270 {
271 return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer,
272 size);
273 }
274 EXPORT_SYMBOL(drm_dp_dpcd_write);
275
276 /**
277 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
278 * @aux: DisplayPort AUX channel
279 * @status: buffer to store the link status in (must be at least 6 bytes)
280 *
281 * Returns the number of bytes transferred on success or a negative error
282 * code on failure.
283 */
drm_dp_dpcd_read_link_status(struct drm_dp_aux * aux,u8 status[DP_LINK_STATUS_SIZE])284 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
285 u8 status[DP_LINK_STATUS_SIZE])
286 {
287 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
288 DP_LINK_STATUS_SIZE);
289 }
290 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
291
292 /**
293 * drm_dp_link_probe() - probe a DisplayPort link for capabilities
294 * @aux: DisplayPort AUX channel
295 * @link: pointer to structure in which to return link capabilities
296 *
297 * The structure filled in by this function can usually be passed directly
298 * into drm_dp_link_power_up() and drm_dp_link_configure() to power up and
299 * configure the link based on the link's capabilities.
300 *
301 * Returns 0 on success or a negative error code on failure.
302 */
drm_dp_link_probe(struct drm_dp_aux * aux,struct drm_dp_link * link)303 int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
304 {
305 u8 values[3];
306 int err;
307
308 memset(link, 0, sizeof(*link));
309
310 err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values));
311 if (err < 0)
312 return err;
313
314 link->revision = values[0];
315 link->rate = drm_dp_bw_code_to_link_rate(values[1]);
316 link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
317
318 if (values[2] & DP_ENHANCED_FRAME_CAP)
319 link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING;
320
321 return 0;
322 }
323 EXPORT_SYMBOL(drm_dp_link_probe);
324
325 /**
326 * drm_dp_link_power_up() - power up a DisplayPort link
327 * @aux: DisplayPort AUX channel
328 * @link: pointer to a structure containing the link configuration
329 *
330 * Returns 0 on success or a negative error code on failure.
331 */
drm_dp_link_power_up(struct drm_dp_aux * aux,struct drm_dp_link * link)332 int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link)
333 {
334 u8 value;
335 int err;
336
337 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
338 if (link->revision < 0x11)
339 return 0;
340
341 err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
342 if (err < 0)
343 return err;
344
345 value &= ~DP_SET_POWER_MASK;
346 value |= DP_SET_POWER_D0;
347
348 err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
349 if (err < 0)
350 return err;
351
352 /*
353 * According to the DP 1.1 specification, a "Sink Device must exit the
354 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
355 * Control Field" (register 0x600).
356 */
357 usleep_range(1000, 2000);
358
359 return 0;
360 }
361 EXPORT_SYMBOL(drm_dp_link_power_up);
362
363 /**
364 * drm_dp_link_power_down() - power down a DisplayPort link
365 * @aux: DisplayPort AUX channel
366 * @link: pointer to a structure containing the link configuration
367 *
368 * Returns 0 on success or a negative error code on failure.
369 */
drm_dp_link_power_down(struct drm_dp_aux * aux,struct drm_dp_link * link)370 int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link)
371 {
372 u8 value;
373 int err;
374
375 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
376 if (link->revision < 0x11)
377 return 0;
378
379 err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
380 if (err < 0)
381 return err;
382
383 value &= ~DP_SET_POWER_MASK;
384 value |= DP_SET_POWER_D3;
385
386 err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
387 if (err < 0)
388 return err;
389
390 return 0;
391 }
392 EXPORT_SYMBOL(drm_dp_link_power_down);
393
394 /**
395 * drm_dp_link_configure() - configure a DisplayPort link
396 * @aux: DisplayPort AUX channel
397 * @link: pointer to a structure containing the link configuration
398 *
399 * Returns 0 on success or a negative error code on failure.
400 */
drm_dp_link_configure(struct drm_dp_aux * aux,struct drm_dp_link * link)401 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
402 {
403 u8 values[2];
404 int err;
405
406 values[0] = drm_dp_link_rate_to_bw_code(link->rate);
407 values[1] = link->num_lanes;
408
409 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
410 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
411
412 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
413 if (err < 0)
414 return err;
415
416 return 0;
417 }
418 EXPORT_SYMBOL(drm_dp_link_configure);
419
420 /*
421 * I2C-over-AUX implementation
422 */
423
drm_dp_i2c_functionality(struct i2c_adapter * adapter)424 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
425 {
426 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
427 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
428 I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
429 I2C_FUNC_10BIT_ADDR;
430 }
431
drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg * msg)432 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
433 {
434 /*
435 * In case of i2c defer or short i2c ack reply to a write,
436 * we need to switch to WRITE_STATUS_UPDATE to drain the
437 * rest of the message
438 */
439 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
440 msg->request &= DP_AUX_I2C_MOT;
441 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
442 }
443 }
444
445 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
446 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
447 #define AUX_STOP_LEN 4
448 #define AUX_CMD_LEN 4
449 #define AUX_ADDRESS_LEN 20
450 #define AUX_REPLY_PAD_LEN 4
451 #define AUX_LENGTH_LEN 8
452
453 /*
454 * Calculate the duration of the AUX request/reply in usec. Gives the
455 * "best" case estimate, ie. successful while as short as possible.
456 */
drm_dp_aux_req_duration(const struct drm_dp_aux_msg * msg)457 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
458 {
459 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
460 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
461
462 if ((msg->request & DP_AUX_I2C_READ) == 0)
463 len += msg->size * 8;
464
465 return len;
466 }
467
drm_dp_aux_reply_duration(const struct drm_dp_aux_msg * msg)468 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
469 {
470 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
471 AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
472
473 /*
474 * For read we expect what was asked. For writes there will
475 * be 0 or 1 data bytes. Assume 0 for the "best" case.
476 */
477 if (msg->request & DP_AUX_I2C_READ)
478 len += msg->size * 8;
479
480 return len;
481 }
482
483 #define I2C_START_LEN 1
484 #define I2C_STOP_LEN 1
485 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
486 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
487
488 /*
489 * Calculate the length of the i2c transfer in usec, assuming
490 * the i2c bus speed is as specified. Gives the the "worst"
491 * case estimate, ie. successful while as long as possible.
492 * Doesn't account the the "MOT" bit, and instead assumes each
493 * message includes a START, ADDRESS and STOP. Neither does it
494 * account for additional random variables such as clock stretching.
495 */
drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg * msg,int i2c_speed_khz)496 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
497 int i2c_speed_khz)
498 {
499 /* AUX bitrate is 1MHz, i2c bitrate as specified */
500 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
501 msg->size * I2C_DATA_LEN +
502 I2C_STOP_LEN) * 1000, i2c_speed_khz);
503 }
504
505 /*
506 * Deterine how many retries should be attempted to successfully transfer
507 * the specified message, based on the estimated durations of the
508 * i2c and AUX transfers.
509 */
drm_dp_i2c_retry_count(const struct drm_dp_aux_msg * msg,int i2c_speed_khz)510 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
511 int i2c_speed_khz)
512 {
513 int aux_time_us = drm_dp_aux_req_duration(msg) +
514 drm_dp_aux_reply_duration(msg);
515 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
516
517 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
518 }
519
520 /*
521 * FIXME currently assumes 10 kHz as some real world devices seem
522 * to require it. We should query/set the speed via DPCD if supported.
523 */
524 static int dp_aux_i2c_speed_khz __read_mostly = 10;
525 module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
526 MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
527 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
528
529 /*
530 * Transfer a single I2C-over-AUX message and handle various error conditions,
531 * retrying the transaction as appropriate. It is assumed that the
532 * aux->transfer function does not modify anything in the msg other than the
533 * reply field.
534 *
535 * Returns bytes transferred on success, or a negative error code on failure.
536 */
drm_dp_i2c_do_msg(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)537 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
538 {
539 unsigned int retry, defer_i2c;
540 int ret;
541 /*
542 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
543 * is required to retry at least seven times upon receiving AUX_DEFER
544 * before giving up the AUX transaction.
545 *
546 * We also try to account for the i2c bus speed.
547 */
548 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
549
550 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
551 ret = aux->transfer(aux, msg);
552 if (ret < 0) {
553 if (ret == -EBUSY)
554 continue;
555
556 DRM_DEBUG_KMS("transaction failed: %d\n", ret);
557 return ret;
558 }
559
560
561 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
562 case DP_AUX_NATIVE_REPLY_ACK:
563 /*
564 * For I2C-over-AUX transactions this isn't enough, we
565 * need to check for the I2C ACK reply.
566 */
567 break;
568
569 case DP_AUX_NATIVE_REPLY_NACK:
570 DRM_DEBUG_KMS("native nack (result=%d, size=%zu)\n", ret, msg->size);
571 return -EREMOTEIO;
572
573 case DP_AUX_NATIVE_REPLY_DEFER:
574 DRM_DEBUG_KMS("native defer\n");
575 /*
576 * We could check for I2C bit rate capabilities and if
577 * available adjust this interval. We could also be
578 * more careful with DP-to-legacy adapters where a
579 * long legacy cable may force very low I2C bit rates.
580 *
581 * For now just defer for long enough to hopefully be
582 * safe for all use-cases.
583 */
584 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
585 continue;
586
587 default:
588 DRM_ERROR("invalid native reply %#04x\n", msg->reply);
589 return -EREMOTEIO;
590 }
591
592 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
593 case DP_AUX_I2C_REPLY_ACK:
594 /*
595 * Both native ACK and I2C ACK replies received. We
596 * can assume the transfer was successful.
597 */
598 if (ret != msg->size)
599 drm_dp_i2c_msg_write_status_update(msg);
600 return ret;
601
602 case DP_AUX_I2C_REPLY_NACK:
603 DRM_DEBUG_KMS("I2C nack (result=%d, size=%zu\n", ret, msg->size);
604 aux->i2c_nack_count++;
605 return -EREMOTEIO;
606
607 case DP_AUX_I2C_REPLY_DEFER:
608 DRM_DEBUG_KMS("I2C defer\n");
609 /* DP Compliance Test 4.2.2.5 Requirement:
610 * Must have at least 7 retries for I2C defers on the
611 * transaction to pass this test
612 */
613 aux->i2c_defer_count++;
614 if (defer_i2c < 7)
615 defer_i2c++;
616 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
617 drm_dp_i2c_msg_write_status_update(msg);
618
619 continue;
620
621 default:
622 DRM_ERROR("invalid I2C reply %#04x\n", msg->reply);
623 return -EREMOTEIO;
624 }
625 }
626
627 DRM_DEBUG_KMS("too many retries, giving up\n");
628 return -EREMOTEIO;
629 }
630
drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg * msg,const struct i2c_msg * i2c_msg)631 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
632 const struct i2c_msg *i2c_msg)
633 {
634 msg->request = (i2c_msg->flags & I2C_M_RD) ?
635 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
636 msg->request |= DP_AUX_I2C_MOT;
637 }
638
639 /*
640 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
641 *
642 * Returns an error code on failure, or a recommended transfer size on success.
643 */
drm_dp_i2c_drain_msg(struct drm_dp_aux * aux,struct drm_dp_aux_msg * orig_msg)644 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
645 {
646 int err, ret = orig_msg->size;
647 struct drm_dp_aux_msg msg = *orig_msg;
648
649 while (msg.size > 0) {
650 err = drm_dp_i2c_do_msg(aux, &msg);
651 if (err <= 0)
652 return err == 0 ? -EPROTO : err;
653
654 if (err < msg.size && err < ret) {
655 DRM_DEBUG_KMS("Partial I2C reply: requested %zu bytes got %d bytes\n",
656 msg.size, err);
657 ret = err;
658 }
659
660 msg.size -= err;
661 msg.buffer += err;
662 }
663
664 return ret;
665 }
666
667 /*
668 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
669 * packets to be as large as possible. If not, the I2C transactions never
670 * succeed. Hence the default is maximum.
671 */
672 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
673 module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
674 MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
675 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
676
drm_dp_i2c_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)677 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
678 int num)
679 {
680 struct drm_dp_aux *aux = adapter->algo_data;
681 unsigned int i, j;
682 unsigned transfer_size;
683 struct drm_dp_aux_msg msg;
684 int err = 0;
685
686 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
687
688 memset(&msg, 0, sizeof(msg));
689
690 mutex_lock(&aux->hw_mutex);
691
692 for (i = 0; i < num; i++) {
693 msg.address = msgs[i].addr;
694 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
695 /* Send a bare address packet to start the transaction.
696 * Zero sized messages specify an address only (bare
697 * address) transaction.
698 */
699 msg.buffer = NULL;
700 msg.size = 0;
701 err = drm_dp_i2c_do_msg(aux, &msg);
702
703 /*
704 * Reset msg.request in case in case it got
705 * changed into a WRITE_STATUS_UPDATE.
706 */
707 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
708
709 if (err < 0)
710 break;
711 /* We want each transaction to be as large as possible, but
712 * we'll go to smaller sizes if the hardware gives us a
713 * short reply.
714 */
715 transfer_size = dp_aux_i2c_transfer_size;
716 for (j = 0; j < msgs[i].len; j += msg.size) {
717 msg.buffer = msgs[i].buf + j;
718 msg.size = min(transfer_size, msgs[i].len - j);
719
720 err = drm_dp_i2c_drain_msg(aux, &msg);
721
722 /*
723 * Reset msg.request in case in case it got
724 * changed into a WRITE_STATUS_UPDATE.
725 */
726 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
727
728 if (err < 0)
729 break;
730 transfer_size = err;
731 }
732 if (err < 0)
733 break;
734 }
735 if (err >= 0)
736 err = num;
737 /* Send a bare address packet to close out the transaction.
738 * Zero sized messages specify an address only (bare
739 * address) transaction.
740 */
741 msg.request &= ~DP_AUX_I2C_MOT;
742 msg.buffer = NULL;
743 msg.size = 0;
744 (void)drm_dp_i2c_do_msg(aux, &msg);
745
746 mutex_unlock(&aux->hw_mutex);
747
748 return err;
749 }
750
751 static const struct i2c_algorithm drm_dp_i2c_algo = {
752 .functionality = drm_dp_i2c_functionality,
753 .master_xfer = drm_dp_i2c_xfer,
754 };
755
756 /**
757 * drm_dp_aux_register() - initialise and register aux channel
758 * @aux: DisplayPort AUX channel
759 *
760 * Returns 0 on success or a negative error code on failure.
761 */
drm_dp_aux_register(struct drm_dp_aux * aux)762 int drm_dp_aux_register(struct drm_dp_aux *aux)
763 {
764 mutex_init(&aux->hw_mutex);
765
766 aux->ddc.algo = &drm_dp_i2c_algo;
767 aux->ddc.algo_data = aux;
768 aux->ddc.retries = 3;
769
770 aux->ddc.class = I2C_CLASS_DDC;
771 aux->ddc.owner = THIS_MODULE;
772 aux->ddc.dev.parent = aux->dev;
773 aux->ddc.dev.of_node = aux->dev->of_node;
774
775 strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
776 sizeof(aux->ddc.name));
777
778 return i2c_add_adapter(&aux->ddc);
779 }
780 EXPORT_SYMBOL(drm_dp_aux_register);
781
782 /**
783 * drm_dp_aux_unregister() - unregister an AUX adapter
784 * @aux: DisplayPort AUX channel
785 */
drm_dp_aux_unregister(struct drm_dp_aux * aux)786 void drm_dp_aux_unregister(struct drm_dp_aux *aux)
787 {
788 i2c_del_adapter(&aux->ddc);
789 }
790 EXPORT_SYMBOL(drm_dp_aux_unregister);
791