1 /*
2 * Core driver for the Synopsys DesignWare DMA Controller
3 *
4 * Copyright (C) 2007-2008 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
6 * Copyright (C) 2013 Intel Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/bitops.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmapool.h>
18 #include <linux/err.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/mm.h>
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/pm_runtime.h>
26
27 #include "../dmaengine.h"
28 #include "internal.h"
29
30 /*
31 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
32 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
33 * of which use ARM any more). See the "Databook" from Synopsys for
34 * information beyond what licensees probably provide.
35 *
36 * The driver has been tested with the Atmel AT32AP7000, which does not
37 * support descriptor writeback.
38 */
39
40 #define DWC_DEFAULT_CTLLO(_chan) ({ \
41 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
42 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
43 bool _is_slave = is_slave_direction(_dwc->direction); \
44 u8 _smsize = _is_slave ? _sconfig->src_maxburst : \
45 DW_DMA_MSIZE_16; \
46 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \
47 DW_DMA_MSIZE_16; \
48 \
49 (DWC_CTLL_DST_MSIZE(_dmsize) \
50 | DWC_CTLL_SRC_MSIZE(_smsize) \
51 | DWC_CTLL_LLP_D_EN \
52 | DWC_CTLL_LLP_S_EN \
53 | DWC_CTLL_DMS(_dwc->dst_master) \
54 | DWC_CTLL_SMS(_dwc->src_master)); \
55 })
56
57 /*
58 * Number of descriptors to allocate for each channel. This should be
59 * made configurable somehow; preferably, the clients (at least the
60 * ones using slave transfers) should be able to give us a hint.
61 */
62 #define NR_DESCS_PER_CHANNEL 64
63
64 /* The set of bus widths supported by the DMA controller */
65 #define DW_DMA_BUSWIDTHS \
66 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
67 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
68 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
69 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
70
71 /*----------------------------------------------------------------------*/
72
chan2dev(struct dma_chan * chan)73 static struct device *chan2dev(struct dma_chan *chan)
74 {
75 return &chan->dev->device;
76 }
77
dwc_first_active(struct dw_dma_chan * dwc)78 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
79 {
80 return to_dw_desc(dwc->active_list.next);
81 }
82
dwc_desc_get(struct dw_dma_chan * dwc)83 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
84 {
85 struct dw_desc *desc, *_desc;
86 struct dw_desc *ret = NULL;
87 unsigned int i = 0;
88 unsigned long flags;
89
90 spin_lock_irqsave(&dwc->lock, flags);
91 list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
92 i++;
93 if (async_tx_test_ack(&desc->txd)) {
94 list_del(&desc->desc_node);
95 ret = desc;
96 break;
97 }
98 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
99 }
100 spin_unlock_irqrestore(&dwc->lock, flags);
101
102 dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
103
104 return ret;
105 }
106
107 /*
108 * Move a descriptor, including any children, to the free list.
109 * `desc' must not be on any lists.
110 */
dwc_desc_put(struct dw_dma_chan * dwc,struct dw_desc * desc)111 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
112 {
113 unsigned long flags;
114
115 if (desc) {
116 struct dw_desc *child;
117
118 spin_lock_irqsave(&dwc->lock, flags);
119 list_for_each_entry(child, &desc->tx_list, desc_node)
120 dev_vdbg(chan2dev(&dwc->chan),
121 "moving child desc %p to freelist\n",
122 child);
123 list_splice_init(&desc->tx_list, &dwc->free_list);
124 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
125 list_add(&desc->desc_node, &dwc->free_list);
126 spin_unlock_irqrestore(&dwc->lock, flags);
127 }
128 }
129
dwc_initialize(struct dw_dma_chan * dwc)130 static void dwc_initialize(struct dw_dma_chan *dwc)
131 {
132 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
133 u32 cfghi = DWC_CFGH_FIFO_MODE;
134 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
135
136 if (dwc->initialized == true)
137 return;
138
139 cfghi |= DWC_CFGH_DST_PER(dwc->dst_id);
140 cfghi |= DWC_CFGH_SRC_PER(dwc->src_id);
141
142 channel_writel(dwc, CFG_LO, cfglo);
143 channel_writel(dwc, CFG_HI, cfghi);
144
145 /* Enable interrupts */
146 channel_set_bit(dw, MASK.XFER, dwc->mask);
147 channel_set_bit(dw, MASK.ERROR, dwc->mask);
148
149 dwc->initialized = true;
150 }
151
152 /*----------------------------------------------------------------------*/
153
dwc_fast_ffs(unsigned long long v)154 static inline unsigned int dwc_fast_ffs(unsigned long long v)
155 {
156 /*
157 * We can be a lot more clever here, but this should take care
158 * of the most common optimization.
159 */
160 if (!(v & 7))
161 return 3;
162 else if (!(v & 3))
163 return 2;
164 else if (!(v & 1))
165 return 1;
166 return 0;
167 }
168
dwc_dump_chan_regs(struct dw_dma_chan * dwc)169 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
170 {
171 dev_err(chan2dev(&dwc->chan),
172 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
173 channel_readl(dwc, SAR),
174 channel_readl(dwc, DAR),
175 channel_readl(dwc, LLP),
176 channel_readl(dwc, CTL_HI),
177 channel_readl(dwc, CTL_LO));
178 }
179
dwc_chan_disable(struct dw_dma * dw,struct dw_dma_chan * dwc)180 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
181 {
182 channel_clear_bit(dw, CH_EN, dwc->mask);
183 while (dma_readl(dw, CH_EN) & dwc->mask)
184 cpu_relax();
185 }
186
187 /*----------------------------------------------------------------------*/
188
189 /* Perform single block transfer */
dwc_do_single_block(struct dw_dma_chan * dwc,struct dw_desc * desc)190 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
191 struct dw_desc *desc)
192 {
193 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
194 u32 ctllo;
195
196 /*
197 * Software emulation of LLP mode relies on interrupts to continue
198 * multi block transfer.
199 */
200 ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
201
202 channel_writel(dwc, SAR, desc->lli.sar);
203 channel_writel(dwc, DAR, desc->lli.dar);
204 channel_writel(dwc, CTL_LO, ctllo);
205 channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
206 channel_set_bit(dw, CH_EN, dwc->mask);
207
208 /* Move pointer to next descriptor */
209 dwc->tx_node_active = dwc->tx_node_active->next;
210 }
211
212 /* Called with dwc->lock held and bh disabled */
dwc_dostart(struct dw_dma_chan * dwc,struct dw_desc * first)213 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
214 {
215 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
216 unsigned long was_soft_llp;
217
218 /* ASSERT: channel is idle */
219 if (dma_readl(dw, CH_EN) & dwc->mask) {
220 dev_err(chan2dev(&dwc->chan),
221 "%s: BUG: Attempted to start non-idle channel\n",
222 __func__);
223 dwc_dump_chan_regs(dwc);
224
225 /* The tasklet will hopefully advance the queue... */
226 return;
227 }
228
229 if (dwc->nollp) {
230 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
231 &dwc->flags);
232 if (was_soft_llp) {
233 dev_err(chan2dev(&dwc->chan),
234 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
235 return;
236 }
237
238 dwc_initialize(dwc);
239
240 dwc->residue = first->total_len;
241 dwc->tx_node_active = &first->tx_list;
242
243 /* Submit first block */
244 dwc_do_single_block(dwc, first);
245
246 return;
247 }
248
249 dwc_initialize(dwc);
250
251 channel_writel(dwc, LLP, first->txd.phys);
252 channel_writel(dwc, CTL_LO,
253 DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
254 channel_writel(dwc, CTL_HI, 0);
255 channel_set_bit(dw, CH_EN, dwc->mask);
256 }
257
dwc_dostart_first_queued(struct dw_dma_chan * dwc)258 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
259 {
260 struct dw_desc *desc;
261
262 if (list_empty(&dwc->queue))
263 return;
264
265 list_move(dwc->queue.next, &dwc->active_list);
266 desc = dwc_first_active(dwc);
267 dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie);
268 dwc_dostart(dwc, desc);
269 }
270
271 /*----------------------------------------------------------------------*/
272
273 static void
dwc_descriptor_complete(struct dw_dma_chan * dwc,struct dw_desc * desc,bool callback_required)274 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
275 bool callback_required)
276 {
277 dma_async_tx_callback callback = NULL;
278 void *param = NULL;
279 struct dma_async_tx_descriptor *txd = &desc->txd;
280 struct dw_desc *child;
281 unsigned long flags;
282
283 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
284
285 spin_lock_irqsave(&dwc->lock, flags);
286 dma_cookie_complete(txd);
287 if (callback_required) {
288 callback = txd->callback;
289 param = txd->callback_param;
290 }
291
292 /* async_tx_ack */
293 list_for_each_entry(child, &desc->tx_list, desc_node)
294 async_tx_ack(&child->txd);
295 async_tx_ack(&desc->txd);
296
297 list_splice_init(&desc->tx_list, &dwc->free_list);
298 list_move(&desc->desc_node, &dwc->free_list);
299
300 dma_descriptor_unmap(txd);
301 spin_unlock_irqrestore(&dwc->lock, flags);
302
303 if (callback)
304 callback(param);
305 }
306
dwc_complete_all(struct dw_dma * dw,struct dw_dma_chan * dwc)307 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
308 {
309 struct dw_desc *desc, *_desc;
310 LIST_HEAD(list);
311 unsigned long flags;
312
313 spin_lock_irqsave(&dwc->lock, flags);
314 if (dma_readl(dw, CH_EN) & dwc->mask) {
315 dev_err(chan2dev(&dwc->chan),
316 "BUG: XFER bit set, but channel not idle!\n");
317
318 /* Try to continue after resetting the channel... */
319 dwc_chan_disable(dw, dwc);
320 }
321
322 /*
323 * Submit queued descriptors ASAP, i.e. before we go through
324 * the completed ones.
325 */
326 list_splice_init(&dwc->active_list, &list);
327 dwc_dostart_first_queued(dwc);
328
329 spin_unlock_irqrestore(&dwc->lock, flags);
330
331 list_for_each_entry_safe(desc, _desc, &list, desc_node)
332 dwc_descriptor_complete(dwc, desc, true);
333 }
334
335 /* Returns how many bytes were already received from source */
dwc_get_sent(struct dw_dma_chan * dwc)336 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
337 {
338 u32 ctlhi = channel_readl(dwc, CTL_HI);
339 u32 ctllo = channel_readl(dwc, CTL_LO);
340
341 return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
342 }
343
dwc_scan_descriptors(struct dw_dma * dw,struct dw_dma_chan * dwc)344 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
345 {
346 dma_addr_t llp;
347 struct dw_desc *desc, *_desc;
348 struct dw_desc *child;
349 u32 status_xfer;
350 unsigned long flags;
351
352 spin_lock_irqsave(&dwc->lock, flags);
353 llp = channel_readl(dwc, LLP);
354 status_xfer = dma_readl(dw, RAW.XFER);
355
356 if (status_xfer & dwc->mask) {
357 /* Everything we've submitted is done */
358 dma_writel(dw, CLEAR.XFER, dwc->mask);
359
360 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
361 struct list_head *head, *active = dwc->tx_node_active;
362
363 /*
364 * We are inside first active descriptor.
365 * Otherwise something is really wrong.
366 */
367 desc = dwc_first_active(dwc);
368
369 head = &desc->tx_list;
370 if (active != head) {
371 /* Update desc to reflect last sent one */
372 if (active != head->next)
373 desc = to_dw_desc(active->prev);
374
375 dwc->residue -= desc->len;
376
377 child = to_dw_desc(active);
378
379 /* Submit next block */
380 dwc_do_single_block(dwc, child);
381
382 spin_unlock_irqrestore(&dwc->lock, flags);
383 return;
384 }
385
386 /* We are done here */
387 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
388 }
389
390 dwc->residue = 0;
391
392 spin_unlock_irqrestore(&dwc->lock, flags);
393
394 dwc_complete_all(dw, dwc);
395 return;
396 }
397
398 if (list_empty(&dwc->active_list)) {
399 dwc->residue = 0;
400 spin_unlock_irqrestore(&dwc->lock, flags);
401 return;
402 }
403
404 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
405 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
406 spin_unlock_irqrestore(&dwc->lock, flags);
407 return;
408 }
409
410 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
411
412 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
413 /* Initial residue value */
414 dwc->residue = desc->total_len;
415
416 /* Check first descriptors addr */
417 if (desc->txd.phys == llp) {
418 spin_unlock_irqrestore(&dwc->lock, flags);
419 return;
420 }
421
422 /* Check first descriptors llp */
423 if (desc->lli.llp == llp) {
424 /* This one is currently in progress */
425 dwc->residue -= dwc_get_sent(dwc);
426 spin_unlock_irqrestore(&dwc->lock, flags);
427 return;
428 }
429
430 dwc->residue -= desc->len;
431 list_for_each_entry(child, &desc->tx_list, desc_node) {
432 if (child->lli.llp == llp) {
433 /* Currently in progress */
434 dwc->residue -= dwc_get_sent(dwc);
435 spin_unlock_irqrestore(&dwc->lock, flags);
436 return;
437 }
438 dwc->residue -= child->len;
439 }
440
441 /*
442 * No descriptors so far seem to be in progress, i.e.
443 * this one must be done.
444 */
445 spin_unlock_irqrestore(&dwc->lock, flags);
446 dwc_descriptor_complete(dwc, desc, true);
447 spin_lock_irqsave(&dwc->lock, flags);
448 }
449
450 dev_err(chan2dev(&dwc->chan),
451 "BUG: All descriptors done, but channel not idle!\n");
452
453 /* Try to continue after resetting the channel... */
454 dwc_chan_disable(dw, dwc);
455
456 dwc_dostart_first_queued(dwc);
457 spin_unlock_irqrestore(&dwc->lock, flags);
458 }
459
dwc_dump_lli(struct dw_dma_chan * dwc,struct dw_lli * lli)460 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
461 {
462 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
463 lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
464 }
465
dwc_handle_error(struct dw_dma * dw,struct dw_dma_chan * dwc)466 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
467 {
468 struct dw_desc *bad_desc;
469 struct dw_desc *child;
470 unsigned long flags;
471
472 dwc_scan_descriptors(dw, dwc);
473
474 spin_lock_irqsave(&dwc->lock, flags);
475
476 /*
477 * The descriptor currently at the head of the active list is
478 * borked. Since we don't have any way to report errors, we'll
479 * just have to scream loudly and try to carry on.
480 */
481 bad_desc = dwc_first_active(dwc);
482 list_del_init(&bad_desc->desc_node);
483 list_move(dwc->queue.next, dwc->active_list.prev);
484
485 /* Clear the error flag and try to restart the controller */
486 dma_writel(dw, CLEAR.ERROR, dwc->mask);
487 if (!list_empty(&dwc->active_list))
488 dwc_dostart(dwc, dwc_first_active(dwc));
489
490 /*
491 * WARN may seem harsh, but since this only happens
492 * when someone submits a bad physical address in a
493 * descriptor, we should consider ourselves lucky that the
494 * controller flagged an error instead of scribbling over
495 * random memory locations.
496 */
497 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
498 " cookie: %d\n", bad_desc->txd.cookie);
499 dwc_dump_lli(dwc, &bad_desc->lli);
500 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
501 dwc_dump_lli(dwc, &child->lli);
502
503 spin_unlock_irqrestore(&dwc->lock, flags);
504
505 /* Pretend the descriptor completed successfully */
506 dwc_descriptor_complete(dwc, bad_desc, true);
507 }
508
509 /* --------------------- Cyclic DMA API extensions -------------------- */
510
dw_dma_get_src_addr(struct dma_chan * chan)511 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
512 {
513 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
514 return channel_readl(dwc, SAR);
515 }
516 EXPORT_SYMBOL(dw_dma_get_src_addr);
517
dw_dma_get_dst_addr(struct dma_chan * chan)518 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
519 {
520 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
521 return channel_readl(dwc, DAR);
522 }
523 EXPORT_SYMBOL(dw_dma_get_dst_addr);
524
525 /* Called with dwc->lock held and all DMAC interrupts disabled */
dwc_handle_cyclic(struct dw_dma * dw,struct dw_dma_chan * dwc,u32 status_block,u32 status_err,u32 status_xfer)526 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
527 u32 status_block, u32 status_err, u32 status_xfer)
528 {
529 unsigned long flags;
530
531 if (status_block & dwc->mask) {
532 void (*callback)(void *param);
533 void *callback_param;
534
535 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
536 channel_readl(dwc, LLP));
537 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
538
539 callback = dwc->cdesc->period_callback;
540 callback_param = dwc->cdesc->period_callback_param;
541
542 if (callback)
543 callback(callback_param);
544 }
545
546 /*
547 * Error and transfer complete are highly unlikely, and will most
548 * likely be due to a configuration error by the user.
549 */
550 if (unlikely(status_err & dwc->mask) ||
551 unlikely(status_xfer & dwc->mask)) {
552 int i;
553
554 dev_err(chan2dev(&dwc->chan),
555 "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
556 status_xfer ? "xfer" : "error");
557
558 spin_lock_irqsave(&dwc->lock, flags);
559
560 dwc_dump_chan_regs(dwc);
561
562 dwc_chan_disable(dw, dwc);
563
564 /* Make sure DMA does not restart by loading a new list */
565 channel_writel(dwc, LLP, 0);
566 channel_writel(dwc, CTL_LO, 0);
567 channel_writel(dwc, CTL_HI, 0);
568
569 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
570 dma_writel(dw, CLEAR.ERROR, dwc->mask);
571 dma_writel(dw, CLEAR.XFER, dwc->mask);
572
573 for (i = 0; i < dwc->cdesc->periods; i++)
574 dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
575
576 spin_unlock_irqrestore(&dwc->lock, flags);
577 }
578
579 /* Re-enable interrupts */
580 channel_set_bit(dw, MASK.BLOCK, dwc->mask);
581 }
582
583 /* ------------------------------------------------------------------------- */
584
dw_dma_tasklet(unsigned long data)585 static void dw_dma_tasklet(unsigned long data)
586 {
587 struct dw_dma *dw = (struct dw_dma *)data;
588 struct dw_dma_chan *dwc;
589 u32 status_block;
590 u32 status_xfer;
591 u32 status_err;
592 int i;
593
594 status_block = dma_readl(dw, RAW.BLOCK);
595 status_xfer = dma_readl(dw, RAW.XFER);
596 status_err = dma_readl(dw, RAW.ERROR);
597
598 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
599
600 for (i = 0; i < dw->dma.chancnt; i++) {
601 dwc = &dw->chan[i];
602 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
603 dwc_handle_cyclic(dw, dwc, status_block, status_err,
604 status_xfer);
605 else if (status_err & (1 << i))
606 dwc_handle_error(dw, dwc);
607 else if (status_xfer & (1 << i))
608 dwc_scan_descriptors(dw, dwc);
609 }
610
611 /* Re-enable interrupts */
612 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
613 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
614 }
615
dw_dma_interrupt(int irq,void * dev_id)616 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
617 {
618 struct dw_dma *dw = dev_id;
619 u32 status = dma_readl(dw, STATUS_INT);
620
621 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
622
623 /* Check if we have any interrupt from the DMAC */
624 if (!status || !dw->in_use)
625 return IRQ_NONE;
626
627 /*
628 * Just disable the interrupts. We'll turn them back on in the
629 * softirq handler.
630 */
631 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
632 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
633 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
634
635 status = dma_readl(dw, STATUS_INT);
636 if (status) {
637 dev_err(dw->dma.dev,
638 "BUG: Unexpected interrupts pending: 0x%x\n",
639 status);
640
641 /* Try to recover */
642 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
643 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
644 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
645 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
646 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
647 }
648
649 tasklet_schedule(&dw->tasklet);
650
651 return IRQ_HANDLED;
652 }
653
654 /*----------------------------------------------------------------------*/
655
dwc_tx_submit(struct dma_async_tx_descriptor * tx)656 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
657 {
658 struct dw_desc *desc = txd_to_dw_desc(tx);
659 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
660 dma_cookie_t cookie;
661 unsigned long flags;
662
663 spin_lock_irqsave(&dwc->lock, flags);
664 cookie = dma_cookie_assign(tx);
665
666 /*
667 * REVISIT: We should attempt to chain as many descriptors as
668 * possible, perhaps even appending to those already submitted
669 * for DMA. But this is hard to do in a race-free manner.
670 */
671
672 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie);
673 list_add_tail(&desc->desc_node, &dwc->queue);
674
675 spin_unlock_irqrestore(&dwc->lock, flags);
676
677 return cookie;
678 }
679
680 static struct dma_async_tx_descriptor *
dwc_prep_dma_memcpy(struct dma_chan * chan,dma_addr_t dest,dma_addr_t src,size_t len,unsigned long flags)681 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
682 size_t len, unsigned long flags)
683 {
684 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
685 struct dw_dma *dw = to_dw_dma(chan->device);
686 struct dw_desc *desc;
687 struct dw_desc *first;
688 struct dw_desc *prev;
689 size_t xfer_count;
690 size_t offset;
691 unsigned int src_width;
692 unsigned int dst_width;
693 unsigned int data_width;
694 u32 ctllo;
695
696 dev_vdbg(chan2dev(chan),
697 "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
698 &dest, &src, len, flags);
699
700 if (unlikely(!len)) {
701 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
702 return NULL;
703 }
704
705 dwc->direction = DMA_MEM_TO_MEM;
706
707 data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
708 dw->data_width[dwc->dst_master]);
709
710 src_width = dst_width = min_t(unsigned int, data_width,
711 dwc_fast_ffs(src | dest | len));
712
713 ctllo = DWC_DEFAULT_CTLLO(chan)
714 | DWC_CTLL_DST_WIDTH(dst_width)
715 | DWC_CTLL_SRC_WIDTH(src_width)
716 | DWC_CTLL_DST_INC
717 | DWC_CTLL_SRC_INC
718 | DWC_CTLL_FC_M2M;
719 prev = first = NULL;
720
721 for (offset = 0; offset < len; offset += xfer_count << src_width) {
722 xfer_count = min_t(size_t, (len - offset) >> src_width,
723 dwc->block_size);
724
725 desc = dwc_desc_get(dwc);
726 if (!desc)
727 goto err_desc_get;
728
729 desc->lli.sar = src + offset;
730 desc->lli.dar = dest + offset;
731 desc->lli.ctllo = ctllo;
732 desc->lli.ctlhi = xfer_count;
733 desc->len = xfer_count << src_width;
734
735 if (!first) {
736 first = desc;
737 } else {
738 prev->lli.llp = desc->txd.phys;
739 list_add_tail(&desc->desc_node,
740 &first->tx_list);
741 }
742 prev = desc;
743 }
744
745 if (flags & DMA_PREP_INTERRUPT)
746 /* Trigger interrupt after last block */
747 prev->lli.ctllo |= DWC_CTLL_INT_EN;
748
749 prev->lli.llp = 0;
750 first->txd.flags = flags;
751 first->total_len = len;
752
753 return &first->txd;
754
755 err_desc_get:
756 dwc_desc_put(dwc, first);
757 return NULL;
758 }
759
760 static struct dma_async_tx_descriptor *
dwc_prep_slave_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned int sg_len,enum dma_transfer_direction direction,unsigned long flags,void * context)761 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
762 unsigned int sg_len, enum dma_transfer_direction direction,
763 unsigned long flags, void *context)
764 {
765 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
766 struct dw_dma *dw = to_dw_dma(chan->device);
767 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
768 struct dw_desc *prev;
769 struct dw_desc *first;
770 u32 ctllo;
771 dma_addr_t reg;
772 unsigned int reg_width;
773 unsigned int mem_width;
774 unsigned int data_width;
775 unsigned int i;
776 struct scatterlist *sg;
777 size_t total_len = 0;
778
779 dev_vdbg(chan2dev(chan), "%s\n", __func__);
780
781 if (unlikely(!is_slave_direction(direction) || !sg_len))
782 return NULL;
783
784 dwc->direction = direction;
785
786 prev = first = NULL;
787
788 switch (direction) {
789 case DMA_MEM_TO_DEV:
790 reg_width = __ffs(sconfig->dst_addr_width);
791 reg = sconfig->dst_addr;
792 ctllo = (DWC_DEFAULT_CTLLO(chan)
793 | DWC_CTLL_DST_WIDTH(reg_width)
794 | DWC_CTLL_DST_FIX
795 | DWC_CTLL_SRC_INC);
796
797 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
798 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
799
800 data_width = dw->data_width[dwc->src_master];
801
802 for_each_sg(sgl, sg, sg_len, i) {
803 struct dw_desc *desc;
804 u32 len, dlen, mem;
805
806 mem = sg_dma_address(sg);
807 len = sg_dma_len(sg);
808
809 mem_width = min_t(unsigned int,
810 data_width, dwc_fast_ffs(mem | len));
811
812 slave_sg_todev_fill_desc:
813 desc = dwc_desc_get(dwc);
814 if (!desc)
815 goto err_desc_get;
816
817 desc->lli.sar = mem;
818 desc->lli.dar = reg;
819 desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
820 if ((len >> mem_width) > dwc->block_size) {
821 dlen = dwc->block_size << mem_width;
822 mem += dlen;
823 len -= dlen;
824 } else {
825 dlen = len;
826 len = 0;
827 }
828
829 desc->lli.ctlhi = dlen >> mem_width;
830 desc->len = dlen;
831
832 if (!first) {
833 first = desc;
834 } else {
835 prev->lli.llp = desc->txd.phys;
836 list_add_tail(&desc->desc_node,
837 &first->tx_list);
838 }
839 prev = desc;
840 total_len += dlen;
841
842 if (len)
843 goto slave_sg_todev_fill_desc;
844 }
845 break;
846 case DMA_DEV_TO_MEM:
847 reg_width = __ffs(sconfig->src_addr_width);
848 reg = sconfig->src_addr;
849 ctllo = (DWC_DEFAULT_CTLLO(chan)
850 | DWC_CTLL_SRC_WIDTH(reg_width)
851 | DWC_CTLL_DST_INC
852 | DWC_CTLL_SRC_FIX);
853
854 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
855 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
856
857 data_width = dw->data_width[dwc->dst_master];
858
859 for_each_sg(sgl, sg, sg_len, i) {
860 struct dw_desc *desc;
861 u32 len, dlen, mem;
862
863 mem = sg_dma_address(sg);
864 len = sg_dma_len(sg);
865
866 mem_width = min_t(unsigned int,
867 data_width, dwc_fast_ffs(mem | len));
868
869 slave_sg_fromdev_fill_desc:
870 desc = dwc_desc_get(dwc);
871 if (!desc)
872 goto err_desc_get;
873
874 desc->lli.sar = reg;
875 desc->lli.dar = mem;
876 desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
877 if ((len >> reg_width) > dwc->block_size) {
878 dlen = dwc->block_size << reg_width;
879 mem += dlen;
880 len -= dlen;
881 } else {
882 dlen = len;
883 len = 0;
884 }
885 desc->lli.ctlhi = dlen >> reg_width;
886 desc->len = dlen;
887
888 if (!first) {
889 first = desc;
890 } else {
891 prev->lli.llp = desc->txd.phys;
892 list_add_tail(&desc->desc_node,
893 &first->tx_list);
894 }
895 prev = desc;
896 total_len += dlen;
897
898 if (len)
899 goto slave_sg_fromdev_fill_desc;
900 }
901 break;
902 default:
903 return NULL;
904 }
905
906 if (flags & DMA_PREP_INTERRUPT)
907 /* Trigger interrupt after last block */
908 prev->lli.ctllo |= DWC_CTLL_INT_EN;
909
910 prev->lli.llp = 0;
911 first->total_len = total_len;
912
913 return &first->txd;
914
915 err_desc_get:
916 dev_err(chan2dev(chan),
917 "not enough descriptors available. Direction %d\n", direction);
918 dwc_desc_put(dwc, first);
919 return NULL;
920 }
921
dw_dma_filter(struct dma_chan * chan,void * param)922 bool dw_dma_filter(struct dma_chan *chan, void *param)
923 {
924 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
925 struct dw_dma_slave *dws = param;
926
927 if (dws->dma_dev != chan->device->dev)
928 return false;
929
930 /* We have to copy data since dws can be temporary storage */
931
932 dwc->src_id = dws->src_id;
933 dwc->dst_id = dws->dst_id;
934
935 dwc->src_master = dws->src_master;
936 dwc->dst_master = dws->dst_master;
937
938 return true;
939 }
940 EXPORT_SYMBOL_GPL(dw_dma_filter);
941
942 /*
943 * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
944 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
945 *
946 * NOTE: burst size 2 is not supported by controller.
947 *
948 * This can be done by finding least significant bit set: n & (n - 1)
949 */
convert_burst(u32 * maxburst)950 static inline void convert_burst(u32 *maxburst)
951 {
952 if (*maxburst > 1)
953 *maxburst = fls(*maxburst) - 2;
954 else
955 *maxburst = 0;
956 }
957
dwc_config(struct dma_chan * chan,struct dma_slave_config * sconfig)958 static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
959 {
960 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
961
962 /* Check if chan will be configured for slave transfers */
963 if (!is_slave_direction(sconfig->direction))
964 return -EINVAL;
965
966 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
967 dwc->direction = sconfig->direction;
968
969 convert_burst(&dwc->dma_sconfig.src_maxburst);
970 convert_burst(&dwc->dma_sconfig.dst_maxburst);
971
972 return 0;
973 }
974
dwc_pause(struct dma_chan * chan)975 static int dwc_pause(struct dma_chan *chan)
976 {
977 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
978 unsigned long flags;
979 unsigned int count = 20; /* timeout iterations */
980 u32 cfglo;
981
982 spin_lock_irqsave(&dwc->lock, flags);
983
984 cfglo = channel_readl(dwc, CFG_LO);
985 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
986 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
987 udelay(2);
988
989 dwc->paused = true;
990
991 spin_unlock_irqrestore(&dwc->lock, flags);
992
993 return 0;
994 }
995
dwc_chan_resume(struct dw_dma_chan * dwc)996 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
997 {
998 u32 cfglo = channel_readl(dwc, CFG_LO);
999
1000 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1001
1002 dwc->paused = false;
1003 }
1004
dwc_resume(struct dma_chan * chan)1005 static int dwc_resume(struct dma_chan *chan)
1006 {
1007 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1008 unsigned long flags;
1009
1010 if (!dwc->paused)
1011 return 0;
1012
1013 spin_lock_irqsave(&dwc->lock, flags);
1014
1015 dwc_chan_resume(dwc);
1016
1017 spin_unlock_irqrestore(&dwc->lock, flags);
1018
1019 return 0;
1020 }
1021
dwc_terminate_all(struct dma_chan * chan)1022 static int dwc_terminate_all(struct dma_chan *chan)
1023 {
1024 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1025 struct dw_dma *dw = to_dw_dma(chan->device);
1026 struct dw_desc *desc, *_desc;
1027 unsigned long flags;
1028 LIST_HEAD(list);
1029
1030 spin_lock_irqsave(&dwc->lock, flags);
1031
1032 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1033
1034 dwc_chan_disable(dw, dwc);
1035
1036 dwc_chan_resume(dwc);
1037
1038 /* active_list entries will end up before queued entries */
1039 list_splice_init(&dwc->queue, &list);
1040 list_splice_init(&dwc->active_list, &list);
1041
1042 spin_unlock_irqrestore(&dwc->lock, flags);
1043
1044 /* Flush all pending and queued descriptors */
1045 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1046 dwc_descriptor_complete(dwc, desc, false);
1047
1048 return 0;
1049 }
1050
dwc_get_residue(struct dw_dma_chan * dwc)1051 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1052 {
1053 unsigned long flags;
1054 u32 residue;
1055
1056 spin_lock_irqsave(&dwc->lock, flags);
1057
1058 residue = dwc->residue;
1059 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1060 residue -= dwc_get_sent(dwc);
1061
1062 spin_unlock_irqrestore(&dwc->lock, flags);
1063 return residue;
1064 }
1065
1066 static enum dma_status
dwc_tx_status(struct dma_chan * chan,dma_cookie_t cookie,struct dma_tx_state * txstate)1067 dwc_tx_status(struct dma_chan *chan,
1068 dma_cookie_t cookie,
1069 struct dma_tx_state *txstate)
1070 {
1071 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1072 enum dma_status ret;
1073
1074 ret = dma_cookie_status(chan, cookie, txstate);
1075 if (ret == DMA_COMPLETE)
1076 return ret;
1077
1078 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1079
1080 ret = dma_cookie_status(chan, cookie, txstate);
1081 if (ret != DMA_COMPLETE)
1082 dma_set_residue(txstate, dwc_get_residue(dwc));
1083
1084 if (dwc->paused && ret == DMA_IN_PROGRESS)
1085 return DMA_PAUSED;
1086
1087 return ret;
1088 }
1089
dwc_issue_pending(struct dma_chan * chan)1090 static void dwc_issue_pending(struct dma_chan *chan)
1091 {
1092 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1093 unsigned long flags;
1094
1095 spin_lock_irqsave(&dwc->lock, flags);
1096 if (list_empty(&dwc->active_list))
1097 dwc_dostart_first_queued(dwc);
1098 spin_unlock_irqrestore(&dwc->lock, flags);
1099 }
1100
1101 /*----------------------------------------------------------------------*/
1102
dw_dma_off(struct dw_dma * dw)1103 static void dw_dma_off(struct dw_dma *dw)
1104 {
1105 int i;
1106
1107 dma_writel(dw, CFG, 0);
1108
1109 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1110 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1111 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1112 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1113 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1114
1115 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1116 cpu_relax();
1117
1118 for (i = 0; i < dw->dma.chancnt; i++)
1119 dw->chan[i].initialized = false;
1120 }
1121
dw_dma_on(struct dw_dma * dw)1122 static void dw_dma_on(struct dw_dma *dw)
1123 {
1124 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1125 }
1126
dwc_alloc_chan_resources(struct dma_chan * chan)1127 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1128 {
1129 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1130 struct dw_dma *dw = to_dw_dma(chan->device);
1131 struct dw_desc *desc;
1132 int i;
1133 unsigned long flags;
1134
1135 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1136
1137 /* ASSERT: channel is idle */
1138 if (dma_readl(dw, CH_EN) & dwc->mask) {
1139 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1140 return -EIO;
1141 }
1142
1143 dma_cookie_init(chan);
1144
1145 /*
1146 * NOTE: some controllers may have additional features that we
1147 * need to initialize here, like "scatter-gather" (which
1148 * doesn't mean what you think it means), and status writeback.
1149 */
1150
1151 /*
1152 * We need controller-specific data to set up slave transfers.
1153 */
1154 if (chan->private && !dw_dma_filter(chan, chan->private)) {
1155 dev_warn(chan2dev(chan), "Wrong controller-specific data\n");
1156 return -EINVAL;
1157 }
1158
1159 /* Enable controller here if needed */
1160 if (!dw->in_use)
1161 dw_dma_on(dw);
1162 dw->in_use |= dwc->mask;
1163
1164 spin_lock_irqsave(&dwc->lock, flags);
1165 i = dwc->descs_allocated;
1166 while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1167 dma_addr_t phys;
1168
1169 spin_unlock_irqrestore(&dwc->lock, flags);
1170
1171 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1172 if (!desc)
1173 goto err_desc_alloc;
1174
1175 memset(desc, 0, sizeof(struct dw_desc));
1176
1177 INIT_LIST_HEAD(&desc->tx_list);
1178 dma_async_tx_descriptor_init(&desc->txd, chan);
1179 desc->txd.tx_submit = dwc_tx_submit;
1180 desc->txd.flags = DMA_CTRL_ACK;
1181 desc->txd.phys = phys;
1182
1183 dwc_desc_put(dwc, desc);
1184
1185 spin_lock_irqsave(&dwc->lock, flags);
1186 i = ++dwc->descs_allocated;
1187 }
1188
1189 spin_unlock_irqrestore(&dwc->lock, flags);
1190
1191 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1192
1193 return i;
1194
1195 err_desc_alloc:
1196 dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1197
1198 return i;
1199 }
1200
dwc_free_chan_resources(struct dma_chan * chan)1201 static void dwc_free_chan_resources(struct dma_chan *chan)
1202 {
1203 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1204 struct dw_dma *dw = to_dw_dma(chan->device);
1205 struct dw_desc *desc, *_desc;
1206 unsigned long flags;
1207 LIST_HEAD(list);
1208
1209 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1210 dwc->descs_allocated);
1211
1212 /* ASSERT: channel is idle */
1213 BUG_ON(!list_empty(&dwc->active_list));
1214 BUG_ON(!list_empty(&dwc->queue));
1215 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1216
1217 spin_lock_irqsave(&dwc->lock, flags);
1218 list_splice_init(&dwc->free_list, &list);
1219 dwc->descs_allocated = 0;
1220
1221 /* Clear custom channel configuration */
1222 dwc->src_id = 0;
1223 dwc->dst_id = 0;
1224
1225 dwc->src_master = 0;
1226 dwc->dst_master = 0;
1227
1228 dwc->initialized = false;
1229
1230 /* Disable interrupts */
1231 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1232 channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
1233 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1234
1235 spin_unlock_irqrestore(&dwc->lock, flags);
1236
1237 /* Disable controller in case it was a last user */
1238 dw->in_use &= ~dwc->mask;
1239 if (!dw->in_use)
1240 dw_dma_off(dw);
1241
1242 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1243 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1244 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1245 }
1246
1247 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1248 }
1249
1250 /* --------------------- Cyclic DMA API extensions -------------------- */
1251
1252 /**
1253 * dw_dma_cyclic_start - start the cyclic DMA transfer
1254 * @chan: the DMA channel to start
1255 *
1256 * Must be called with soft interrupts disabled. Returns zero on success or
1257 * -errno on failure.
1258 */
dw_dma_cyclic_start(struct dma_chan * chan)1259 int dw_dma_cyclic_start(struct dma_chan *chan)
1260 {
1261 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1262 struct dw_dma *dw = to_dw_dma(chan->device);
1263 unsigned long flags;
1264
1265 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1266 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1267 return -ENODEV;
1268 }
1269
1270 spin_lock_irqsave(&dwc->lock, flags);
1271
1272 /* Enable interrupts to perform cyclic transfer */
1273 channel_set_bit(dw, MASK.BLOCK, dwc->mask);
1274
1275 dwc_dostart(dwc, dwc->cdesc->desc[0]);
1276
1277 spin_unlock_irqrestore(&dwc->lock, flags);
1278
1279 return 0;
1280 }
1281 EXPORT_SYMBOL(dw_dma_cyclic_start);
1282
1283 /**
1284 * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1285 * @chan: the DMA channel to stop
1286 *
1287 * Must be called with soft interrupts disabled.
1288 */
dw_dma_cyclic_stop(struct dma_chan * chan)1289 void dw_dma_cyclic_stop(struct dma_chan *chan)
1290 {
1291 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1292 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1293 unsigned long flags;
1294
1295 spin_lock_irqsave(&dwc->lock, flags);
1296
1297 dwc_chan_disable(dw, dwc);
1298
1299 spin_unlock_irqrestore(&dwc->lock, flags);
1300 }
1301 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1302
1303 /**
1304 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1305 * @chan: the DMA channel to prepare
1306 * @buf_addr: physical DMA address where the buffer starts
1307 * @buf_len: total number of bytes for the entire buffer
1308 * @period_len: number of bytes for each period
1309 * @direction: transfer direction, to or from device
1310 *
1311 * Must be called before trying to start the transfer. Returns a valid struct
1312 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1313 */
dw_dma_cyclic_prep(struct dma_chan * chan,dma_addr_t buf_addr,size_t buf_len,size_t period_len,enum dma_transfer_direction direction)1314 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1315 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1316 enum dma_transfer_direction direction)
1317 {
1318 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1319 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
1320 struct dw_cyclic_desc *cdesc;
1321 struct dw_cyclic_desc *retval = NULL;
1322 struct dw_desc *desc;
1323 struct dw_desc *last = NULL;
1324 unsigned long was_cyclic;
1325 unsigned int reg_width;
1326 unsigned int periods;
1327 unsigned int i;
1328 unsigned long flags;
1329
1330 spin_lock_irqsave(&dwc->lock, flags);
1331 if (dwc->nollp) {
1332 spin_unlock_irqrestore(&dwc->lock, flags);
1333 dev_dbg(chan2dev(&dwc->chan),
1334 "channel doesn't support LLP transfers\n");
1335 return ERR_PTR(-EINVAL);
1336 }
1337
1338 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1339 spin_unlock_irqrestore(&dwc->lock, flags);
1340 dev_dbg(chan2dev(&dwc->chan),
1341 "queue and/or active list are not empty\n");
1342 return ERR_PTR(-EBUSY);
1343 }
1344
1345 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1346 spin_unlock_irqrestore(&dwc->lock, flags);
1347 if (was_cyclic) {
1348 dev_dbg(chan2dev(&dwc->chan),
1349 "channel already prepared for cyclic DMA\n");
1350 return ERR_PTR(-EBUSY);
1351 }
1352
1353 retval = ERR_PTR(-EINVAL);
1354
1355 if (unlikely(!is_slave_direction(direction)))
1356 goto out_err;
1357
1358 dwc->direction = direction;
1359
1360 if (direction == DMA_MEM_TO_DEV)
1361 reg_width = __ffs(sconfig->dst_addr_width);
1362 else
1363 reg_width = __ffs(sconfig->src_addr_width);
1364
1365 periods = buf_len / period_len;
1366
1367 /* Check for too big/unaligned periods and unaligned DMA buffer. */
1368 if (period_len > (dwc->block_size << reg_width))
1369 goto out_err;
1370 if (unlikely(period_len & ((1 << reg_width) - 1)))
1371 goto out_err;
1372 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1373 goto out_err;
1374
1375 retval = ERR_PTR(-ENOMEM);
1376
1377 if (periods > NR_DESCS_PER_CHANNEL)
1378 goto out_err;
1379
1380 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1381 if (!cdesc)
1382 goto out_err;
1383
1384 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1385 if (!cdesc->desc)
1386 goto out_err_alloc;
1387
1388 for (i = 0; i < periods; i++) {
1389 desc = dwc_desc_get(dwc);
1390 if (!desc)
1391 goto out_err_desc_get;
1392
1393 switch (direction) {
1394 case DMA_MEM_TO_DEV:
1395 desc->lli.dar = sconfig->dst_addr;
1396 desc->lli.sar = buf_addr + (period_len * i);
1397 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1398 | DWC_CTLL_DST_WIDTH(reg_width)
1399 | DWC_CTLL_SRC_WIDTH(reg_width)
1400 | DWC_CTLL_DST_FIX
1401 | DWC_CTLL_SRC_INC
1402 | DWC_CTLL_INT_EN);
1403
1404 desc->lli.ctllo |= sconfig->device_fc ?
1405 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1406 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1407
1408 break;
1409 case DMA_DEV_TO_MEM:
1410 desc->lli.dar = buf_addr + (period_len * i);
1411 desc->lli.sar = sconfig->src_addr;
1412 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1413 | DWC_CTLL_SRC_WIDTH(reg_width)
1414 | DWC_CTLL_DST_WIDTH(reg_width)
1415 | DWC_CTLL_DST_INC
1416 | DWC_CTLL_SRC_FIX
1417 | DWC_CTLL_INT_EN);
1418
1419 desc->lli.ctllo |= sconfig->device_fc ?
1420 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1421 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1422
1423 break;
1424 default:
1425 break;
1426 }
1427
1428 desc->lli.ctlhi = (period_len >> reg_width);
1429 cdesc->desc[i] = desc;
1430
1431 if (last)
1432 last->lli.llp = desc->txd.phys;
1433
1434 last = desc;
1435 }
1436
1437 /* Let's make a cyclic list */
1438 last->lli.llp = cdesc->desc[0]->txd.phys;
1439
1440 dev_dbg(chan2dev(&dwc->chan),
1441 "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1442 &buf_addr, buf_len, period_len, periods);
1443
1444 cdesc->periods = periods;
1445 dwc->cdesc = cdesc;
1446
1447 return cdesc;
1448
1449 out_err_desc_get:
1450 while (i--)
1451 dwc_desc_put(dwc, cdesc->desc[i]);
1452 out_err_alloc:
1453 kfree(cdesc);
1454 out_err:
1455 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1456 return (struct dw_cyclic_desc *)retval;
1457 }
1458 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1459
1460 /**
1461 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1462 * @chan: the DMA channel to free
1463 */
dw_dma_cyclic_free(struct dma_chan * chan)1464 void dw_dma_cyclic_free(struct dma_chan *chan)
1465 {
1466 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1467 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1468 struct dw_cyclic_desc *cdesc = dwc->cdesc;
1469 int i;
1470 unsigned long flags;
1471
1472 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1473
1474 if (!cdesc)
1475 return;
1476
1477 spin_lock_irqsave(&dwc->lock, flags);
1478
1479 dwc_chan_disable(dw, dwc);
1480
1481 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
1482 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1483 dma_writel(dw, CLEAR.XFER, dwc->mask);
1484
1485 spin_unlock_irqrestore(&dwc->lock, flags);
1486
1487 for (i = 0; i < cdesc->periods; i++)
1488 dwc_desc_put(dwc, cdesc->desc[i]);
1489
1490 kfree(cdesc->desc);
1491 kfree(cdesc);
1492
1493 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1494 }
1495 EXPORT_SYMBOL(dw_dma_cyclic_free);
1496
1497 /*----------------------------------------------------------------------*/
1498
dw_dma_probe(struct dw_dma_chip * chip,struct dw_dma_platform_data * pdata)1499 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1500 {
1501 struct dw_dma *dw;
1502 bool autocfg = false;
1503 unsigned int dw_params;
1504 unsigned int max_blk_size = 0;
1505 int err;
1506 int i;
1507
1508 dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
1509 if (!dw)
1510 return -ENOMEM;
1511
1512 dw->regs = chip->regs;
1513 chip->dw = dw;
1514
1515 pm_runtime_get_sync(chip->dev);
1516
1517 if (!pdata) {
1518 dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1519 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1520
1521 autocfg = dw_params >> DW_PARAMS_EN & 1;
1522 if (!autocfg) {
1523 err = -EINVAL;
1524 goto err_pdata;
1525 }
1526
1527 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
1528 if (!pdata) {
1529 err = -ENOMEM;
1530 goto err_pdata;
1531 }
1532
1533 /* Get hardware configuration parameters */
1534 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
1535 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1536 for (i = 0; i < pdata->nr_masters; i++) {
1537 pdata->data_width[i] =
1538 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1539 }
1540 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1541
1542 /* Fill platform data with the default values */
1543 pdata->is_private = true;
1544 pdata->is_memcpy = true;
1545 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1546 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1547 } else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1548 err = -EINVAL;
1549 goto err_pdata;
1550 }
1551
1552 dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
1553 GFP_KERNEL);
1554 if (!dw->chan) {
1555 err = -ENOMEM;
1556 goto err_pdata;
1557 }
1558
1559 /* Get hardware configuration parameters */
1560 dw->nr_masters = pdata->nr_masters;
1561 for (i = 0; i < dw->nr_masters; i++)
1562 dw->data_width[i] = pdata->data_width[i];
1563
1564 /* Calculate all channel mask before DMA setup */
1565 dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1566
1567 /* Force dma off, just in case */
1568 dw_dma_off(dw);
1569
1570 /* Create a pool of consistent memory blocks for hardware descriptors */
1571 dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1572 sizeof(struct dw_desc), 4, 0);
1573 if (!dw->desc_pool) {
1574 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1575 err = -ENOMEM;
1576 goto err_pdata;
1577 }
1578
1579 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1580
1581 err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1582 "dw_dmac", dw);
1583 if (err)
1584 goto err_pdata;
1585
1586 INIT_LIST_HEAD(&dw->dma.channels);
1587 for (i = 0; i < pdata->nr_channels; i++) {
1588 struct dw_dma_chan *dwc = &dw->chan[i];
1589
1590 dwc->chan.device = &dw->dma;
1591 dma_cookie_init(&dwc->chan);
1592 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1593 list_add_tail(&dwc->chan.device_node,
1594 &dw->dma.channels);
1595 else
1596 list_add(&dwc->chan.device_node, &dw->dma.channels);
1597
1598 /* 7 is highest priority & 0 is lowest. */
1599 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1600 dwc->priority = pdata->nr_channels - i - 1;
1601 else
1602 dwc->priority = i;
1603
1604 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1605 spin_lock_init(&dwc->lock);
1606 dwc->mask = 1 << i;
1607
1608 INIT_LIST_HEAD(&dwc->active_list);
1609 INIT_LIST_HEAD(&dwc->queue);
1610 INIT_LIST_HEAD(&dwc->free_list);
1611
1612 channel_clear_bit(dw, CH_EN, dwc->mask);
1613
1614 dwc->direction = DMA_TRANS_NONE;
1615
1616 /* Hardware configuration */
1617 if (autocfg) {
1618 unsigned int dwc_params;
1619 unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1;
1620 void __iomem *addr = chip->regs + r * sizeof(u32);
1621
1622 dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
1623
1624 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1625 dwc_params);
1626
1627 /*
1628 * Decode maximum block size for given channel. The
1629 * stored 4 bit value represents blocks from 0x00 for 3
1630 * up to 0x0a for 4095.
1631 */
1632 dwc->block_size =
1633 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1634 dwc->nollp =
1635 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1636 } else {
1637 dwc->block_size = pdata->block_size;
1638
1639 /* Check if channel supports multi block transfer */
1640 channel_writel(dwc, LLP, 0xfffffffc);
1641 dwc->nollp =
1642 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1643 channel_writel(dwc, LLP, 0);
1644 }
1645 }
1646
1647 /* Clear all interrupts on all channels. */
1648 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1649 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1650 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1651 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1652 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1653
1654 /* Set capabilities */
1655 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1656 if (pdata->is_private)
1657 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1658 if (pdata->is_memcpy)
1659 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1660
1661 dw->dma.dev = chip->dev;
1662 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1663 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1664
1665 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1666 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1667
1668 dw->dma.device_config = dwc_config;
1669 dw->dma.device_pause = dwc_pause;
1670 dw->dma.device_resume = dwc_resume;
1671 dw->dma.device_terminate_all = dwc_terminate_all;
1672
1673 dw->dma.device_tx_status = dwc_tx_status;
1674 dw->dma.device_issue_pending = dwc_issue_pending;
1675
1676 /* DMA capabilities */
1677 dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
1678 dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
1679 dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
1680 BIT(DMA_MEM_TO_MEM);
1681 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1682
1683 err = dma_async_device_register(&dw->dma);
1684 if (err)
1685 goto err_dma_register;
1686
1687 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1688 pdata->nr_channels);
1689
1690 pm_runtime_put_sync_suspend(chip->dev);
1691
1692 return 0;
1693
1694 err_dma_register:
1695 free_irq(chip->irq, dw);
1696 err_pdata:
1697 pm_runtime_put_sync_suspend(chip->dev);
1698 return err;
1699 }
1700 EXPORT_SYMBOL_GPL(dw_dma_probe);
1701
dw_dma_remove(struct dw_dma_chip * chip)1702 int dw_dma_remove(struct dw_dma_chip *chip)
1703 {
1704 struct dw_dma *dw = chip->dw;
1705 struct dw_dma_chan *dwc, *_dwc;
1706
1707 pm_runtime_get_sync(chip->dev);
1708
1709 dw_dma_off(dw);
1710 dma_async_device_unregister(&dw->dma);
1711
1712 free_irq(chip->irq, dw);
1713 tasklet_kill(&dw->tasklet);
1714
1715 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1716 chan.device_node) {
1717 list_del(&dwc->chan.device_node);
1718 channel_clear_bit(dw, CH_EN, dwc->mask);
1719 }
1720
1721 pm_runtime_put_sync_suspend(chip->dev);
1722 return 0;
1723 }
1724 EXPORT_SYMBOL_GPL(dw_dma_remove);
1725
dw_dma_disable(struct dw_dma_chip * chip)1726 int dw_dma_disable(struct dw_dma_chip *chip)
1727 {
1728 struct dw_dma *dw = chip->dw;
1729
1730 dw_dma_off(dw);
1731 return 0;
1732 }
1733 EXPORT_SYMBOL_GPL(dw_dma_disable);
1734
dw_dma_enable(struct dw_dma_chip * chip)1735 int dw_dma_enable(struct dw_dma_chip *chip)
1736 {
1737 struct dw_dma *dw = chip->dw;
1738
1739 dw_dma_on(dw);
1740 return 0;
1741 }
1742 EXPORT_SYMBOL_GPL(dw_dma_enable);
1743
1744 MODULE_LICENSE("GPL v2");
1745 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1746 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1747 MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");
1748