1 /* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2015 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
21
22 #include "e1000.h"
23
24 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
25 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
26 u16 *data, bool read, bool page_set);
27 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
28 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
29 u16 *data, bool read);
30
31 /* Cable length tables */
32 static const u16 e1000_m88_cable_length_table[] = {
33 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
34 };
35
36 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
37 ARRAY_SIZE(e1000_m88_cable_length_table)
38
39 static const u16 e1000_igp_2_cable_length_table[] = {
40 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
41 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
42 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
43 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
44 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
45 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
46 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
47 124
48 };
49
50 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
51 ARRAY_SIZE(e1000_igp_2_cable_length_table)
52
53 /**
54 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
55 * @hw: pointer to the HW structure
56 *
57 * Read the PHY management control register and check whether a PHY reset
58 * is blocked. If a reset is not blocked return 0, otherwise
59 * return E1000_BLK_PHY_RESET (12).
60 **/
e1000e_check_reset_block_generic(struct e1000_hw * hw)61 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
62 {
63 u32 manc;
64
65 manc = er32(MANC);
66
67 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
68 }
69
70 /**
71 * e1000e_get_phy_id - Retrieve the PHY ID and revision
72 * @hw: pointer to the HW structure
73 *
74 * Reads the PHY registers and stores the PHY ID and possibly the PHY
75 * revision in the hardware structure.
76 **/
e1000e_get_phy_id(struct e1000_hw * hw)77 s32 e1000e_get_phy_id(struct e1000_hw *hw)
78 {
79 struct e1000_phy_info *phy = &hw->phy;
80 s32 ret_val = 0;
81 u16 phy_id;
82 u16 retry_count = 0;
83
84 if (!phy->ops.read_reg)
85 return 0;
86
87 while (retry_count < 2) {
88 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
89 if (ret_val)
90 return ret_val;
91
92 phy->id = (u32)(phy_id << 16);
93 usleep_range(20, 40);
94 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
95 if (ret_val)
96 return ret_val;
97
98 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
99 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
100
101 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
102 return 0;
103
104 retry_count++;
105 }
106
107 return 0;
108 }
109
110 /**
111 * e1000e_phy_reset_dsp - Reset PHY DSP
112 * @hw: pointer to the HW structure
113 *
114 * Reset the digital signal processor.
115 **/
e1000e_phy_reset_dsp(struct e1000_hw * hw)116 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
117 {
118 s32 ret_val;
119
120 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
121 if (ret_val)
122 return ret_val;
123
124 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
125 }
126
127 /**
128 * e1000e_read_phy_reg_mdic - Read MDI control register
129 * @hw: pointer to the HW structure
130 * @offset: register offset to be read
131 * @data: pointer to the read data
132 *
133 * Reads the MDI control register in the PHY at offset and stores the
134 * information read to data.
135 **/
e1000e_read_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 * data)136 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
137 {
138 struct e1000_phy_info *phy = &hw->phy;
139 u32 i, mdic = 0;
140
141 if (offset > MAX_PHY_REG_ADDRESS) {
142 e_dbg("PHY Address %d is out of range\n", offset);
143 return -E1000_ERR_PARAM;
144 }
145
146 /* Set up Op-code, Phy Address, and register offset in the MDI
147 * Control register. The MAC will take care of interfacing with the
148 * PHY to retrieve the desired data.
149 */
150 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
151 (phy->addr << E1000_MDIC_PHY_SHIFT) |
152 (E1000_MDIC_OP_READ));
153
154 ew32(MDIC, mdic);
155
156 /* Poll the ready bit to see if the MDI read completed
157 * Increasing the time out as testing showed failures with
158 * the lower time out
159 */
160 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
161 udelay(50);
162 mdic = er32(MDIC);
163 if (mdic & E1000_MDIC_READY)
164 break;
165 }
166 if (!(mdic & E1000_MDIC_READY)) {
167 e_dbg("MDI Read did not complete\n");
168 return -E1000_ERR_PHY;
169 }
170 if (mdic & E1000_MDIC_ERROR) {
171 e_dbg("MDI Error\n");
172 return -E1000_ERR_PHY;
173 }
174 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
175 e_dbg("MDI Read offset error - requested %d, returned %d\n",
176 offset,
177 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
178 return -E1000_ERR_PHY;
179 }
180 *data = (u16)mdic;
181
182 /* Allow some time after each MDIC transaction to avoid
183 * reading duplicate data in the next MDIC transaction.
184 */
185 if (hw->mac.type == e1000_pch2lan)
186 udelay(100);
187
188 return 0;
189 }
190
191 /**
192 * e1000e_write_phy_reg_mdic - Write MDI control register
193 * @hw: pointer to the HW structure
194 * @offset: register offset to write to
195 * @data: data to write to register at offset
196 *
197 * Writes data to MDI control register in the PHY at offset.
198 **/
e1000e_write_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 data)199 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
200 {
201 struct e1000_phy_info *phy = &hw->phy;
202 u32 i, mdic = 0;
203
204 if (offset > MAX_PHY_REG_ADDRESS) {
205 e_dbg("PHY Address %d is out of range\n", offset);
206 return -E1000_ERR_PARAM;
207 }
208
209 /* Set up Op-code, Phy Address, and register offset in the MDI
210 * Control register. The MAC will take care of interfacing with the
211 * PHY to retrieve the desired data.
212 */
213 mdic = (((u32)data) |
214 (offset << E1000_MDIC_REG_SHIFT) |
215 (phy->addr << E1000_MDIC_PHY_SHIFT) |
216 (E1000_MDIC_OP_WRITE));
217
218 ew32(MDIC, mdic);
219
220 /* Poll the ready bit to see if the MDI read completed
221 * Increasing the time out as testing showed failures with
222 * the lower time out
223 */
224 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
225 udelay(50);
226 mdic = er32(MDIC);
227 if (mdic & E1000_MDIC_READY)
228 break;
229 }
230 if (!(mdic & E1000_MDIC_READY)) {
231 e_dbg("MDI Write did not complete\n");
232 return -E1000_ERR_PHY;
233 }
234 if (mdic & E1000_MDIC_ERROR) {
235 e_dbg("MDI Error\n");
236 return -E1000_ERR_PHY;
237 }
238 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
239 e_dbg("MDI Write offset error - requested %d, returned %d\n",
240 offset,
241 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
242 return -E1000_ERR_PHY;
243 }
244
245 /* Allow some time after each MDIC transaction to avoid
246 * reading duplicate data in the next MDIC transaction.
247 */
248 if (hw->mac.type == e1000_pch2lan)
249 udelay(100);
250
251 return 0;
252 }
253
254 /**
255 * e1000e_read_phy_reg_m88 - Read m88 PHY register
256 * @hw: pointer to the HW structure
257 * @offset: register offset to be read
258 * @data: pointer to the read data
259 *
260 * Acquires semaphore, if necessary, then reads the PHY register at offset
261 * and storing the retrieved information in data. Release any acquired
262 * semaphores before exiting.
263 **/
e1000e_read_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 * data)264 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
265 {
266 s32 ret_val;
267
268 ret_val = hw->phy.ops.acquire(hw);
269 if (ret_val)
270 return ret_val;
271
272 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
273 data);
274
275 hw->phy.ops.release(hw);
276
277 return ret_val;
278 }
279
280 /**
281 * e1000e_write_phy_reg_m88 - Write m88 PHY register
282 * @hw: pointer to the HW structure
283 * @offset: register offset to write to
284 * @data: data to write at register offset
285 *
286 * Acquires semaphore, if necessary, then writes the data to PHY register
287 * at the offset. Release any acquired semaphores before exiting.
288 **/
e1000e_write_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 data)289 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
290 {
291 s32 ret_val;
292
293 ret_val = hw->phy.ops.acquire(hw);
294 if (ret_val)
295 return ret_val;
296
297 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
298 data);
299
300 hw->phy.ops.release(hw);
301
302 return ret_val;
303 }
304
305 /**
306 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
307 * @hw: pointer to the HW structure
308 * @page: page to set (shifted left when necessary)
309 *
310 * Sets PHY page required for PHY register access. Assumes semaphore is
311 * already acquired. Note, this function sets phy.addr to 1 so the caller
312 * must set it appropriately (if necessary) after this function returns.
313 **/
e1000_set_page_igp(struct e1000_hw * hw,u16 page)314 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
315 {
316 e_dbg("Setting page 0x%x\n", page);
317
318 hw->phy.addr = 1;
319
320 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
321 }
322
323 /**
324 * __e1000e_read_phy_reg_igp - Read igp PHY register
325 * @hw: pointer to the HW structure
326 * @offset: register offset to be read
327 * @data: pointer to the read data
328 * @locked: semaphore has already been acquired or not
329 *
330 * Acquires semaphore, if necessary, then reads the PHY register at offset
331 * and stores the retrieved information in data. Release any acquired
332 * semaphores before exiting.
333 **/
__e1000e_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)334 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
335 bool locked)
336 {
337 s32 ret_val = 0;
338
339 if (!locked) {
340 if (!hw->phy.ops.acquire)
341 return 0;
342
343 ret_val = hw->phy.ops.acquire(hw);
344 if (ret_val)
345 return ret_val;
346 }
347
348 if (offset > MAX_PHY_MULTI_PAGE_REG)
349 ret_val = e1000e_write_phy_reg_mdic(hw,
350 IGP01E1000_PHY_PAGE_SELECT,
351 (u16)offset);
352 if (!ret_val)
353 ret_val = e1000e_read_phy_reg_mdic(hw,
354 MAX_PHY_REG_ADDRESS & offset,
355 data);
356 if (!locked)
357 hw->phy.ops.release(hw);
358
359 return ret_val;
360 }
361
362 /**
363 * e1000e_read_phy_reg_igp - Read igp PHY register
364 * @hw: pointer to the HW structure
365 * @offset: register offset to be read
366 * @data: pointer to the read data
367 *
368 * Acquires semaphore then reads the PHY register at offset and stores the
369 * retrieved information in data.
370 * Release the acquired semaphore before exiting.
371 **/
e1000e_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data)372 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
373 {
374 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
375 }
376
377 /**
378 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
379 * @hw: pointer to the HW structure
380 * @offset: register offset to be read
381 * @data: pointer to the read data
382 *
383 * Reads the PHY register at offset and stores the retrieved information
384 * in data. Assumes semaphore already acquired.
385 **/
e1000e_read_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 * data)386 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
387 {
388 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
389 }
390
391 /**
392 * e1000e_write_phy_reg_igp - Write igp PHY register
393 * @hw: pointer to the HW structure
394 * @offset: register offset to write to
395 * @data: data to write at register offset
396 * @locked: semaphore has already been acquired or not
397 *
398 * Acquires semaphore, if necessary, then writes the data to PHY register
399 * at the offset. Release any acquired semaphores before exiting.
400 **/
__e1000e_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data,bool locked)401 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
402 bool locked)
403 {
404 s32 ret_val = 0;
405
406 if (!locked) {
407 if (!hw->phy.ops.acquire)
408 return 0;
409
410 ret_val = hw->phy.ops.acquire(hw);
411 if (ret_val)
412 return ret_val;
413 }
414
415 if (offset > MAX_PHY_MULTI_PAGE_REG)
416 ret_val = e1000e_write_phy_reg_mdic(hw,
417 IGP01E1000_PHY_PAGE_SELECT,
418 (u16)offset);
419 if (!ret_val)
420 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
421 offset, data);
422 if (!locked)
423 hw->phy.ops.release(hw);
424
425 return ret_val;
426 }
427
428 /**
429 * e1000e_write_phy_reg_igp - Write igp PHY register
430 * @hw: pointer to the HW structure
431 * @offset: register offset to write to
432 * @data: data to write at register offset
433 *
434 * Acquires semaphore then writes the data to PHY register
435 * at the offset. Release any acquired semaphores before exiting.
436 **/
e1000e_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data)437 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
438 {
439 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
440 }
441
442 /**
443 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
444 * @hw: pointer to the HW structure
445 * @offset: register offset to write to
446 * @data: data to write at register offset
447 *
448 * Writes the data to PHY register at the offset.
449 * Assumes semaphore already acquired.
450 **/
e1000e_write_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 data)451 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
452 {
453 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
454 }
455
456 /**
457 * __e1000_read_kmrn_reg - Read kumeran register
458 * @hw: pointer to the HW structure
459 * @offset: register offset to be read
460 * @data: pointer to the read data
461 * @locked: semaphore has already been acquired or not
462 *
463 * Acquires semaphore, if necessary. Then reads the PHY register at offset
464 * using the kumeran interface. The information retrieved is stored in data.
465 * Release any acquired semaphores before exiting.
466 **/
__e1000_read_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)467 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
468 bool locked)
469 {
470 u32 kmrnctrlsta;
471
472 if (!locked) {
473 s32 ret_val = 0;
474
475 if (!hw->phy.ops.acquire)
476 return 0;
477
478 ret_val = hw->phy.ops.acquire(hw);
479 if (ret_val)
480 return ret_val;
481 }
482
483 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
484 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
485 ew32(KMRNCTRLSTA, kmrnctrlsta);
486 e1e_flush();
487
488 udelay(2);
489
490 kmrnctrlsta = er32(KMRNCTRLSTA);
491 *data = (u16)kmrnctrlsta;
492
493 if (!locked)
494 hw->phy.ops.release(hw);
495
496 return 0;
497 }
498
499 /**
500 * e1000e_read_kmrn_reg - Read kumeran register
501 * @hw: pointer to the HW structure
502 * @offset: register offset to be read
503 * @data: pointer to the read data
504 *
505 * Acquires semaphore then reads the PHY register at offset using the
506 * kumeran interface. The information retrieved is stored in data.
507 * Release the acquired semaphore before exiting.
508 **/
e1000e_read_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 * data)509 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
510 {
511 return __e1000_read_kmrn_reg(hw, offset, data, false);
512 }
513
514 /**
515 * e1000e_read_kmrn_reg_locked - Read kumeran register
516 * @hw: pointer to the HW structure
517 * @offset: register offset to be read
518 * @data: pointer to the read data
519 *
520 * Reads the PHY register at offset using the kumeran interface. The
521 * information retrieved is stored in data.
522 * Assumes semaphore already acquired.
523 **/
e1000e_read_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 * data)524 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
525 {
526 return __e1000_read_kmrn_reg(hw, offset, data, true);
527 }
528
529 /**
530 * __e1000_write_kmrn_reg - Write kumeran register
531 * @hw: pointer to the HW structure
532 * @offset: register offset to write to
533 * @data: data to write at register offset
534 * @locked: semaphore has already been acquired or not
535 *
536 * Acquires semaphore, if necessary. Then write the data to PHY register
537 * at the offset using the kumeran interface. Release any acquired semaphores
538 * before exiting.
539 **/
__e1000_write_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 data,bool locked)540 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
541 bool locked)
542 {
543 u32 kmrnctrlsta;
544
545 if (!locked) {
546 s32 ret_val = 0;
547
548 if (!hw->phy.ops.acquire)
549 return 0;
550
551 ret_val = hw->phy.ops.acquire(hw);
552 if (ret_val)
553 return ret_val;
554 }
555
556 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
557 E1000_KMRNCTRLSTA_OFFSET) | data;
558 ew32(KMRNCTRLSTA, kmrnctrlsta);
559 e1e_flush();
560
561 udelay(2);
562
563 if (!locked)
564 hw->phy.ops.release(hw);
565
566 return 0;
567 }
568
569 /**
570 * e1000e_write_kmrn_reg - Write kumeran register
571 * @hw: pointer to the HW structure
572 * @offset: register offset to write to
573 * @data: data to write at register offset
574 *
575 * Acquires semaphore then writes the data to the PHY register at the offset
576 * using the kumeran interface. Release the acquired semaphore before exiting.
577 **/
e1000e_write_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 data)578 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
579 {
580 return __e1000_write_kmrn_reg(hw, offset, data, false);
581 }
582
583 /**
584 * e1000e_write_kmrn_reg_locked - Write kumeran register
585 * @hw: pointer to the HW structure
586 * @offset: register offset to write to
587 * @data: data to write at register offset
588 *
589 * Write the data to PHY register at the offset using the kumeran interface.
590 * Assumes semaphore already acquired.
591 **/
e1000e_write_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 data)592 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
593 {
594 return __e1000_write_kmrn_reg(hw, offset, data, true);
595 }
596
597 /**
598 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
599 * @hw: pointer to the HW structure
600 *
601 * Sets up Master/slave mode
602 **/
e1000_set_master_slave_mode(struct e1000_hw * hw)603 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
604 {
605 s32 ret_val;
606 u16 phy_data;
607
608 /* Resolve Master/Slave mode */
609 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data);
610 if (ret_val)
611 return ret_val;
612
613 /* load defaults for future use */
614 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ?
615 ((phy_data & CTL1000_AS_MASTER) ?
616 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
617
618 switch (hw->phy.ms_type) {
619 case e1000_ms_force_master:
620 phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
621 break;
622 case e1000_ms_force_slave:
623 phy_data |= CTL1000_ENABLE_MASTER;
624 phy_data &= ~(CTL1000_AS_MASTER);
625 break;
626 case e1000_ms_auto:
627 phy_data &= ~CTL1000_ENABLE_MASTER;
628 /* fall-through */
629 default:
630 break;
631 }
632
633 return e1e_wphy(hw, MII_CTRL1000, phy_data);
634 }
635
636 /**
637 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
638 * @hw: pointer to the HW structure
639 *
640 * Sets up Carrier-sense on Transmit and downshift values.
641 **/
e1000_copper_link_setup_82577(struct e1000_hw * hw)642 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
643 {
644 s32 ret_val;
645 u16 phy_data;
646
647 /* Enable CRS on Tx. This must be set for half-duplex operation. */
648 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
649 if (ret_val)
650 return ret_val;
651
652 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
653
654 /* Enable downshift */
655 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
656
657 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
658 if (ret_val)
659 return ret_val;
660
661 /* Set MDI/MDIX mode */
662 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
663 if (ret_val)
664 return ret_val;
665 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
666 /* Options:
667 * 0 - Auto (default)
668 * 1 - MDI mode
669 * 2 - MDI-X mode
670 */
671 switch (hw->phy.mdix) {
672 case 1:
673 break;
674 case 2:
675 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
676 break;
677 case 0:
678 default:
679 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
680 break;
681 }
682 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
683 if (ret_val)
684 return ret_val;
685
686 return e1000_set_master_slave_mode(hw);
687 }
688
689 /**
690 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
691 * @hw: pointer to the HW structure
692 *
693 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
694 * and downshift values are set also.
695 **/
e1000e_copper_link_setup_m88(struct e1000_hw * hw)696 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
697 {
698 struct e1000_phy_info *phy = &hw->phy;
699 s32 ret_val;
700 u16 phy_data;
701
702 /* Enable CRS on Tx. This must be set for half-duplex operation. */
703 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
704 if (ret_val)
705 return ret_val;
706
707 /* For BM PHY this bit is downshift enable */
708 if (phy->type != e1000_phy_bm)
709 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
710
711 /* Options:
712 * MDI/MDI-X = 0 (default)
713 * 0 - Auto for all speeds
714 * 1 - MDI mode
715 * 2 - MDI-X mode
716 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
717 */
718 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
719
720 switch (phy->mdix) {
721 case 1:
722 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
723 break;
724 case 2:
725 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
726 break;
727 case 3:
728 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
729 break;
730 case 0:
731 default:
732 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
733 break;
734 }
735
736 /* Options:
737 * disable_polarity_correction = 0 (default)
738 * Automatic Correction for Reversed Cable Polarity
739 * 0 - Disabled
740 * 1 - Enabled
741 */
742 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
743 if (phy->disable_polarity_correction)
744 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
745
746 /* Enable downshift on BM (disabled by default) */
747 if (phy->type == e1000_phy_bm) {
748 /* For 82574/82583, first disable then enable downshift */
749 if (phy->id == BME1000_E_PHY_ID_R2) {
750 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
751 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
752 phy_data);
753 if (ret_val)
754 return ret_val;
755 /* Commit the changes. */
756 ret_val = phy->ops.commit(hw);
757 if (ret_val) {
758 e_dbg("Error committing the PHY changes\n");
759 return ret_val;
760 }
761 }
762
763 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
764 }
765
766 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
767 if (ret_val)
768 return ret_val;
769
770 if ((phy->type == e1000_phy_m88) &&
771 (phy->revision < E1000_REVISION_4) &&
772 (phy->id != BME1000_E_PHY_ID_R2)) {
773 /* Force TX_CLK in the Extended PHY Specific Control Register
774 * to 25MHz clock.
775 */
776 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
777 if (ret_val)
778 return ret_val;
779
780 phy_data |= M88E1000_EPSCR_TX_CLK_25;
781
782 if ((phy->revision == 2) && (phy->id == M88E1111_I_PHY_ID)) {
783 /* 82573L PHY - set the downshift counter to 5x. */
784 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
785 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
786 } else {
787 /* Configure Master and Slave downshift values */
788 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
789 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
790 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
791 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
792 }
793 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
794 if (ret_val)
795 return ret_val;
796 }
797
798 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
799 /* Set PHY page 0, register 29 to 0x0003 */
800 ret_val = e1e_wphy(hw, 29, 0x0003);
801 if (ret_val)
802 return ret_val;
803
804 /* Set PHY page 0, register 30 to 0x0000 */
805 ret_val = e1e_wphy(hw, 30, 0x0000);
806 if (ret_val)
807 return ret_val;
808 }
809
810 /* Commit the changes. */
811 if (phy->ops.commit) {
812 ret_val = phy->ops.commit(hw);
813 if (ret_val) {
814 e_dbg("Error committing the PHY changes\n");
815 return ret_val;
816 }
817 }
818
819 if (phy->type == e1000_phy_82578) {
820 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
821 if (ret_val)
822 return ret_val;
823
824 /* 82578 PHY - set the downshift count to 1x. */
825 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
826 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
827 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
828 if (ret_val)
829 return ret_val;
830 }
831
832 return 0;
833 }
834
835 /**
836 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
837 * @hw: pointer to the HW structure
838 *
839 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
840 * igp PHY's.
841 **/
e1000e_copper_link_setup_igp(struct e1000_hw * hw)842 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
843 {
844 struct e1000_phy_info *phy = &hw->phy;
845 s32 ret_val;
846 u16 data;
847
848 ret_val = e1000_phy_hw_reset(hw);
849 if (ret_val) {
850 e_dbg("Error resetting the PHY.\n");
851 return ret_val;
852 }
853
854 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
855 * timeout issues when LFS is enabled.
856 */
857 msleep(100);
858
859 /* disable lplu d0 during driver init */
860 if (hw->phy.ops.set_d0_lplu_state) {
861 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
862 if (ret_val) {
863 e_dbg("Error Disabling LPLU D0\n");
864 return ret_val;
865 }
866 }
867 /* Configure mdi-mdix settings */
868 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
869 if (ret_val)
870 return ret_val;
871
872 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
873
874 switch (phy->mdix) {
875 case 1:
876 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
877 break;
878 case 2:
879 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
880 break;
881 case 0:
882 default:
883 data |= IGP01E1000_PSCR_AUTO_MDIX;
884 break;
885 }
886 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
887 if (ret_val)
888 return ret_val;
889
890 /* set auto-master slave resolution settings */
891 if (hw->mac.autoneg) {
892 /* when autonegotiation advertisement is only 1000Mbps then we
893 * should disable SmartSpeed and enable Auto MasterSlave
894 * resolution as hardware default.
895 */
896 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
897 /* Disable SmartSpeed */
898 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
899 &data);
900 if (ret_val)
901 return ret_val;
902
903 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
904 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
905 data);
906 if (ret_val)
907 return ret_val;
908
909 /* Set auto Master/Slave resolution process */
910 ret_val = e1e_rphy(hw, MII_CTRL1000, &data);
911 if (ret_val)
912 return ret_val;
913
914 data &= ~CTL1000_ENABLE_MASTER;
915 ret_val = e1e_wphy(hw, MII_CTRL1000, data);
916 if (ret_val)
917 return ret_val;
918 }
919
920 ret_val = e1000_set_master_slave_mode(hw);
921 }
922
923 return ret_val;
924 }
925
926 /**
927 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
928 * @hw: pointer to the HW structure
929 *
930 * Reads the MII auto-neg advertisement register and/or the 1000T control
931 * register and if the PHY is already setup for auto-negotiation, then
932 * return successful. Otherwise, setup advertisement and flow control to
933 * the appropriate values for the wanted auto-negotiation.
934 **/
e1000_phy_setup_autoneg(struct e1000_hw * hw)935 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
936 {
937 struct e1000_phy_info *phy = &hw->phy;
938 s32 ret_val;
939 u16 mii_autoneg_adv_reg;
940 u16 mii_1000t_ctrl_reg = 0;
941
942 phy->autoneg_advertised &= phy->autoneg_mask;
943
944 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
945 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg);
946 if (ret_val)
947 return ret_val;
948
949 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
950 /* Read the MII 1000Base-T Control Register (Address 9). */
951 ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg);
952 if (ret_val)
953 return ret_val;
954 }
955
956 /* Need to parse both autoneg_advertised and fc and set up
957 * the appropriate PHY registers. First we will parse for
958 * autoneg_advertised software override. Since we can advertise
959 * a plethora of combinations, we need to check each bit
960 * individually.
961 */
962
963 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
964 * Advertisement Register (Address 4) and the 1000 mb speed bits in
965 * the 1000Base-T Control Register (Address 9).
966 */
967 mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL |
968 ADVERTISE_100HALF |
969 ADVERTISE_10FULL | ADVERTISE_10HALF);
970 mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
971
972 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
973
974 /* Do we want to advertise 10 Mb Half Duplex? */
975 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
976 e_dbg("Advertise 10mb Half duplex\n");
977 mii_autoneg_adv_reg |= ADVERTISE_10HALF;
978 }
979
980 /* Do we want to advertise 10 Mb Full Duplex? */
981 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
982 e_dbg("Advertise 10mb Full duplex\n");
983 mii_autoneg_adv_reg |= ADVERTISE_10FULL;
984 }
985
986 /* Do we want to advertise 100 Mb Half Duplex? */
987 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
988 e_dbg("Advertise 100mb Half duplex\n");
989 mii_autoneg_adv_reg |= ADVERTISE_100HALF;
990 }
991
992 /* Do we want to advertise 100 Mb Full Duplex? */
993 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
994 e_dbg("Advertise 100mb Full duplex\n");
995 mii_autoneg_adv_reg |= ADVERTISE_100FULL;
996 }
997
998 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
999 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1000 e_dbg("Advertise 1000mb Half duplex request denied!\n");
1001
1002 /* Do we want to advertise 1000 Mb Full Duplex? */
1003 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1004 e_dbg("Advertise 1000mb Full duplex\n");
1005 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
1006 }
1007
1008 /* Check for a software override of the flow control settings, and
1009 * setup the PHY advertisement registers accordingly. If
1010 * auto-negotiation is enabled, then software will have to set the
1011 * "PAUSE" bits to the correct value in the Auto-Negotiation
1012 * Advertisement Register (MII_ADVERTISE) and re-start auto-
1013 * negotiation.
1014 *
1015 * The possible values of the "fc" parameter are:
1016 * 0: Flow control is completely disabled
1017 * 1: Rx flow control is enabled (we can receive pause frames
1018 * but not send pause frames).
1019 * 2: Tx flow control is enabled (we can send pause frames
1020 * but we do not support receiving pause frames).
1021 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1022 * other: No software override. The flow control configuration
1023 * in the EEPROM is used.
1024 */
1025 switch (hw->fc.current_mode) {
1026 case e1000_fc_none:
1027 /* Flow control (Rx & Tx) is completely disabled by a
1028 * software over-ride.
1029 */
1030 mii_autoneg_adv_reg &=
1031 ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1032 break;
1033 case e1000_fc_rx_pause:
1034 /* Rx Flow control is enabled, and Tx Flow control is
1035 * disabled, by a software over-ride.
1036 *
1037 * Since there really isn't a way to advertise that we are
1038 * capable of Rx Pause ONLY, we will advertise that we
1039 * support both symmetric and asymmetric Rx PAUSE. Later
1040 * (in e1000e_config_fc_after_link_up) we will disable the
1041 * hw's ability to send PAUSE frames.
1042 */
1043 mii_autoneg_adv_reg |=
1044 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1045 break;
1046 case e1000_fc_tx_pause:
1047 /* Tx Flow control is enabled, and Rx Flow control is
1048 * disabled, by a software over-ride.
1049 */
1050 mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM;
1051 mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP;
1052 break;
1053 case e1000_fc_full:
1054 /* Flow control (both Rx and Tx) is enabled by a software
1055 * over-ride.
1056 */
1057 mii_autoneg_adv_reg |=
1058 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1059 break;
1060 default:
1061 e_dbg("Flow control param set incorrectly\n");
1062 return -E1000_ERR_CONFIG;
1063 }
1064
1065 ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
1066 if (ret_val)
1067 return ret_val;
1068
1069 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1070
1071 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1072 ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg);
1073
1074 return ret_val;
1075 }
1076
1077 /**
1078 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1079 * @hw: pointer to the HW structure
1080 *
1081 * Performs initial bounds checking on autoneg advertisement parameter, then
1082 * configure to advertise the full capability. Setup the PHY to autoneg
1083 * and restart the negotiation process between the link partner. If
1084 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1085 **/
e1000_copper_link_autoneg(struct e1000_hw * hw)1086 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1087 {
1088 struct e1000_phy_info *phy = &hw->phy;
1089 s32 ret_val;
1090 u16 phy_ctrl;
1091
1092 /* Perform some bounds checking on the autoneg advertisement
1093 * parameter.
1094 */
1095 phy->autoneg_advertised &= phy->autoneg_mask;
1096
1097 /* If autoneg_advertised is zero, we assume it was not defaulted
1098 * by the calling code so we set to advertise full capability.
1099 */
1100 if (!phy->autoneg_advertised)
1101 phy->autoneg_advertised = phy->autoneg_mask;
1102
1103 e_dbg("Reconfiguring auto-neg advertisement params\n");
1104 ret_val = e1000_phy_setup_autoneg(hw);
1105 if (ret_val) {
1106 e_dbg("Error Setting up Auto-Negotiation\n");
1107 return ret_val;
1108 }
1109 e_dbg("Restarting Auto-Neg\n");
1110
1111 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1112 * the Auto Neg Restart bit in the PHY control register.
1113 */
1114 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
1115 if (ret_val)
1116 return ret_val;
1117
1118 phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
1119 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
1120 if (ret_val)
1121 return ret_val;
1122
1123 /* Does the user want to wait for Auto-Neg to complete here, or
1124 * check at a later time (for example, callback routine).
1125 */
1126 if (phy->autoneg_wait_to_complete) {
1127 ret_val = e1000_wait_autoneg(hw);
1128 if (ret_val) {
1129 e_dbg("Error while waiting for autoneg to complete\n");
1130 return ret_val;
1131 }
1132 }
1133
1134 hw->mac.get_link_status = true;
1135
1136 return ret_val;
1137 }
1138
1139 /**
1140 * e1000e_setup_copper_link - Configure copper link settings
1141 * @hw: pointer to the HW structure
1142 *
1143 * Calls the appropriate function to configure the link for auto-neg or forced
1144 * speed and duplex. Then we check for link, once link is established calls
1145 * to configure collision distance and flow control are called. If link is
1146 * not established, we return -E1000_ERR_PHY (-2).
1147 **/
e1000e_setup_copper_link(struct e1000_hw * hw)1148 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1149 {
1150 s32 ret_val;
1151 bool link;
1152
1153 if (hw->mac.autoneg) {
1154 /* Setup autoneg and flow control advertisement and perform
1155 * autonegotiation.
1156 */
1157 ret_val = e1000_copper_link_autoneg(hw);
1158 if (ret_val)
1159 return ret_val;
1160 } else {
1161 /* PHY will be set to 10H, 10F, 100H or 100F
1162 * depending on user settings.
1163 */
1164 e_dbg("Forcing Speed and Duplex\n");
1165 ret_val = hw->phy.ops.force_speed_duplex(hw);
1166 if (ret_val) {
1167 e_dbg("Error Forcing Speed and Duplex\n");
1168 return ret_val;
1169 }
1170 }
1171
1172 /* Check link status. Wait up to 100 microseconds for link to become
1173 * valid.
1174 */
1175 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1176 &link);
1177 if (ret_val)
1178 return ret_val;
1179
1180 if (link) {
1181 e_dbg("Valid link established!!!\n");
1182 hw->mac.ops.config_collision_dist(hw);
1183 ret_val = e1000e_config_fc_after_link_up(hw);
1184 } else {
1185 e_dbg("Unable to establish link!!!\n");
1186 }
1187
1188 return ret_val;
1189 }
1190
1191 /**
1192 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1193 * @hw: pointer to the HW structure
1194 *
1195 * Calls the PHY setup function to force speed and duplex. Clears the
1196 * auto-crossover to force MDI manually. Waits for link and returns
1197 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1198 **/
e1000e_phy_force_speed_duplex_igp(struct e1000_hw * hw)1199 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1200 {
1201 struct e1000_phy_info *phy = &hw->phy;
1202 s32 ret_val;
1203 u16 phy_data;
1204 bool link;
1205
1206 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1207 if (ret_val)
1208 return ret_val;
1209
1210 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1211
1212 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1213 if (ret_val)
1214 return ret_val;
1215
1216 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1217 * forced whenever speed and duplex are forced.
1218 */
1219 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1220 if (ret_val)
1221 return ret_val;
1222
1223 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1224 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1225
1226 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1227 if (ret_val)
1228 return ret_val;
1229
1230 e_dbg("IGP PSCR: %X\n", phy_data);
1231
1232 udelay(1);
1233
1234 if (phy->autoneg_wait_to_complete) {
1235 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1236
1237 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1238 100000, &link);
1239 if (ret_val)
1240 return ret_val;
1241
1242 if (!link)
1243 e_dbg("Link taking longer than expected.\n");
1244
1245 /* Try once more */
1246 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1247 100000, &link);
1248 }
1249
1250 return ret_val;
1251 }
1252
1253 /**
1254 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1255 * @hw: pointer to the HW structure
1256 *
1257 * Calls the PHY setup function to force speed and duplex. Clears the
1258 * auto-crossover to force MDI manually. Resets the PHY to commit the
1259 * changes. If time expires while waiting for link up, we reset the DSP.
1260 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1261 * successful completion, else return corresponding error code.
1262 **/
e1000e_phy_force_speed_duplex_m88(struct e1000_hw * hw)1263 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1264 {
1265 struct e1000_phy_info *phy = &hw->phy;
1266 s32 ret_val;
1267 u16 phy_data;
1268 bool link;
1269
1270 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1271 * forced whenever speed and duplex are forced.
1272 */
1273 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1274 if (ret_val)
1275 return ret_val;
1276
1277 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1278 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1279 if (ret_val)
1280 return ret_val;
1281
1282 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1283
1284 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1285 if (ret_val)
1286 return ret_val;
1287
1288 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1289
1290 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1291 if (ret_val)
1292 return ret_val;
1293
1294 /* Reset the phy to commit changes. */
1295 if (hw->phy.ops.commit) {
1296 ret_val = hw->phy.ops.commit(hw);
1297 if (ret_val)
1298 return ret_val;
1299 }
1300
1301 if (phy->autoneg_wait_to_complete) {
1302 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1303
1304 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1305 100000, &link);
1306 if (ret_val)
1307 return ret_val;
1308
1309 if (!link) {
1310 if (hw->phy.type != e1000_phy_m88) {
1311 e_dbg("Link taking longer than expected.\n");
1312 } else {
1313 /* We didn't get link.
1314 * Reset the DSP and cross our fingers.
1315 */
1316 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1317 0x001d);
1318 if (ret_val)
1319 return ret_val;
1320 ret_val = e1000e_phy_reset_dsp(hw);
1321 if (ret_val)
1322 return ret_val;
1323 }
1324 }
1325
1326 /* Try once more */
1327 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1328 100000, &link);
1329 if (ret_val)
1330 return ret_val;
1331 }
1332
1333 if (hw->phy.type != e1000_phy_m88)
1334 return 0;
1335
1336 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1337 if (ret_val)
1338 return ret_val;
1339
1340 /* Resetting the phy means we need to re-force TX_CLK in the
1341 * Extended PHY Specific Control Register to 25MHz clock from
1342 * the reset value of 2.5MHz.
1343 */
1344 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1345 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1346 if (ret_val)
1347 return ret_val;
1348
1349 /* In addition, we must re-enable CRS on Tx for both half and full
1350 * duplex.
1351 */
1352 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1353 if (ret_val)
1354 return ret_val;
1355
1356 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1357 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1358
1359 return ret_val;
1360 }
1361
1362 /**
1363 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1364 * @hw: pointer to the HW structure
1365 *
1366 * Forces the speed and duplex settings of the PHY.
1367 * This is a function pointer entry point only called by
1368 * PHY setup routines.
1369 **/
e1000_phy_force_speed_duplex_ife(struct e1000_hw * hw)1370 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1371 {
1372 struct e1000_phy_info *phy = &hw->phy;
1373 s32 ret_val;
1374 u16 data;
1375 bool link;
1376
1377 ret_val = e1e_rphy(hw, MII_BMCR, &data);
1378 if (ret_val)
1379 return ret_val;
1380
1381 e1000e_phy_force_speed_duplex_setup(hw, &data);
1382
1383 ret_val = e1e_wphy(hw, MII_BMCR, data);
1384 if (ret_val)
1385 return ret_val;
1386
1387 /* Disable MDI-X support for 10/100 */
1388 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1389 if (ret_val)
1390 return ret_val;
1391
1392 data &= ~IFE_PMC_AUTO_MDIX;
1393 data &= ~IFE_PMC_FORCE_MDIX;
1394
1395 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1396 if (ret_val)
1397 return ret_val;
1398
1399 e_dbg("IFE PMC: %X\n", data);
1400
1401 udelay(1);
1402
1403 if (phy->autoneg_wait_to_complete) {
1404 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1405
1406 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1407 100000, &link);
1408 if (ret_val)
1409 return ret_val;
1410
1411 if (!link)
1412 e_dbg("Link taking longer than expected.\n");
1413
1414 /* Try once more */
1415 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1416 100000, &link);
1417 if (ret_val)
1418 return ret_val;
1419 }
1420
1421 return 0;
1422 }
1423
1424 /**
1425 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1426 * @hw: pointer to the HW structure
1427 * @phy_ctrl: pointer to current value of MII_BMCR
1428 *
1429 * Forces speed and duplex on the PHY by doing the following: disable flow
1430 * control, force speed/duplex on the MAC, disable auto speed detection,
1431 * disable auto-negotiation, configure duplex, configure speed, configure
1432 * the collision distance, write configuration to CTRL register. The
1433 * caller must write to the MII_BMCR register for these settings to
1434 * take affect.
1435 **/
e1000e_phy_force_speed_duplex_setup(struct e1000_hw * hw,u16 * phy_ctrl)1436 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1437 {
1438 struct e1000_mac_info *mac = &hw->mac;
1439 u32 ctrl;
1440
1441 /* Turn off flow control when forcing speed/duplex */
1442 hw->fc.current_mode = e1000_fc_none;
1443
1444 /* Force speed/duplex on the mac */
1445 ctrl = er32(CTRL);
1446 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1447 ctrl &= ~E1000_CTRL_SPD_SEL;
1448
1449 /* Disable Auto Speed Detection */
1450 ctrl &= ~E1000_CTRL_ASDE;
1451
1452 /* Disable autoneg on the phy */
1453 *phy_ctrl &= ~BMCR_ANENABLE;
1454
1455 /* Forcing Full or Half Duplex? */
1456 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1457 ctrl &= ~E1000_CTRL_FD;
1458 *phy_ctrl &= ~BMCR_FULLDPLX;
1459 e_dbg("Half Duplex\n");
1460 } else {
1461 ctrl |= E1000_CTRL_FD;
1462 *phy_ctrl |= BMCR_FULLDPLX;
1463 e_dbg("Full Duplex\n");
1464 }
1465
1466 /* Forcing 10mb or 100mb? */
1467 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1468 ctrl |= E1000_CTRL_SPD_100;
1469 *phy_ctrl |= BMCR_SPEED100;
1470 *phy_ctrl &= ~BMCR_SPEED1000;
1471 e_dbg("Forcing 100mb\n");
1472 } else {
1473 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1474 *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100);
1475 e_dbg("Forcing 10mb\n");
1476 }
1477
1478 hw->mac.ops.config_collision_dist(hw);
1479
1480 ew32(CTRL, ctrl);
1481 }
1482
1483 /**
1484 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1485 * @hw: pointer to the HW structure
1486 * @active: boolean used to enable/disable lplu
1487 *
1488 * Success returns 0, Failure returns 1
1489 *
1490 * The low power link up (lplu) state is set to the power management level D3
1491 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1492 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1493 * is used during Dx states where the power conservation is most important.
1494 * During driver activity, SmartSpeed should be enabled so performance is
1495 * maintained.
1496 **/
e1000e_set_d3_lplu_state(struct e1000_hw * hw,bool active)1497 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1498 {
1499 struct e1000_phy_info *phy = &hw->phy;
1500 s32 ret_val;
1501 u16 data;
1502
1503 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1504 if (ret_val)
1505 return ret_val;
1506
1507 if (!active) {
1508 data &= ~IGP02E1000_PM_D3_LPLU;
1509 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1510 if (ret_val)
1511 return ret_val;
1512 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1513 * during Dx states where the power conservation is most
1514 * important. During driver activity we should enable
1515 * SmartSpeed, so performance is maintained.
1516 */
1517 if (phy->smart_speed == e1000_smart_speed_on) {
1518 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1519 &data);
1520 if (ret_val)
1521 return ret_val;
1522
1523 data |= IGP01E1000_PSCFR_SMART_SPEED;
1524 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1525 data);
1526 if (ret_val)
1527 return ret_val;
1528 } else if (phy->smart_speed == e1000_smart_speed_off) {
1529 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1530 &data);
1531 if (ret_val)
1532 return ret_val;
1533
1534 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1535 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1536 data);
1537 if (ret_val)
1538 return ret_val;
1539 }
1540 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1541 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1542 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1543 data |= IGP02E1000_PM_D3_LPLU;
1544 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1545 if (ret_val)
1546 return ret_val;
1547
1548 /* When LPLU is enabled, we should disable SmartSpeed */
1549 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1550 if (ret_val)
1551 return ret_val;
1552
1553 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1554 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1555 }
1556
1557 return ret_val;
1558 }
1559
1560 /**
1561 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1562 * @hw: pointer to the HW structure
1563 *
1564 * Success returns 0, Failure returns 1
1565 *
1566 * A downshift is detected by querying the PHY link health.
1567 **/
e1000e_check_downshift(struct e1000_hw * hw)1568 s32 e1000e_check_downshift(struct e1000_hw *hw)
1569 {
1570 struct e1000_phy_info *phy = &hw->phy;
1571 s32 ret_val;
1572 u16 phy_data, offset, mask;
1573
1574 switch (phy->type) {
1575 case e1000_phy_m88:
1576 case e1000_phy_gg82563:
1577 case e1000_phy_bm:
1578 case e1000_phy_82578:
1579 offset = M88E1000_PHY_SPEC_STATUS;
1580 mask = M88E1000_PSSR_DOWNSHIFT;
1581 break;
1582 case e1000_phy_igp_2:
1583 case e1000_phy_igp_3:
1584 offset = IGP01E1000_PHY_LINK_HEALTH;
1585 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1586 break;
1587 default:
1588 /* speed downshift not supported */
1589 phy->speed_downgraded = false;
1590 return 0;
1591 }
1592
1593 ret_val = e1e_rphy(hw, offset, &phy_data);
1594
1595 if (!ret_val)
1596 phy->speed_downgraded = !!(phy_data & mask);
1597
1598 return ret_val;
1599 }
1600
1601 /**
1602 * e1000_check_polarity_m88 - Checks the polarity.
1603 * @hw: pointer to the HW structure
1604 *
1605 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1606 *
1607 * Polarity is determined based on the PHY specific status register.
1608 **/
e1000_check_polarity_m88(struct e1000_hw * hw)1609 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1610 {
1611 struct e1000_phy_info *phy = &hw->phy;
1612 s32 ret_val;
1613 u16 data;
1614
1615 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1616
1617 if (!ret_val)
1618 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
1619 ? e1000_rev_polarity_reversed
1620 : e1000_rev_polarity_normal);
1621
1622 return ret_val;
1623 }
1624
1625 /**
1626 * e1000_check_polarity_igp - Checks the polarity.
1627 * @hw: pointer to the HW structure
1628 *
1629 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1630 *
1631 * Polarity is determined based on the PHY port status register, and the
1632 * current speed (since there is no polarity at 100Mbps).
1633 **/
e1000_check_polarity_igp(struct e1000_hw * hw)1634 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1635 {
1636 struct e1000_phy_info *phy = &hw->phy;
1637 s32 ret_val;
1638 u16 data, offset, mask;
1639
1640 /* Polarity is determined based on the speed of
1641 * our connection.
1642 */
1643 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1644 if (ret_val)
1645 return ret_val;
1646
1647 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1648 IGP01E1000_PSSR_SPEED_1000MBPS) {
1649 offset = IGP01E1000_PHY_PCS_INIT_REG;
1650 mask = IGP01E1000_PHY_POLARITY_MASK;
1651 } else {
1652 /* This really only applies to 10Mbps since
1653 * there is no polarity for 100Mbps (always 0).
1654 */
1655 offset = IGP01E1000_PHY_PORT_STATUS;
1656 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1657 }
1658
1659 ret_val = e1e_rphy(hw, offset, &data);
1660
1661 if (!ret_val)
1662 phy->cable_polarity = ((data & mask)
1663 ? e1000_rev_polarity_reversed
1664 : e1000_rev_polarity_normal);
1665
1666 return ret_val;
1667 }
1668
1669 /**
1670 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1671 * @hw: pointer to the HW structure
1672 *
1673 * Polarity is determined on the polarity reversal feature being enabled.
1674 **/
e1000_check_polarity_ife(struct e1000_hw * hw)1675 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1676 {
1677 struct e1000_phy_info *phy = &hw->phy;
1678 s32 ret_val;
1679 u16 phy_data, offset, mask;
1680
1681 /* Polarity is determined based on the reversal feature being enabled.
1682 */
1683 if (phy->polarity_correction) {
1684 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1685 mask = IFE_PESC_POLARITY_REVERSED;
1686 } else {
1687 offset = IFE_PHY_SPECIAL_CONTROL;
1688 mask = IFE_PSC_FORCE_POLARITY;
1689 }
1690
1691 ret_val = e1e_rphy(hw, offset, &phy_data);
1692
1693 if (!ret_val)
1694 phy->cable_polarity = ((phy_data & mask)
1695 ? e1000_rev_polarity_reversed
1696 : e1000_rev_polarity_normal);
1697
1698 return ret_val;
1699 }
1700
1701 /**
1702 * e1000_wait_autoneg - Wait for auto-neg completion
1703 * @hw: pointer to the HW structure
1704 *
1705 * Waits for auto-negotiation to complete or for the auto-negotiation time
1706 * limit to expire, which ever happens first.
1707 **/
e1000_wait_autoneg(struct e1000_hw * hw)1708 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1709 {
1710 s32 ret_val = 0;
1711 u16 i, phy_status;
1712
1713 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1714 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1715 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1716 if (ret_val)
1717 break;
1718 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1719 if (ret_val)
1720 break;
1721 if (phy_status & BMSR_ANEGCOMPLETE)
1722 break;
1723 msleep(100);
1724 }
1725
1726 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1727 * has completed.
1728 */
1729 return ret_val;
1730 }
1731
1732 /**
1733 * e1000e_phy_has_link_generic - Polls PHY for link
1734 * @hw: pointer to the HW structure
1735 * @iterations: number of times to poll for link
1736 * @usec_interval: delay between polling attempts
1737 * @success: pointer to whether polling was successful or not
1738 *
1739 * Polls the PHY status register for link, 'iterations' number of times.
1740 **/
e1000e_phy_has_link_generic(struct e1000_hw * hw,u32 iterations,u32 usec_interval,bool * success)1741 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1742 u32 usec_interval, bool *success)
1743 {
1744 s32 ret_val = 0;
1745 u16 i, phy_status;
1746
1747 *success = false;
1748 for (i = 0; i < iterations; i++) {
1749 /* Some PHYs require the MII_BMSR register to be read
1750 * twice due to the link bit being sticky. No harm doing
1751 * it across the board.
1752 */
1753 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1754 if (ret_val) {
1755 /* If the first read fails, another entity may have
1756 * ownership of the resources, wait and try again to
1757 * see if they have relinquished the resources yet.
1758 */
1759 if (usec_interval >= 1000)
1760 msleep(usec_interval / 1000);
1761 else
1762 udelay(usec_interval);
1763 }
1764 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1765 if (ret_val)
1766 break;
1767 if (phy_status & BMSR_LSTATUS) {
1768 *success = true;
1769 break;
1770 }
1771 if (usec_interval >= 1000)
1772 msleep(usec_interval / 1000);
1773 else
1774 udelay(usec_interval);
1775 }
1776
1777 return ret_val;
1778 }
1779
1780 /**
1781 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1782 * @hw: pointer to the HW structure
1783 *
1784 * Reads the PHY specific status register to retrieve the cable length
1785 * information. The cable length is determined by averaging the minimum and
1786 * maximum values to get the "average" cable length. The m88 PHY has four
1787 * possible cable length values, which are:
1788 * Register Value Cable Length
1789 * 0 < 50 meters
1790 * 1 50 - 80 meters
1791 * 2 80 - 110 meters
1792 * 3 110 - 140 meters
1793 * 4 > 140 meters
1794 **/
e1000e_get_cable_length_m88(struct e1000_hw * hw)1795 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1796 {
1797 struct e1000_phy_info *phy = &hw->phy;
1798 s32 ret_val;
1799 u16 phy_data, index;
1800
1801 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1802 if (ret_val)
1803 return ret_val;
1804
1805 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1806 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
1807
1808 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1809 return -E1000_ERR_PHY;
1810
1811 phy->min_cable_length = e1000_m88_cable_length_table[index];
1812 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1813
1814 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1815
1816 return 0;
1817 }
1818
1819 /**
1820 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1821 * @hw: pointer to the HW structure
1822 *
1823 * The automatic gain control (agc) normalizes the amplitude of the
1824 * received signal, adjusting for the attenuation produced by the
1825 * cable. By reading the AGC registers, which represent the
1826 * combination of coarse and fine gain value, the value can be put
1827 * into a lookup table to obtain the approximate cable length
1828 * for each channel.
1829 **/
e1000e_get_cable_length_igp_2(struct e1000_hw * hw)1830 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1831 {
1832 struct e1000_phy_info *phy = &hw->phy;
1833 s32 ret_val;
1834 u16 phy_data, i, agc_value = 0;
1835 u16 cur_agc_index, max_agc_index = 0;
1836 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1837 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1838 IGP02E1000_PHY_AGC_A,
1839 IGP02E1000_PHY_AGC_B,
1840 IGP02E1000_PHY_AGC_C,
1841 IGP02E1000_PHY_AGC_D
1842 };
1843
1844 /* Read the AGC registers for all channels */
1845 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1846 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1847 if (ret_val)
1848 return ret_val;
1849
1850 /* Getting bits 15:9, which represent the combination of
1851 * coarse and fine gain values. The result is a number
1852 * that can be put into the lookup table to obtain the
1853 * approximate cable length.
1854 */
1855 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1856 IGP02E1000_AGC_LENGTH_MASK);
1857
1858 /* Array index bound check. */
1859 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1860 (cur_agc_index == 0))
1861 return -E1000_ERR_PHY;
1862
1863 /* Remove min & max AGC values from calculation. */
1864 if (e1000_igp_2_cable_length_table[min_agc_index] >
1865 e1000_igp_2_cable_length_table[cur_agc_index])
1866 min_agc_index = cur_agc_index;
1867 if (e1000_igp_2_cable_length_table[max_agc_index] <
1868 e1000_igp_2_cable_length_table[cur_agc_index])
1869 max_agc_index = cur_agc_index;
1870
1871 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1872 }
1873
1874 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1875 e1000_igp_2_cable_length_table[max_agc_index]);
1876 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1877
1878 /* Calculate cable length with the error range of +/- 10 meters. */
1879 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1880 (agc_value - IGP02E1000_AGC_RANGE) : 0);
1881 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1882
1883 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1884
1885 return 0;
1886 }
1887
1888 /**
1889 * e1000e_get_phy_info_m88 - Retrieve PHY information
1890 * @hw: pointer to the HW structure
1891 *
1892 * Valid for only copper links. Read the PHY status register (sticky read)
1893 * to verify that link is up. Read the PHY special control register to
1894 * determine the polarity and 10base-T extended distance. Read the PHY
1895 * special status register to determine MDI/MDIx and current speed. If
1896 * speed is 1000, then determine cable length, local and remote receiver.
1897 **/
e1000e_get_phy_info_m88(struct e1000_hw * hw)1898 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1899 {
1900 struct e1000_phy_info *phy = &hw->phy;
1901 s32 ret_val;
1902 u16 phy_data;
1903 bool link;
1904
1905 if (phy->media_type != e1000_media_type_copper) {
1906 e_dbg("Phy info is only valid for copper media\n");
1907 return -E1000_ERR_CONFIG;
1908 }
1909
1910 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1911 if (ret_val)
1912 return ret_val;
1913
1914 if (!link) {
1915 e_dbg("Phy info is only valid if link is up\n");
1916 return -E1000_ERR_CONFIG;
1917 }
1918
1919 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1920 if (ret_val)
1921 return ret_val;
1922
1923 phy->polarity_correction = !!(phy_data &
1924 M88E1000_PSCR_POLARITY_REVERSAL);
1925
1926 ret_val = e1000_check_polarity_m88(hw);
1927 if (ret_val)
1928 return ret_val;
1929
1930 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1931 if (ret_val)
1932 return ret_val;
1933
1934 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
1935
1936 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1937 ret_val = hw->phy.ops.get_cable_length(hw);
1938 if (ret_val)
1939 return ret_val;
1940
1941 ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data);
1942 if (ret_val)
1943 return ret_val;
1944
1945 phy->local_rx = (phy_data & LPA_1000LOCALRXOK)
1946 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1947
1948 phy->remote_rx = (phy_data & LPA_1000REMRXOK)
1949 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1950 } else {
1951 /* Set values to "undefined" */
1952 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1953 phy->local_rx = e1000_1000t_rx_status_undefined;
1954 phy->remote_rx = e1000_1000t_rx_status_undefined;
1955 }
1956
1957 return ret_val;
1958 }
1959
1960 /**
1961 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1962 * @hw: pointer to the HW structure
1963 *
1964 * Read PHY status to determine if link is up. If link is up, then
1965 * set/determine 10base-T extended distance and polarity correction. Read
1966 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1967 * determine on the cable length, local and remote receiver.
1968 **/
e1000e_get_phy_info_igp(struct e1000_hw * hw)1969 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1970 {
1971 struct e1000_phy_info *phy = &hw->phy;
1972 s32 ret_val;
1973 u16 data;
1974 bool link;
1975
1976 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1977 if (ret_val)
1978 return ret_val;
1979
1980 if (!link) {
1981 e_dbg("Phy info is only valid if link is up\n");
1982 return -E1000_ERR_CONFIG;
1983 }
1984
1985 phy->polarity_correction = true;
1986
1987 ret_val = e1000_check_polarity_igp(hw);
1988 if (ret_val)
1989 return ret_val;
1990
1991 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1992 if (ret_val)
1993 return ret_val;
1994
1995 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
1996
1997 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1998 IGP01E1000_PSSR_SPEED_1000MBPS) {
1999 ret_val = phy->ops.get_cable_length(hw);
2000 if (ret_val)
2001 return ret_val;
2002
2003 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
2004 if (ret_val)
2005 return ret_val;
2006
2007 phy->local_rx = (data & LPA_1000LOCALRXOK)
2008 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2009
2010 phy->remote_rx = (data & LPA_1000REMRXOK)
2011 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2012 } else {
2013 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2014 phy->local_rx = e1000_1000t_rx_status_undefined;
2015 phy->remote_rx = e1000_1000t_rx_status_undefined;
2016 }
2017
2018 return ret_val;
2019 }
2020
2021 /**
2022 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2023 * @hw: pointer to the HW structure
2024 *
2025 * Populates "phy" structure with various feature states.
2026 **/
e1000_get_phy_info_ife(struct e1000_hw * hw)2027 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2028 {
2029 struct e1000_phy_info *phy = &hw->phy;
2030 s32 ret_val;
2031 u16 data;
2032 bool link;
2033
2034 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2035 if (ret_val)
2036 return ret_val;
2037
2038 if (!link) {
2039 e_dbg("Phy info is only valid if link is up\n");
2040 return -E1000_ERR_CONFIG;
2041 }
2042
2043 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2044 if (ret_val)
2045 return ret_val;
2046 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2047
2048 if (phy->polarity_correction) {
2049 ret_val = e1000_check_polarity_ife(hw);
2050 if (ret_val)
2051 return ret_val;
2052 } else {
2053 /* Polarity is forced */
2054 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2055 ? e1000_rev_polarity_reversed
2056 : e1000_rev_polarity_normal);
2057 }
2058
2059 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2060 if (ret_val)
2061 return ret_val;
2062
2063 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2064
2065 /* The following parameters are undefined for 10/100 operation. */
2066 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2067 phy->local_rx = e1000_1000t_rx_status_undefined;
2068 phy->remote_rx = e1000_1000t_rx_status_undefined;
2069
2070 return 0;
2071 }
2072
2073 /**
2074 * e1000e_phy_sw_reset - PHY software reset
2075 * @hw: pointer to the HW structure
2076 *
2077 * Does a software reset of the PHY by reading the PHY control register and
2078 * setting/write the control register reset bit to the PHY.
2079 **/
e1000e_phy_sw_reset(struct e1000_hw * hw)2080 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2081 {
2082 s32 ret_val;
2083 u16 phy_ctrl;
2084
2085 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
2086 if (ret_val)
2087 return ret_val;
2088
2089 phy_ctrl |= BMCR_RESET;
2090 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
2091 if (ret_val)
2092 return ret_val;
2093
2094 udelay(1);
2095
2096 return ret_val;
2097 }
2098
2099 /**
2100 * e1000e_phy_hw_reset_generic - PHY hardware reset
2101 * @hw: pointer to the HW structure
2102 *
2103 * Verify the reset block is not blocking us from resetting. Acquire
2104 * semaphore (if necessary) and read/set/write the device control reset
2105 * bit in the PHY. Wait the appropriate delay time for the device to
2106 * reset and release the semaphore (if necessary).
2107 **/
e1000e_phy_hw_reset_generic(struct e1000_hw * hw)2108 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2109 {
2110 struct e1000_phy_info *phy = &hw->phy;
2111 s32 ret_val;
2112 u32 ctrl;
2113
2114 if (phy->ops.check_reset_block) {
2115 ret_val = phy->ops.check_reset_block(hw);
2116 if (ret_val)
2117 return 0;
2118 }
2119
2120 ret_val = phy->ops.acquire(hw);
2121 if (ret_val)
2122 return ret_val;
2123
2124 ctrl = er32(CTRL);
2125 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2126 e1e_flush();
2127
2128 udelay(phy->reset_delay_us);
2129
2130 ew32(CTRL, ctrl);
2131 e1e_flush();
2132
2133 usleep_range(150, 300);
2134
2135 phy->ops.release(hw);
2136
2137 return phy->ops.get_cfg_done(hw);
2138 }
2139
2140 /**
2141 * e1000e_get_cfg_done_generic - Generic configuration done
2142 * @hw: pointer to the HW structure
2143 *
2144 * Generic function to wait 10 milli-seconds for configuration to complete
2145 * and return success.
2146 **/
e1000e_get_cfg_done_generic(struct e1000_hw __always_unused * hw)2147 s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw)
2148 {
2149 mdelay(10);
2150
2151 return 0;
2152 }
2153
2154 /**
2155 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2156 * @hw: pointer to the HW structure
2157 *
2158 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2159 **/
e1000e_phy_init_script_igp3(struct e1000_hw * hw)2160 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2161 {
2162 e_dbg("Running IGP 3 PHY init script\n");
2163
2164 /* PHY init IGP 3 */
2165 /* Enable rise/fall, 10-mode work in class-A */
2166 e1e_wphy(hw, 0x2F5B, 0x9018);
2167 /* Remove all caps from Replica path filter */
2168 e1e_wphy(hw, 0x2F52, 0x0000);
2169 /* Bias trimming for ADC, AFE and Driver (Default) */
2170 e1e_wphy(hw, 0x2FB1, 0x8B24);
2171 /* Increase Hybrid poly bias */
2172 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2173 /* Add 4% to Tx amplitude in Gig mode */
2174 e1e_wphy(hw, 0x2010, 0x10B0);
2175 /* Disable trimming (TTT) */
2176 e1e_wphy(hw, 0x2011, 0x0000);
2177 /* Poly DC correction to 94.6% + 2% for all channels */
2178 e1e_wphy(hw, 0x20DD, 0x249A);
2179 /* ABS DC correction to 95.9% */
2180 e1e_wphy(hw, 0x20DE, 0x00D3);
2181 /* BG temp curve trim */
2182 e1e_wphy(hw, 0x28B4, 0x04CE);
2183 /* Increasing ADC OPAMP stage 1 currents to max */
2184 e1e_wphy(hw, 0x2F70, 0x29E4);
2185 /* Force 1000 ( required for enabling PHY regs configuration) */
2186 e1e_wphy(hw, 0x0000, 0x0140);
2187 /* Set upd_freq to 6 */
2188 e1e_wphy(hw, 0x1F30, 0x1606);
2189 /* Disable NPDFE */
2190 e1e_wphy(hw, 0x1F31, 0xB814);
2191 /* Disable adaptive fixed FFE (Default) */
2192 e1e_wphy(hw, 0x1F35, 0x002A);
2193 /* Enable FFE hysteresis */
2194 e1e_wphy(hw, 0x1F3E, 0x0067);
2195 /* Fixed FFE for short cable lengths */
2196 e1e_wphy(hw, 0x1F54, 0x0065);
2197 /* Fixed FFE for medium cable lengths */
2198 e1e_wphy(hw, 0x1F55, 0x002A);
2199 /* Fixed FFE for long cable lengths */
2200 e1e_wphy(hw, 0x1F56, 0x002A);
2201 /* Enable Adaptive Clip Threshold */
2202 e1e_wphy(hw, 0x1F72, 0x3FB0);
2203 /* AHT reset limit to 1 */
2204 e1e_wphy(hw, 0x1F76, 0xC0FF);
2205 /* Set AHT master delay to 127 msec */
2206 e1e_wphy(hw, 0x1F77, 0x1DEC);
2207 /* Set scan bits for AHT */
2208 e1e_wphy(hw, 0x1F78, 0xF9EF);
2209 /* Set AHT Preset bits */
2210 e1e_wphy(hw, 0x1F79, 0x0210);
2211 /* Change integ_factor of channel A to 3 */
2212 e1e_wphy(hw, 0x1895, 0x0003);
2213 /* Change prop_factor of channels BCD to 8 */
2214 e1e_wphy(hw, 0x1796, 0x0008);
2215 /* Change cg_icount + enable integbp for channels BCD */
2216 e1e_wphy(hw, 0x1798, 0xD008);
2217 /* Change cg_icount + enable integbp + change prop_factor_master
2218 * to 8 for channel A
2219 */
2220 e1e_wphy(hw, 0x1898, 0xD918);
2221 /* Disable AHT in Slave mode on channel A */
2222 e1e_wphy(hw, 0x187A, 0x0800);
2223 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2224 * Enable SPD+B2B
2225 */
2226 e1e_wphy(hw, 0x0019, 0x008D);
2227 /* Enable restart AN on an1000_dis change */
2228 e1e_wphy(hw, 0x001B, 0x2080);
2229 /* Enable wh_fifo read clock in 10/100 modes */
2230 e1e_wphy(hw, 0x0014, 0x0045);
2231 /* Restart AN, Speed selection is 1000 */
2232 e1e_wphy(hw, 0x0000, 0x1340);
2233
2234 return 0;
2235 }
2236
2237 /**
2238 * e1000e_get_phy_type_from_id - Get PHY type from id
2239 * @phy_id: phy_id read from the phy
2240 *
2241 * Returns the phy type from the id.
2242 **/
e1000e_get_phy_type_from_id(u32 phy_id)2243 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2244 {
2245 enum e1000_phy_type phy_type = e1000_phy_unknown;
2246
2247 switch (phy_id) {
2248 case M88E1000_I_PHY_ID:
2249 case M88E1000_E_PHY_ID:
2250 case M88E1111_I_PHY_ID:
2251 case M88E1011_I_PHY_ID:
2252 phy_type = e1000_phy_m88;
2253 break;
2254 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2255 phy_type = e1000_phy_igp_2;
2256 break;
2257 case GG82563_E_PHY_ID:
2258 phy_type = e1000_phy_gg82563;
2259 break;
2260 case IGP03E1000_E_PHY_ID:
2261 phy_type = e1000_phy_igp_3;
2262 break;
2263 case IFE_E_PHY_ID:
2264 case IFE_PLUS_E_PHY_ID:
2265 case IFE_C_E_PHY_ID:
2266 phy_type = e1000_phy_ife;
2267 break;
2268 case BME1000_E_PHY_ID:
2269 case BME1000_E_PHY_ID_R2:
2270 phy_type = e1000_phy_bm;
2271 break;
2272 case I82578_E_PHY_ID:
2273 phy_type = e1000_phy_82578;
2274 break;
2275 case I82577_E_PHY_ID:
2276 phy_type = e1000_phy_82577;
2277 break;
2278 case I82579_E_PHY_ID:
2279 phy_type = e1000_phy_82579;
2280 break;
2281 case I217_E_PHY_ID:
2282 phy_type = e1000_phy_i217;
2283 break;
2284 default:
2285 phy_type = e1000_phy_unknown;
2286 break;
2287 }
2288 return phy_type;
2289 }
2290
2291 /**
2292 * e1000e_determine_phy_address - Determines PHY address.
2293 * @hw: pointer to the HW structure
2294 *
2295 * This uses a trial and error method to loop through possible PHY
2296 * addresses. It tests each by reading the PHY ID registers and
2297 * checking for a match.
2298 **/
e1000e_determine_phy_address(struct e1000_hw * hw)2299 s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2300 {
2301 u32 phy_addr = 0;
2302 u32 i;
2303 enum e1000_phy_type phy_type = e1000_phy_unknown;
2304
2305 hw->phy.id = phy_type;
2306
2307 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2308 hw->phy.addr = phy_addr;
2309 i = 0;
2310
2311 do {
2312 e1000e_get_phy_id(hw);
2313 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2314
2315 /* If phy_type is valid, break - we found our
2316 * PHY address
2317 */
2318 if (phy_type != e1000_phy_unknown)
2319 return 0;
2320
2321 usleep_range(1000, 2000);
2322 i++;
2323 } while (i < 10);
2324 }
2325
2326 return -E1000_ERR_PHY_TYPE;
2327 }
2328
2329 /**
2330 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2331 * @page: page to access
2332 *
2333 * Returns the phy address for the page requested.
2334 **/
e1000_get_phy_addr_for_bm_page(u32 page,u32 reg)2335 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2336 {
2337 u32 phy_addr = 2;
2338
2339 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2340 phy_addr = 1;
2341
2342 return phy_addr;
2343 }
2344
2345 /**
2346 * e1000e_write_phy_reg_bm - Write BM PHY register
2347 * @hw: pointer to the HW structure
2348 * @offset: register offset to write to
2349 * @data: data to write at register offset
2350 *
2351 * Acquires semaphore, if necessary, then writes the data to PHY register
2352 * at the offset. Release any acquired semaphores before exiting.
2353 **/
e1000e_write_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 data)2354 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2355 {
2356 s32 ret_val;
2357 u32 page = offset >> IGP_PAGE_SHIFT;
2358
2359 ret_val = hw->phy.ops.acquire(hw);
2360 if (ret_val)
2361 return ret_val;
2362
2363 /* Page 800 works differently than the rest so it has its own func */
2364 if (page == BM_WUC_PAGE) {
2365 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2366 false, false);
2367 goto release;
2368 }
2369
2370 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2371
2372 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2373 u32 page_shift, page_select;
2374
2375 /* Page select is register 31 for phy address 1 and 22 for
2376 * phy address 2 and 3. Page select is shifted only for
2377 * phy address 1.
2378 */
2379 if (hw->phy.addr == 1) {
2380 page_shift = IGP_PAGE_SHIFT;
2381 page_select = IGP01E1000_PHY_PAGE_SELECT;
2382 } else {
2383 page_shift = 0;
2384 page_select = BM_PHY_PAGE_SELECT;
2385 }
2386
2387 /* Page is shifted left, PHY expects (page x 32) */
2388 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2389 (page << page_shift));
2390 if (ret_val)
2391 goto release;
2392 }
2393
2394 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2395 data);
2396
2397 release:
2398 hw->phy.ops.release(hw);
2399 return ret_val;
2400 }
2401
2402 /**
2403 * e1000e_read_phy_reg_bm - Read BM PHY register
2404 * @hw: pointer to the HW structure
2405 * @offset: register offset to be read
2406 * @data: pointer to the read data
2407 *
2408 * Acquires semaphore, if necessary, then reads the PHY register at offset
2409 * and storing the retrieved information in data. Release any acquired
2410 * semaphores before exiting.
2411 **/
e1000e_read_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data)2412 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2413 {
2414 s32 ret_val;
2415 u32 page = offset >> IGP_PAGE_SHIFT;
2416
2417 ret_val = hw->phy.ops.acquire(hw);
2418 if (ret_val)
2419 return ret_val;
2420
2421 /* Page 800 works differently than the rest so it has its own func */
2422 if (page == BM_WUC_PAGE) {
2423 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2424 true, false);
2425 goto release;
2426 }
2427
2428 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2429
2430 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2431 u32 page_shift, page_select;
2432
2433 /* Page select is register 31 for phy address 1 and 22 for
2434 * phy address 2 and 3. Page select is shifted only for
2435 * phy address 1.
2436 */
2437 if (hw->phy.addr == 1) {
2438 page_shift = IGP_PAGE_SHIFT;
2439 page_select = IGP01E1000_PHY_PAGE_SELECT;
2440 } else {
2441 page_shift = 0;
2442 page_select = BM_PHY_PAGE_SELECT;
2443 }
2444
2445 /* Page is shifted left, PHY expects (page x 32) */
2446 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2447 (page << page_shift));
2448 if (ret_val)
2449 goto release;
2450 }
2451
2452 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2453 data);
2454 release:
2455 hw->phy.ops.release(hw);
2456 return ret_val;
2457 }
2458
2459 /**
2460 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2461 * @hw: pointer to the HW structure
2462 * @offset: register offset to be read
2463 * @data: pointer to the read data
2464 *
2465 * Acquires semaphore, if necessary, then reads the PHY register at offset
2466 * and storing the retrieved information in data. Release any acquired
2467 * semaphores before exiting.
2468 **/
e1000e_read_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 * data)2469 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2470 {
2471 s32 ret_val;
2472 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2473
2474 ret_val = hw->phy.ops.acquire(hw);
2475 if (ret_val)
2476 return ret_val;
2477
2478 /* Page 800 works differently than the rest so it has its own func */
2479 if (page == BM_WUC_PAGE) {
2480 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2481 true, false);
2482 goto release;
2483 }
2484
2485 hw->phy.addr = 1;
2486
2487 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2488 /* Page is shifted left, PHY expects (page x 32) */
2489 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2490 page);
2491
2492 if (ret_val)
2493 goto release;
2494 }
2495
2496 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2497 data);
2498 release:
2499 hw->phy.ops.release(hw);
2500 return ret_val;
2501 }
2502
2503 /**
2504 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2505 * @hw: pointer to the HW structure
2506 * @offset: register offset to write to
2507 * @data: data to write at register offset
2508 *
2509 * Acquires semaphore, if necessary, then writes the data to PHY register
2510 * at the offset. Release any acquired semaphores before exiting.
2511 **/
e1000e_write_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 data)2512 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2513 {
2514 s32 ret_val;
2515 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2516
2517 ret_val = hw->phy.ops.acquire(hw);
2518 if (ret_val)
2519 return ret_val;
2520
2521 /* Page 800 works differently than the rest so it has its own func */
2522 if (page == BM_WUC_PAGE) {
2523 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2524 false, false);
2525 goto release;
2526 }
2527
2528 hw->phy.addr = 1;
2529
2530 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2531 /* Page is shifted left, PHY expects (page x 32) */
2532 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2533 page);
2534
2535 if (ret_val)
2536 goto release;
2537 }
2538
2539 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2540 data);
2541
2542 release:
2543 hw->phy.ops.release(hw);
2544 return ret_val;
2545 }
2546
2547 /**
2548 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2549 * @hw: pointer to the HW structure
2550 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2551 *
2552 * Assumes semaphore already acquired and phy_reg points to a valid memory
2553 * address to store contents of the BM_WUC_ENABLE_REG register.
2554 **/
e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw * hw,u16 * phy_reg)2555 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2556 {
2557 s32 ret_val;
2558 u16 temp;
2559
2560 /* All page select, port ctrl and wakeup registers use phy address 1 */
2561 hw->phy.addr = 1;
2562
2563 /* Select Port Control Registers page */
2564 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2565 if (ret_val) {
2566 e_dbg("Could not set Port Control page\n");
2567 return ret_val;
2568 }
2569
2570 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2571 if (ret_val) {
2572 e_dbg("Could not read PHY register %d.%d\n",
2573 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2574 return ret_val;
2575 }
2576
2577 /* Enable both PHY wakeup mode and Wakeup register page writes.
2578 * Prevent a power state change by disabling ME and Host PHY wakeup.
2579 */
2580 temp = *phy_reg;
2581 temp |= BM_WUC_ENABLE_BIT;
2582 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2583
2584 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2585 if (ret_val) {
2586 e_dbg("Could not write PHY register %d.%d\n",
2587 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2588 return ret_val;
2589 }
2590
2591 /* Select Host Wakeup Registers page - caller now able to write
2592 * registers on the Wakeup registers page
2593 */
2594 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2595 }
2596
2597 /**
2598 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2599 * @hw: pointer to the HW structure
2600 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2601 *
2602 * Restore BM_WUC_ENABLE_REG to its original value.
2603 *
2604 * Assumes semaphore already acquired and *phy_reg is the contents of the
2605 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2606 * caller.
2607 **/
e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw * hw,u16 * phy_reg)2608 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2609 {
2610 s32 ret_val;
2611
2612 /* Select Port Control Registers page */
2613 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2614 if (ret_val) {
2615 e_dbg("Could not set Port Control page\n");
2616 return ret_val;
2617 }
2618
2619 /* Restore 769.17 to its original value */
2620 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2621 if (ret_val)
2622 e_dbg("Could not restore PHY register %d.%d\n",
2623 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2624
2625 return ret_val;
2626 }
2627
2628 /**
2629 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2630 * @hw: pointer to the HW structure
2631 * @offset: register offset to be read or written
2632 * @data: pointer to the data to read or write
2633 * @read: determines if operation is read or write
2634 * @page_set: BM_WUC_PAGE already set and access enabled
2635 *
2636 * Read the PHY register at offset and store the retrieved information in
2637 * data, or write data to PHY register at offset. Note the procedure to
2638 * access the PHY wakeup registers is different than reading the other PHY
2639 * registers. It works as such:
2640 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2641 * 2) Set page to 800 for host (801 if we were manageability)
2642 * 3) Write the address using the address opcode (0x11)
2643 * 4) Read or write the data using the data opcode (0x12)
2644 * 5) Restore 769.17.2 to its original value
2645 *
2646 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2647 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2648 *
2649 * Assumes semaphore is already acquired. When page_set==true, assumes
2650 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2651 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2652 **/
e1000_access_phy_wakeup_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data,bool read,bool page_set)2653 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2654 u16 *data, bool read, bool page_set)
2655 {
2656 s32 ret_val;
2657 u16 reg = BM_PHY_REG_NUM(offset);
2658 u16 page = BM_PHY_REG_PAGE(offset);
2659 u16 phy_reg = 0;
2660
2661 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2662 if ((hw->mac.type == e1000_pchlan) &&
2663 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2664 e_dbg("Attempting to access page %d while gig enabled.\n",
2665 page);
2666
2667 if (!page_set) {
2668 /* Enable access to PHY wakeup registers */
2669 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2670 if (ret_val) {
2671 e_dbg("Could not enable PHY wakeup reg access\n");
2672 return ret_val;
2673 }
2674 }
2675
2676 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2677
2678 /* Write the Wakeup register page offset value using opcode 0x11 */
2679 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2680 if (ret_val) {
2681 e_dbg("Could not write address opcode to page %d\n", page);
2682 return ret_val;
2683 }
2684
2685 if (read) {
2686 /* Read the Wakeup register page value using opcode 0x12 */
2687 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2688 data);
2689 } else {
2690 /* Write the Wakeup register page value using opcode 0x12 */
2691 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2692 *data);
2693 }
2694
2695 if (ret_val) {
2696 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2697 return ret_val;
2698 }
2699
2700 if (!page_set)
2701 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2702
2703 return ret_val;
2704 }
2705
2706 /**
2707 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2708 * @hw: pointer to the HW structure
2709 *
2710 * In the case of a PHY power down to save power, or to turn off link during a
2711 * driver unload, or wake on lan is not enabled, restore the link to previous
2712 * settings.
2713 **/
e1000_power_up_phy_copper(struct e1000_hw * hw)2714 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2715 {
2716 u16 mii_reg = 0;
2717
2718 /* The PHY will retain its settings across a power down/up cycle */
2719 e1e_rphy(hw, MII_BMCR, &mii_reg);
2720 mii_reg &= ~BMCR_PDOWN;
2721 e1e_wphy(hw, MII_BMCR, mii_reg);
2722 }
2723
2724 /**
2725 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2726 * @hw: pointer to the HW structure
2727 *
2728 * In the case of a PHY power down to save power, or to turn off link during a
2729 * driver unload, or wake on lan is not enabled, restore the link to previous
2730 * settings.
2731 **/
e1000_power_down_phy_copper(struct e1000_hw * hw)2732 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2733 {
2734 u16 mii_reg = 0;
2735
2736 /* The PHY will retain its settings across a power down/up cycle */
2737 e1e_rphy(hw, MII_BMCR, &mii_reg);
2738 mii_reg |= BMCR_PDOWN;
2739 e1e_wphy(hw, MII_BMCR, mii_reg);
2740 usleep_range(1000, 2000);
2741 }
2742
2743 /**
2744 * __e1000_read_phy_reg_hv - Read HV PHY register
2745 * @hw: pointer to the HW structure
2746 * @offset: register offset to be read
2747 * @data: pointer to the read data
2748 * @locked: semaphore has already been acquired or not
2749 *
2750 * Acquires semaphore, if necessary, then reads the PHY register at offset
2751 * and stores the retrieved information in data. Release any acquired
2752 * semaphore before exiting.
2753 **/
__e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool locked,bool page_set)2754 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2755 bool locked, bool page_set)
2756 {
2757 s32 ret_val;
2758 u16 page = BM_PHY_REG_PAGE(offset);
2759 u16 reg = BM_PHY_REG_NUM(offset);
2760 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2761
2762 if (!locked) {
2763 ret_val = hw->phy.ops.acquire(hw);
2764 if (ret_val)
2765 return ret_val;
2766 }
2767
2768 /* Page 800 works differently than the rest so it has its own func */
2769 if (page == BM_WUC_PAGE) {
2770 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2771 true, page_set);
2772 goto out;
2773 }
2774
2775 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2776 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2777 data, true);
2778 goto out;
2779 }
2780
2781 if (!page_set) {
2782 if (page == HV_INTC_FC_PAGE_START)
2783 page = 0;
2784
2785 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2786 /* Page is shifted left, PHY expects (page x 32) */
2787 ret_val = e1000_set_page_igp(hw,
2788 (page << IGP_PAGE_SHIFT));
2789
2790 hw->phy.addr = phy_addr;
2791
2792 if (ret_val)
2793 goto out;
2794 }
2795 }
2796
2797 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2798 page << IGP_PAGE_SHIFT, reg);
2799
2800 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data);
2801 out:
2802 if (!locked)
2803 hw->phy.ops.release(hw);
2804
2805 return ret_val;
2806 }
2807
2808 /**
2809 * e1000_read_phy_reg_hv - Read HV PHY register
2810 * @hw: pointer to the HW structure
2811 * @offset: register offset to be read
2812 * @data: pointer to the read data
2813 *
2814 * Acquires semaphore then reads the PHY register at offset and stores
2815 * the retrieved information in data. Release the acquired semaphore
2816 * before exiting.
2817 **/
e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data)2818 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2819 {
2820 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2821 }
2822
2823 /**
2824 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2825 * @hw: pointer to the HW structure
2826 * @offset: register offset to be read
2827 * @data: pointer to the read data
2828 *
2829 * Reads the PHY register at offset and stores the retrieved information
2830 * in data. Assumes semaphore already acquired.
2831 **/
e1000_read_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 * data)2832 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2833 {
2834 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2835 }
2836
2837 /**
2838 * e1000_read_phy_reg_page_hv - Read HV PHY register
2839 * @hw: pointer to the HW structure
2840 * @offset: register offset to write to
2841 * @data: data to write at register offset
2842 *
2843 * Reads the PHY register at offset and stores the retrieved information
2844 * in data. Assumes semaphore already acquired and page already set.
2845 **/
e1000_read_phy_reg_page_hv(struct e1000_hw * hw,u32 offset,u16 * data)2846 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2847 {
2848 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2849 }
2850
2851 /**
2852 * __e1000_write_phy_reg_hv - Write HV PHY register
2853 * @hw: pointer to the HW structure
2854 * @offset: register offset to write to
2855 * @data: data to write at register offset
2856 * @locked: semaphore has already been acquired or not
2857 *
2858 * Acquires semaphore, if necessary, then writes the data to PHY register
2859 * at the offset. Release any acquired semaphores before exiting.
2860 **/
__e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data,bool locked,bool page_set)2861 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2862 bool locked, bool page_set)
2863 {
2864 s32 ret_val;
2865 u16 page = BM_PHY_REG_PAGE(offset);
2866 u16 reg = BM_PHY_REG_NUM(offset);
2867 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2868
2869 if (!locked) {
2870 ret_val = hw->phy.ops.acquire(hw);
2871 if (ret_val)
2872 return ret_val;
2873 }
2874
2875 /* Page 800 works differently than the rest so it has its own func */
2876 if (page == BM_WUC_PAGE) {
2877 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2878 false, page_set);
2879 goto out;
2880 }
2881
2882 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2883 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2884 &data, false);
2885 goto out;
2886 }
2887
2888 if (!page_set) {
2889 if (page == HV_INTC_FC_PAGE_START)
2890 page = 0;
2891
2892 /* Workaround MDIO accesses being disabled after entering IEEE
2893 * Power Down (when bit 11 of the PHY Control register is set)
2894 */
2895 if ((hw->phy.type == e1000_phy_82578) &&
2896 (hw->phy.revision >= 1) &&
2897 (hw->phy.addr == 2) &&
2898 !(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) {
2899 u16 data2 = 0x7EFF;
2900
2901 ret_val = e1000_access_phy_debug_regs_hv(hw,
2902 (1 << 6) | 0x3,
2903 &data2, false);
2904 if (ret_val)
2905 goto out;
2906 }
2907
2908 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2909 /* Page is shifted left, PHY expects (page x 32) */
2910 ret_val = e1000_set_page_igp(hw,
2911 (page << IGP_PAGE_SHIFT));
2912
2913 hw->phy.addr = phy_addr;
2914
2915 if (ret_val)
2916 goto out;
2917 }
2918 }
2919
2920 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2921 page << IGP_PAGE_SHIFT, reg);
2922
2923 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2924 data);
2925
2926 out:
2927 if (!locked)
2928 hw->phy.ops.release(hw);
2929
2930 return ret_val;
2931 }
2932
2933 /**
2934 * e1000_write_phy_reg_hv - Write HV PHY register
2935 * @hw: pointer to the HW structure
2936 * @offset: register offset to write to
2937 * @data: data to write at register offset
2938 *
2939 * Acquires semaphore then writes the data to PHY register at the offset.
2940 * Release the acquired semaphores before exiting.
2941 **/
e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data)2942 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2943 {
2944 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
2945 }
2946
2947 /**
2948 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2949 * @hw: pointer to the HW structure
2950 * @offset: register offset to write to
2951 * @data: data to write at register offset
2952 *
2953 * Writes the data to PHY register at the offset. Assumes semaphore
2954 * already acquired.
2955 **/
e1000_write_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 data)2956 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
2957 {
2958 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
2959 }
2960
2961 /**
2962 * e1000_write_phy_reg_page_hv - Write HV PHY register
2963 * @hw: pointer to the HW structure
2964 * @offset: register offset to write to
2965 * @data: data to write at register offset
2966 *
2967 * Writes the data to PHY register at the offset. Assumes semaphore
2968 * already acquired and page already set.
2969 **/
e1000_write_phy_reg_page_hv(struct e1000_hw * hw,u32 offset,u16 data)2970 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
2971 {
2972 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
2973 }
2974
2975 /**
2976 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
2977 * @page: page to be accessed
2978 **/
e1000_get_phy_addr_for_hv_page(u32 page)2979 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
2980 {
2981 u32 phy_addr = 2;
2982
2983 if (page >= HV_INTC_FC_PAGE_START)
2984 phy_addr = 1;
2985
2986 return phy_addr;
2987 }
2988
2989 /**
2990 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
2991 * @hw: pointer to the HW structure
2992 * @offset: register offset to be read or written
2993 * @data: pointer to the data to be read or written
2994 * @read: determines if operation is read or write
2995 *
2996 * Reads the PHY register at offset and stores the retreived information
2997 * in data. Assumes semaphore already acquired. Note that the procedure
2998 * to access these regs uses the address port and data port to read/write.
2999 * These accesses done with PHY address 2 and without using pages.
3000 **/
e1000_access_phy_debug_regs_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool read)3001 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3002 u16 *data, bool read)
3003 {
3004 s32 ret_val;
3005 u32 addr_reg;
3006 u32 data_reg;
3007
3008 /* This takes care of the difference with desktop vs mobile phy */
3009 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3010 I82578_ADDR_REG : I82577_ADDR_REG);
3011 data_reg = addr_reg + 1;
3012
3013 /* All operations in this function are phy address 2 */
3014 hw->phy.addr = 2;
3015
3016 /* masking with 0x3F to remove the page from offset */
3017 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3018 if (ret_val) {
3019 e_dbg("Could not write the Address Offset port register\n");
3020 return ret_val;
3021 }
3022
3023 /* Read or write the data value next */
3024 if (read)
3025 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3026 else
3027 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3028
3029 if (ret_val)
3030 e_dbg("Could not access the Data port register\n");
3031
3032 return ret_val;
3033 }
3034
3035 /**
3036 * e1000_link_stall_workaround_hv - Si workaround
3037 * @hw: pointer to the HW structure
3038 *
3039 * This function works around a Si bug where the link partner can get
3040 * a link up indication before the PHY does. If small packets are sent
3041 * by the link partner they can be placed in the packet buffer without
3042 * being properly accounted for by the PHY and will stall preventing
3043 * further packets from being received. The workaround is to clear the
3044 * packet buffer after the PHY detects link up.
3045 **/
e1000_link_stall_workaround_hv(struct e1000_hw * hw)3046 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3047 {
3048 s32 ret_val = 0;
3049 u16 data;
3050
3051 if (hw->phy.type != e1000_phy_82578)
3052 return 0;
3053
3054 /* Do not apply workaround if in PHY loopback bit 14 set */
3055 e1e_rphy(hw, MII_BMCR, &data);
3056 if (data & BMCR_LOOPBACK)
3057 return 0;
3058
3059 /* check if link is up and at 1Gbps */
3060 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3061 if (ret_val)
3062 return ret_val;
3063
3064 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3065 BM_CS_STATUS_SPEED_MASK);
3066
3067 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3068 BM_CS_STATUS_SPEED_1000))
3069 return 0;
3070
3071 msleep(200);
3072
3073 /* flush the packets in the fifo buffer */
3074 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL,
3075 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3076 HV_MUX_DATA_CTRL_FORCE_SPEED));
3077 if (ret_val)
3078 return ret_val;
3079
3080 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3081 }
3082
3083 /**
3084 * e1000_check_polarity_82577 - Checks the polarity.
3085 * @hw: pointer to the HW structure
3086 *
3087 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3088 *
3089 * Polarity is determined based on the PHY specific status register.
3090 **/
e1000_check_polarity_82577(struct e1000_hw * hw)3091 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3092 {
3093 struct e1000_phy_info *phy = &hw->phy;
3094 s32 ret_val;
3095 u16 data;
3096
3097 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3098
3099 if (!ret_val)
3100 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3101 ? e1000_rev_polarity_reversed
3102 : e1000_rev_polarity_normal);
3103
3104 return ret_val;
3105 }
3106
3107 /**
3108 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3109 * @hw: pointer to the HW structure
3110 *
3111 * Calls the PHY setup function to force speed and duplex.
3112 **/
e1000_phy_force_speed_duplex_82577(struct e1000_hw * hw)3113 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3114 {
3115 struct e1000_phy_info *phy = &hw->phy;
3116 s32 ret_val;
3117 u16 phy_data;
3118 bool link;
3119
3120 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
3121 if (ret_val)
3122 return ret_val;
3123
3124 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3125
3126 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
3127 if (ret_val)
3128 return ret_val;
3129
3130 udelay(1);
3131
3132 if (phy->autoneg_wait_to_complete) {
3133 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3134
3135 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3136 100000, &link);
3137 if (ret_val)
3138 return ret_val;
3139
3140 if (!link)
3141 e_dbg("Link taking longer than expected.\n");
3142
3143 /* Try once more */
3144 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3145 100000, &link);
3146 }
3147
3148 return ret_val;
3149 }
3150
3151 /**
3152 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3153 * @hw: pointer to the HW structure
3154 *
3155 * Read PHY status to determine if link is up. If link is up, then
3156 * set/determine 10base-T extended distance and polarity correction. Read
3157 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3158 * determine on the cable length, local and remote receiver.
3159 **/
e1000_get_phy_info_82577(struct e1000_hw * hw)3160 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3161 {
3162 struct e1000_phy_info *phy = &hw->phy;
3163 s32 ret_val;
3164 u16 data;
3165 bool link;
3166
3167 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3168 if (ret_val)
3169 return ret_val;
3170
3171 if (!link) {
3172 e_dbg("Phy info is only valid if link is up\n");
3173 return -E1000_ERR_CONFIG;
3174 }
3175
3176 phy->polarity_correction = true;
3177
3178 ret_val = e1000_check_polarity_82577(hw);
3179 if (ret_val)
3180 return ret_val;
3181
3182 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3183 if (ret_val)
3184 return ret_val;
3185
3186 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3187
3188 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3189 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3190 ret_val = hw->phy.ops.get_cable_length(hw);
3191 if (ret_val)
3192 return ret_val;
3193
3194 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
3195 if (ret_val)
3196 return ret_val;
3197
3198 phy->local_rx = (data & LPA_1000LOCALRXOK)
3199 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3200
3201 phy->remote_rx = (data & LPA_1000REMRXOK)
3202 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3203 } else {
3204 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3205 phy->local_rx = e1000_1000t_rx_status_undefined;
3206 phy->remote_rx = e1000_1000t_rx_status_undefined;
3207 }
3208
3209 return 0;
3210 }
3211
3212 /**
3213 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3214 * @hw: pointer to the HW structure
3215 *
3216 * Reads the diagnostic status register and verifies result is valid before
3217 * placing it in the phy_cable_length field.
3218 **/
e1000_get_cable_length_82577(struct e1000_hw * hw)3219 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3220 {
3221 struct e1000_phy_info *phy = &hw->phy;
3222 s32 ret_val;
3223 u16 phy_data, length;
3224
3225 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3226 if (ret_val)
3227 return ret_val;
3228
3229 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3230 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
3231
3232 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3233 return -E1000_ERR_PHY;
3234
3235 phy->cable_length = length;
3236
3237 return 0;
3238 }
3239