1 /*
2 * Defines, structures, APIs for edac_core module
3 *
4 * (C) 2007 Linux Networx (http://lnxi.com)
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
7 *
8 * Written by Thayne Harbaugh
9 * Based on work by Dan Hollis <goemon at anime dot net> and others.
10 * http://www.anime.net/~goemon/linux-ecc/
11 *
12 * NMI handling support added by
13 * Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
14 *
15 * Refactored for multi-source files:
16 * Doug Thompson <norsk5@xmission.com>
17 *
18 */
19
20 #ifndef _EDAC_CORE_H_
21 #define _EDAC_CORE_H_
22
23 #include <linux/kernel.h>
24 #include <linux/types.h>
25 #include <linux/module.h>
26 #include <linux/spinlock.h>
27 #include <linux/smp.h>
28 #include <linux/pci.h>
29 #include <linux/time.h>
30 #include <linux/nmi.h>
31 #include <linux/rcupdate.h>
32 #include <linux/completion.h>
33 #include <linux/kobject.h>
34 #include <linux/platform_device.h>
35 #include <linux/workqueue.h>
36 #include <linux/edac.h>
37
38 #define EDAC_DEVICE_NAME_LEN 31
39 #define EDAC_ATTRIB_VALUE_LEN 15
40
41 #if PAGE_SHIFT < 20
42 #define PAGES_TO_MiB(pages) ((pages) >> (20 - PAGE_SHIFT))
43 #define MiB_TO_PAGES(mb) ((mb) << (20 - PAGE_SHIFT))
44 #else /* PAGE_SHIFT > 20 */
45 #define PAGES_TO_MiB(pages) ((pages) << (PAGE_SHIFT - 20))
46 #define MiB_TO_PAGES(mb) ((mb) >> (PAGE_SHIFT - 20))
47 #endif
48
49 #define edac_printk(level, prefix, fmt, arg...) \
50 printk(level "EDAC " prefix ": " fmt, ##arg)
51
52 #define edac_mc_printk(mci, level, fmt, arg...) \
53 printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
54
55 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
56 printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
57
58 #define edac_device_printk(ctl, level, fmt, arg...) \
59 printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
60
61 #define edac_pci_printk(ctl, level, fmt, arg...) \
62 printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
63
64 /* prefixes for edac_printk() and edac_mc_printk() */
65 #define EDAC_MC "MC"
66 #define EDAC_PCI "PCI"
67 #define EDAC_DEBUG "DEBUG"
68
69 extern const char * const edac_mem_types[];
70
71 #ifdef CONFIG_EDAC_DEBUG
72 extern int edac_debug_level;
73
74 #define edac_dbg(level, fmt, ...) \
75 do { \
76 if (level <= edac_debug_level) \
77 edac_printk(KERN_DEBUG, EDAC_DEBUG, \
78 "%s: " fmt, __func__, ##__VA_ARGS__); \
79 } while (0)
80
81 #else /* !CONFIG_EDAC_DEBUG */
82
83 #define edac_dbg(level, fmt, ...) \
84 do { \
85 if (0) \
86 edac_printk(KERN_DEBUG, EDAC_DEBUG, \
87 "%s: " fmt, __func__, ##__VA_ARGS__); \
88 } while (0)
89
90 #endif /* !CONFIG_EDAC_DEBUG */
91
92 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
93 PCI_DEVICE_ID_ ## vend ## _ ## dev
94
95 #define edac_dev_name(dev) (dev)->dev_name
96
97 #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
98
99 /*
100 * The following are the structures to provide for a generic
101 * or abstract 'edac_device'. This set of structures and the
102 * code that implements the APIs for the same, provide for
103 * registering EDAC type devices which are NOT standard memory.
104 *
105 * CPU caches (L1 and L2)
106 * DMA engines
107 * Core CPU switches
108 * Fabric switch units
109 * PCIe interface controllers
110 * other EDAC/ECC type devices that can be monitored for
111 * errors, etc.
112 *
113 * It allows for a 2 level set of hierarchy. For example:
114 *
115 * cache could be composed of L1, L2 and L3 levels of cache.
116 * Each CPU core would have its own L1 cache, while sharing
117 * L2 and maybe L3 caches.
118 *
119 * View them arranged, via the sysfs presentation:
120 * /sys/devices/system/edac/..
121 *
122 * mc/ <existing memory device directory>
123 * cpu/cpu0/.. <L1 and L2 block directory>
124 * /L1-cache/ce_count
125 * /ue_count
126 * /L2-cache/ce_count
127 * /ue_count
128 * cpu/cpu1/.. <L1 and L2 block directory>
129 * /L1-cache/ce_count
130 * /ue_count
131 * /L2-cache/ce_count
132 * /ue_count
133 * ...
134 *
135 * the L1 and L2 directories would be "edac_device_block's"
136 */
137
138 struct edac_device_counter {
139 u32 ue_count;
140 u32 ce_count;
141 };
142
143 /* forward reference */
144 struct edac_device_ctl_info;
145 struct edac_device_block;
146
147 /* edac_dev_sysfs_attribute structure
148 * used for driver sysfs attributes in mem_ctl_info
149 * for extra controls and attributes:
150 * like high level error Injection controls
151 */
152 struct edac_dev_sysfs_attribute {
153 struct attribute attr;
154 ssize_t (*show)(struct edac_device_ctl_info *, char *);
155 ssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);
156 };
157
158 /* edac_dev_sysfs_block_attribute structure
159 *
160 * used in leaf 'block' nodes for adding controls/attributes
161 *
162 * each block in each instance of the containing control structure
163 * can have an array of the following. The show and store functions
164 * will be filled in with the show/store function in the
165 * low level driver.
166 *
167 * The 'value' field will be the actual value field used for
168 * counting
169 */
170 struct edac_dev_sysfs_block_attribute {
171 struct attribute attr;
172 ssize_t (*show)(struct kobject *, struct attribute *, char *);
173 ssize_t (*store)(struct kobject *, struct attribute *,
174 const char *, size_t);
175 struct edac_device_block *block;
176
177 unsigned int value;
178 };
179
180 /* device block control structure */
181 struct edac_device_block {
182 struct edac_device_instance *instance; /* Up Pointer */
183 char name[EDAC_DEVICE_NAME_LEN + 1];
184
185 struct edac_device_counter counters; /* basic UE and CE counters */
186
187 int nr_attribs; /* how many attributes */
188
189 /* this block's attributes, could be NULL */
190 struct edac_dev_sysfs_block_attribute *block_attributes;
191
192 /* edac sysfs device control */
193 struct kobject kobj;
194 };
195
196 /* device instance control structure */
197 struct edac_device_instance {
198 struct edac_device_ctl_info *ctl; /* Up pointer */
199 char name[EDAC_DEVICE_NAME_LEN + 4];
200
201 struct edac_device_counter counters; /* instance counters */
202
203 u32 nr_blocks; /* how many blocks */
204 struct edac_device_block *blocks; /* block array */
205
206 /* edac sysfs device control */
207 struct kobject kobj;
208 };
209
210
211 /*
212 * Abstract edac_device control info structure
213 *
214 */
215 struct edac_device_ctl_info {
216 /* for global list of edac_device_ctl_info structs */
217 struct list_head link;
218
219 struct module *owner; /* Module owner of this control struct */
220
221 int dev_idx;
222
223 /* Per instance controls for this edac_device */
224 int log_ue; /* boolean for logging UEs */
225 int log_ce; /* boolean for logging CEs */
226 int panic_on_ue; /* boolean for panic'ing on an UE */
227 unsigned poll_msec; /* number of milliseconds to poll interval */
228 unsigned long delay; /* number of jiffies for poll_msec */
229
230 /* Additional top controller level attributes, but specified
231 * by the low level driver.
232 *
233 * Set by the low level driver to provide attributes at the
234 * controller level, same level as 'ue_count' and 'ce_count' above.
235 * An array of structures, NULL terminated
236 *
237 * If attributes are desired, then set to array of attributes
238 * If no attributes are desired, leave NULL
239 */
240 struct edac_dev_sysfs_attribute *sysfs_attributes;
241
242 /* pointer to main 'edac' subsys in sysfs */
243 struct bus_type *edac_subsys;
244
245 /* the internal state of this controller instance */
246 int op_state;
247 /* work struct for this instance */
248 struct delayed_work work;
249
250 /* pointer to edac polling checking routine:
251 * If NOT NULL: points to polling check routine
252 * If NULL: Then assumes INTERRUPT operation, where
253 * MC driver will receive events
254 */
255 void (*edac_check) (struct edac_device_ctl_info * edac_dev);
256
257 struct device *dev; /* pointer to device structure */
258
259 const char *mod_name; /* module name */
260 const char *ctl_name; /* edac controller name */
261 const char *dev_name; /* pci/platform/etc... name */
262
263 void *pvt_info; /* pointer to 'private driver' info */
264
265 unsigned long start_time; /* edac_device load start time (jiffies) */
266
267 struct completion removal_complete;
268
269 /* sysfs top name under 'edac' directory
270 * and instance name:
271 * cpu/cpu0/...
272 * cpu/cpu1/...
273 * cpu/cpu2/...
274 * ...
275 */
276 char name[EDAC_DEVICE_NAME_LEN + 1];
277
278 /* Number of instances supported on this control structure
279 * and the array of those instances
280 */
281 u32 nr_instances;
282 struct edac_device_instance *instances;
283
284 /* Event counters for the this whole EDAC Device */
285 struct edac_device_counter counters;
286
287 /* edac sysfs device control for the 'name'
288 * device this structure controls
289 */
290 struct kobject kobj;
291 };
292
293 /* To get from the instance's wq to the beginning of the ctl structure */
294 #define to_edac_mem_ctl_work(w) \
295 container_of(w, struct mem_ctl_info, work)
296
297 #define to_edac_device_ctl_work(w) \
298 container_of(w,struct edac_device_ctl_info,work)
299
300 /*
301 * The alloc() and free() functions for the 'edac_device' control info
302 * structure. A MC driver will allocate one of these for each edac_device
303 * it is going to control/register with the EDAC CORE.
304 */
305 extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
306 unsigned sizeof_private,
307 char *edac_device_name, unsigned nr_instances,
308 char *edac_block_name, unsigned nr_blocks,
309 unsigned offset_value,
310 struct edac_dev_sysfs_block_attribute *block_attributes,
311 unsigned nr_attribs,
312 int device_index);
313
314 /* The offset value can be:
315 * -1 indicating no offset value
316 * 0 for zero-based block numbers
317 * 1 for 1-based block number
318 * other for other-based block number
319 */
320 #define BLOCK_OFFSET_VALUE_OFF ((unsigned) -1)
321
322 extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
323
324 #ifdef CONFIG_PCI
325
326 struct edac_pci_counter {
327 atomic_t pe_count;
328 atomic_t npe_count;
329 };
330
331 /*
332 * Abstract edac_pci control info structure
333 *
334 */
335 struct edac_pci_ctl_info {
336 /* for global list of edac_pci_ctl_info structs */
337 struct list_head link;
338
339 int pci_idx;
340
341 struct bus_type *edac_subsys; /* pointer to subsystem */
342
343 /* the internal state of this controller instance */
344 int op_state;
345 /* work struct for this instance */
346 struct delayed_work work;
347
348 /* pointer to edac polling checking routine:
349 * If NOT NULL: points to polling check routine
350 * If NULL: Then assumes INTERRUPT operation, where
351 * MC driver will receive events
352 */
353 void (*edac_check) (struct edac_pci_ctl_info * edac_dev);
354
355 struct device *dev; /* pointer to device structure */
356
357 const char *mod_name; /* module name */
358 const char *ctl_name; /* edac controller name */
359 const char *dev_name; /* pci/platform/etc... name */
360
361 void *pvt_info; /* pointer to 'private driver' info */
362
363 unsigned long start_time; /* edac_pci load start time (jiffies) */
364
365 struct completion complete;
366
367 /* sysfs top name under 'edac' directory
368 * and instance name:
369 * cpu/cpu0/...
370 * cpu/cpu1/...
371 * cpu/cpu2/...
372 * ...
373 */
374 char name[EDAC_DEVICE_NAME_LEN + 1];
375
376 /* Event counters for the this whole EDAC Device */
377 struct edac_pci_counter counters;
378
379 /* edac sysfs device control for the 'name'
380 * device this structure controls
381 */
382 struct kobject kobj;
383 struct completion kobj_complete;
384 };
385
386 #define to_edac_pci_ctl_work(w) \
387 container_of(w, struct edac_pci_ctl_info,work)
388
389 /* write all or some bits in a byte-register*/
pci_write_bits8(struct pci_dev * pdev,int offset,u8 value,u8 mask)390 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
391 u8 mask)
392 {
393 if (mask != 0xff) {
394 u8 buf;
395
396 pci_read_config_byte(pdev, offset, &buf);
397 value &= mask;
398 buf &= ~mask;
399 value |= buf;
400 }
401
402 pci_write_config_byte(pdev, offset, value);
403 }
404
405 /* write all or some bits in a word-register*/
pci_write_bits16(struct pci_dev * pdev,int offset,u16 value,u16 mask)406 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
407 u16 value, u16 mask)
408 {
409 if (mask != 0xffff) {
410 u16 buf;
411
412 pci_read_config_word(pdev, offset, &buf);
413 value &= mask;
414 buf &= ~mask;
415 value |= buf;
416 }
417
418 pci_write_config_word(pdev, offset, value);
419 }
420
421 /*
422 * pci_write_bits32
423 *
424 * edac local routine to do pci_write_config_dword, but adds
425 * a mask parameter. If mask is all ones, ignore the mask.
426 * Otherwise utilize the mask to isolate specified bits
427 *
428 * write all or some bits in a dword-register
429 */
pci_write_bits32(struct pci_dev * pdev,int offset,u32 value,u32 mask)430 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
431 u32 value, u32 mask)
432 {
433 if (mask != 0xffffffff) {
434 u32 buf;
435
436 pci_read_config_dword(pdev, offset, &buf);
437 value &= mask;
438 buf &= ~mask;
439 value |= buf;
440 }
441
442 pci_write_config_dword(pdev, offset, value);
443 }
444
445 #endif /* CONFIG_PCI */
446
447 struct mem_ctl_info *edac_mc_alloc(unsigned mc_num,
448 unsigned n_layers,
449 struct edac_mc_layer *layers,
450 unsigned sz_pvt);
451 extern int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci,
452 const struct attribute_group **groups);
453 #define edac_mc_add_mc(mci) edac_mc_add_mc_with_groups(mci, NULL)
454 extern void edac_mc_free(struct mem_ctl_info *mci);
455 extern struct mem_ctl_info *edac_mc_find(int idx);
456 extern struct mem_ctl_info *find_mci_by_dev(struct device *dev);
457 extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
458 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
459 unsigned long page);
460
461 void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type,
462 struct mem_ctl_info *mci,
463 struct edac_raw_error_desc *e);
464
465 void edac_mc_handle_error(const enum hw_event_mc_err_type type,
466 struct mem_ctl_info *mci,
467 const u16 error_count,
468 const unsigned long page_frame_number,
469 const unsigned long offset_in_page,
470 const unsigned long syndrome,
471 const int top_layer,
472 const int mid_layer,
473 const int low_layer,
474 const char *msg,
475 const char *other_detail);
476
477 /*
478 * edac_device APIs
479 */
480 extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
481 extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
482 extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
483 int inst_nr, int block_nr, const char *msg);
484 extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
485 int inst_nr, int block_nr, const char *msg);
486 extern int edac_device_alloc_index(void);
487 extern const char *edac_layer_name[];
488
489 /*
490 * edac_pci APIs
491 */
492 extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
493 const char *edac_pci_name);
494
495 extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
496
497 extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
498 unsigned long value);
499
500 extern int edac_pci_alloc_index(void);
501 extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
502 extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);
503
504 extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
505 struct device *dev,
506 const char *mod_name);
507
508 extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
509 extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
510 extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
511
512 /*
513 * edac misc APIs
514 */
515 extern char *edac_op_state_to_string(int op_state);
516
517 #endif /* _EDAC_CORE_H_ */
518