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1 /*
2  * PCI address cache; allows the lookup of PCI devices based on I/O address
3  *
4  * Copyright IBM Corporation 2004
5  * Copyright Linas Vepstas <linas@austin.ibm.com> 2004
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
20  */
21 
22 #include <linux/list.h>
23 #include <linux/pci.h>
24 #include <linux/rbtree.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/atomic.h>
28 #include <asm/pci-bridge.h>
29 #include <asm/ppc-pci.h>
30 
31 
32 /**
33  * The pci address cache subsystem.  This subsystem places
34  * PCI device address resources into a red-black tree, sorted
35  * according to the address range, so that given only an i/o
36  * address, the corresponding PCI device can be **quickly**
37  * found. It is safe to perform an address lookup in an interrupt
38  * context; this ability is an important feature.
39  *
40  * Currently, the only customer of this code is the EEH subsystem;
41  * thus, this code has been somewhat tailored to suit EEH better.
42  * In particular, the cache does *not* hold the addresses of devices
43  * for which EEH is not enabled.
44  *
45  * (Implementation Note: The RB tree seems to be better/faster
46  * than any hash algo I could think of for this problem, even
47  * with the penalty of slow pointer chases for d-cache misses).
48  */
49 struct pci_io_addr_range {
50 	struct rb_node rb_node;
51 	resource_size_t addr_lo;
52 	resource_size_t addr_hi;
53 	struct eeh_dev *edev;
54 	struct pci_dev *pcidev;
55 	unsigned long flags;
56 };
57 
58 static struct pci_io_addr_cache {
59 	struct rb_root rb_root;
60 	spinlock_t piar_lock;
61 } pci_io_addr_cache_root;
62 
__eeh_addr_cache_get_device(unsigned long addr)63 static inline struct eeh_dev *__eeh_addr_cache_get_device(unsigned long addr)
64 {
65 	struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node;
66 
67 	while (n) {
68 		struct pci_io_addr_range *piar;
69 		piar = rb_entry(n, struct pci_io_addr_range, rb_node);
70 
71 		if (addr < piar->addr_lo)
72 			n = n->rb_left;
73 		else if (addr > piar->addr_hi)
74 			n = n->rb_right;
75 		else
76 			return piar->edev;
77 	}
78 
79 	return NULL;
80 }
81 
82 /**
83  * eeh_addr_cache_get_dev - Get device, given only address
84  * @addr: mmio (PIO) phys address or i/o port number
85  *
86  * Given an mmio phys address, or a port number, find a pci device
87  * that implements this address.  Be sure to pci_dev_put the device
88  * when finished.  I/O port numbers are assumed to be offset
89  * from zero (that is, they do *not* have pci_io_addr added in).
90  * It is safe to call this function within an interrupt.
91  */
eeh_addr_cache_get_dev(unsigned long addr)92 struct eeh_dev *eeh_addr_cache_get_dev(unsigned long addr)
93 {
94 	struct eeh_dev *edev;
95 	unsigned long flags;
96 
97 	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
98 	edev = __eeh_addr_cache_get_device(addr);
99 	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
100 	return edev;
101 }
102 
103 #ifdef DEBUG
104 /*
105  * Handy-dandy debug print routine, does nothing more
106  * than print out the contents of our addr cache.
107  */
eeh_addr_cache_print(struct pci_io_addr_cache * cache)108 static void eeh_addr_cache_print(struct pci_io_addr_cache *cache)
109 {
110 	struct rb_node *n;
111 	int cnt = 0;
112 
113 	n = rb_first(&cache->rb_root);
114 	while (n) {
115 		struct pci_io_addr_range *piar;
116 		piar = rb_entry(n, struct pci_io_addr_range, rb_node);
117 		pr_debug("PCI: %s addr range %d [%lx-%lx]: %s\n",
118 		       (piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt,
119 		       piar->addr_lo, piar->addr_hi, pci_name(piar->pcidev));
120 		cnt++;
121 		n = rb_next(n);
122 	}
123 }
124 #endif
125 
126 /* Insert address range into the rb tree. */
127 static struct pci_io_addr_range *
eeh_addr_cache_insert(struct pci_dev * dev,resource_size_t alo,resource_size_t ahi,unsigned long flags)128 eeh_addr_cache_insert(struct pci_dev *dev, resource_size_t alo,
129 		      resource_size_t ahi, unsigned long flags)
130 {
131 	struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node;
132 	struct rb_node *parent = NULL;
133 	struct pci_io_addr_range *piar;
134 
135 	/* Walk tree, find a place to insert into tree */
136 	while (*p) {
137 		parent = *p;
138 		piar = rb_entry(parent, struct pci_io_addr_range, rb_node);
139 		if (ahi < piar->addr_lo) {
140 			p = &parent->rb_left;
141 		} else if (alo > piar->addr_hi) {
142 			p = &parent->rb_right;
143 		} else {
144 			if (dev != piar->pcidev ||
145 			    alo != piar->addr_lo || ahi != piar->addr_hi) {
146 				pr_warn("PIAR: overlapping address range\n");
147 			}
148 			return piar;
149 		}
150 	}
151 	piar = kzalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC);
152 	if (!piar)
153 		return NULL;
154 
155 	piar->addr_lo = alo;
156 	piar->addr_hi = ahi;
157 	piar->edev = pci_dev_to_eeh_dev(dev);
158 	piar->pcidev = dev;
159 	piar->flags = flags;
160 
161 #ifdef DEBUG
162 	pr_debug("PIAR: insert range=[%lx:%lx] dev=%s\n",
163 	                  alo, ahi, pci_name(dev));
164 #endif
165 
166 	rb_link_node(&piar->rb_node, parent, p);
167 	rb_insert_color(&piar->rb_node, &pci_io_addr_cache_root.rb_root);
168 
169 	return piar;
170 }
171 
__eeh_addr_cache_insert_dev(struct pci_dev * dev)172 static void __eeh_addr_cache_insert_dev(struct pci_dev *dev)
173 {
174 	struct pci_dn *pdn;
175 	struct eeh_dev *edev;
176 	int i;
177 
178 	pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
179 	if (!pdn) {
180 		pr_warn("PCI: no pci dn found for dev=%s\n",
181 			pci_name(dev));
182 		return;
183 	}
184 
185 	edev = pdn_to_eeh_dev(pdn);
186 	if (!edev) {
187 		pr_warn("PCI: no EEH dev found for %s\n",
188 			pci_name(dev));
189 		return;
190 	}
191 
192 	/* Skip any devices for which EEH is not enabled. */
193 	if (!edev->pe) {
194 		dev_dbg(&dev->dev, "EEH: Skip building address cache\n");
195 		return;
196 	}
197 
198 	/* Walk resources on this device, poke them into the tree */
199 	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
200 		resource_size_t start = pci_resource_start(dev,i);
201 		resource_size_t end = pci_resource_end(dev,i);
202 		unsigned long flags = pci_resource_flags(dev,i);
203 
204 		/* We are interested only bus addresses, not dma or other stuff */
205 		if (0 == (flags & (IORESOURCE_IO | IORESOURCE_MEM)))
206 			continue;
207 		if (start == 0 || ~start == 0 || end == 0 || ~end == 0)
208 			 continue;
209 		eeh_addr_cache_insert(dev, start, end, flags);
210 	}
211 }
212 
213 /**
214  * eeh_addr_cache_insert_dev - Add a device to the address cache
215  * @dev: PCI device whose I/O addresses we are interested in.
216  *
217  * In order to support the fast lookup of devices based on addresses,
218  * we maintain a cache of devices that can be quickly searched.
219  * This routine adds a device to that cache.
220  */
eeh_addr_cache_insert_dev(struct pci_dev * dev)221 void eeh_addr_cache_insert_dev(struct pci_dev *dev)
222 {
223 	unsigned long flags;
224 
225 	/* Ignore PCI bridges */
226 	if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
227 		return;
228 
229 	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
230 	__eeh_addr_cache_insert_dev(dev);
231 	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
232 }
233 
__eeh_addr_cache_rmv_dev(struct pci_dev * dev)234 static inline void __eeh_addr_cache_rmv_dev(struct pci_dev *dev)
235 {
236 	struct rb_node *n;
237 
238 restart:
239 	n = rb_first(&pci_io_addr_cache_root.rb_root);
240 	while (n) {
241 		struct pci_io_addr_range *piar;
242 		piar = rb_entry(n, struct pci_io_addr_range, rb_node);
243 
244 		if (piar->pcidev == dev) {
245 			rb_erase(n, &pci_io_addr_cache_root.rb_root);
246 			kfree(piar);
247 			goto restart;
248 		}
249 		n = rb_next(n);
250 	}
251 }
252 
253 /**
254  * eeh_addr_cache_rmv_dev - remove pci device from addr cache
255  * @dev: device to remove
256  *
257  * Remove a device from the addr-cache tree.
258  * This is potentially expensive, since it will walk
259  * the tree multiple times (once per resource).
260  * But so what; device removal doesn't need to be that fast.
261  */
eeh_addr_cache_rmv_dev(struct pci_dev * dev)262 void eeh_addr_cache_rmv_dev(struct pci_dev *dev)
263 {
264 	unsigned long flags;
265 
266 	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
267 	__eeh_addr_cache_rmv_dev(dev);
268 	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
269 }
270 
271 /**
272  * eeh_addr_cache_build - Build a cache of I/O addresses
273  *
274  * Build a cache of pci i/o addresses.  This cache will be used to
275  * find the pci device that corresponds to a given address.
276  * This routine scans all pci busses to build the cache.
277  * Must be run late in boot process, after the pci controllers
278  * have been scanned for devices (after all device resources are known).
279  */
eeh_addr_cache_build(void)280 void eeh_addr_cache_build(void)
281 {
282 	struct pci_dn *pdn;
283 	struct eeh_dev *edev;
284 	struct pci_dev *dev = NULL;
285 
286 	spin_lock_init(&pci_io_addr_cache_root.piar_lock);
287 
288 	for_each_pci_dev(dev) {
289 		pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
290 		if (!pdn)
291 			continue;
292 
293 		edev = pdn_to_eeh_dev(pdn);
294 		if (!edev)
295 			continue;
296 
297 		dev->dev.archdata.edev = edev;
298 		edev->pdev = dev;
299 
300 		eeh_addr_cache_insert_dev(dev);
301 		eeh_sysfs_add_device(dev);
302 	}
303 
304 #ifdef DEBUG
305 	/* Verify tree built up above, echo back the list of addrs. */
306 	eeh_addr_cache_print(&pci_io_addr_cache_root);
307 #endif
308 }
309