1 /*
2 * ci.h - common structures, functions, and macros of the ChipIdea driver
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
14 #define __DRIVERS_USB_CHIPIDEA_CI_H
15
16 #include <linux/list.h>
17 #include <linux/irqreturn.h>
18 #include <linux/usb.h>
19 #include <linux/usb/gadget.h>
20 #include <linux/usb/otg-fsm.h>
21
22 /******************************************************************************
23 * DEFINE
24 *****************************************************************************/
25 #define TD_PAGE_COUNT 5
26 #define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */
27 #define ENDPT_MAX 32
28
29 /******************************************************************************
30 * REGISTERS
31 *****************************************************************************/
32 /* Identification Registers */
33 #define ID_ID 0x0
34 #define ID_HWGENERAL 0x4
35 #define ID_HWHOST 0x8
36 #define ID_HWDEVICE 0xc
37 #define ID_HWTXBUF 0x10
38 #define ID_HWRXBUF 0x14
39 #define ID_SBUSCFG 0x90
40
41 /* register indices */
42 enum ci_hw_regs {
43 CAP_CAPLENGTH,
44 CAP_HCCPARAMS,
45 CAP_DCCPARAMS,
46 CAP_TESTMODE,
47 CAP_LAST = CAP_TESTMODE,
48 OP_USBCMD,
49 OP_USBSTS,
50 OP_USBINTR,
51 OP_DEVICEADDR,
52 OP_ENDPTLISTADDR,
53 OP_TTCTRL,
54 OP_BURSTSIZE,
55 OP_PORTSC,
56 OP_DEVLC,
57 OP_OTGSC,
58 OP_USBMODE,
59 OP_ENDPTSETUPSTAT,
60 OP_ENDPTPRIME,
61 OP_ENDPTFLUSH,
62 OP_ENDPTSTAT,
63 OP_ENDPTCOMPLETE,
64 OP_ENDPTCTRL,
65 /* endptctrl1..15 follow */
66 OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
67 };
68
69 /******************************************************************************
70 * STRUCTURES
71 *****************************************************************************/
72 /**
73 * struct ci_hw_ep - endpoint representation
74 * @ep: endpoint structure for gadget drivers
75 * @dir: endpoint direction (TX/RX)
76 * @num: endpoint number
77 * @type: endpoint type
78 * @name: string description of the endpoint
79 * @qh: queue head for this endpoint
80 * @wedge: is the endpoint wedged
81 * @ci: pointer to the controller
82 * @lock: pointer to controller's spinlock
83 * @td_pool: pointer to controller's TD pool
84 */
85 struct ci_hw_ep {
86 struct usb_ep ep;
87 u8 dir;
88 u8 num;
89 u8 type;
90 char name[16];
91 struct {
92 struct list_head queue;
93 struct ci_hw_qh *ptr;
94 dma_addr_t dma;
95 } qh;
96 int wedge;
97
98 /* global resources */
99 struct ci_hdrc *ci;
100 spinlock_t *lock;
101 struct dma_pool *td_pool;
102 struct td_node *pending_td;
103 };
104
105 enum ci_role {
106 CI_ROLE_HOST = 0,
107 CI_ROLE_GADGET,
108 CI_ROLE_END,
109 };
110
111 enum ci_revision {
112 CI_REVISION_1X = 10, /* Revision 1.x */
113 CI_REVISION_20 = 20, /* Revision 2.0 */
114 CI_REVISION_21, /* Revision 2.1 */
115 CI_REVISION_22, /* Revision 2.2 */
116 CI_REVISION_23, /* Revision 2.3 */
117 CI_REVISION_24, /* Revision 2.4 */
118 CI_REVISION_25, /* Revision 2.5 */
119 CI_REVISION_25_PLUS, /* Revision above than 2.5 */
120 CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
121 };
122
123 /**
124 * struct ci_role_driver - host/gadget role driver
125 * @start: start this role
126 * @stop: stop this role
127 * @irq: irq handler for this role
128 * @name: role name string (host/gadget)
129 */
130 struct ci_role_driver {
131 int (*start)(struct ci_hdrc *);
132 void (*stop)(struct ci_hdrc *);
133 irqreturn_t (*irq)(struct ci_hdrc *);
134 const char *name;
135 };
136
137 /**
138 * struct hw_bank - hardware register mapping representation
139 * @lpm: set if the device is LPM capable
140 * @phys: physical address of the controller's registers
141 * @abs: absolute address of the beginning of register window
142 * @cap: capability registers
143 * @op: operational registers
144 * @size: size of the register window
145 * @regmap: register lookup table
146 */
147 struct hw_bank {
148 unsigned lpm;
149 resource_size_t phys;
150 void __iomem *abs;
151 void __iomem *cap;
152 void __iomem *op;
153 size_t size;
154 void __iomem *regmap[OP_LAST + 1];
155 };
156
157 /**
158 * struct ci_hdrc - chipidea device representation
159 * @dev: pointer to parent device
160 * @lock: access synchronization
161 * @hw_bank: hardware register mapping
162 * @irq: IRQ number
163 * @roles: array of supported roles for this controller
164 * @role: current role
165 * @is_otg: if the device is otg-capable
166 * @fsm: otg finite state machine
167 * @otg_fsm_hrtimer: hrtimer for otg fsm timers
168 * @hr_timeouts: time out list for active otg fsm timers
169 * @enabled_otg_timer_bits: bits of enabled otg timers
170 * @next_otg_timer: next nearest enabled timer to be expired
171 * @work: work for role changing
172 * @wq: workqueue thread
173 * @qh_pool: allocation pool for queue heads
174 * @td_pool: allocation pool for transfer descriptors
175 * @gadget: device side representation for peripheral controller
176 * @driver: gadget driver
177 * @hw_ep_max: total number of endpoints supported by hardware
178 * @ci_hw_ep: array of endpoints
179 * @ep0_dir: ep0 direction
180 * @ep0out: pointer to ep0 OUT endpoint
181 * @ep0in: pointer to ep0 IN endpoint
182 * @status: ep0 status request
183 * @setaddr: if we should set the address on status completion
184 * @address: usb address received from the host
185 * @remote_wakeup: host-enabled remote wakeup
186 * @suspended: suspended by host
187 * @test_mode: the selected test mode
188 * @platdata: platform specific information supplied by parent device
189 * @vbus_active: is VBUS active
190 * @phy: pointer to PHY, if any
191 * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
192 * @hcd: pointer to usb_hcd for ehci host driver
193 * @debugfs: root dentry for this controller in debugfs
194 * @id_event: indicates there is an id event, and handled at ci_otg_work
195 * @b_sess_valid_event: indicates there is a vbus event, and handled
196 * at ci_otg_work
197 * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
198 * @supports_runtime_pm: if runtime pm is supported
199 * @in_lpm: if the core in low power mode
200 * @wakeup_int: if wakeup interrupt occur
201 * @rev: The revision number for controller
202 */
203 struct ci_hdrc {
204 struct device *dev;
205 spinlock_t lock;
206 struct hw_bank hw_bank;
207 int irq;
208 struct ci_role_driver *roles[CI_ROLE_END];
209 enum ci_role role;
210 bool is_otg;
211 struct usb_otg otg;
212 struct otg_fsm fsm;
213 struct hrtimer otg_fsm_hrtimer;
214 ktime_t hr_timeouts[NUM_OTG_FSM_TIMERS];
215 unsigned enabled_otg_timer_bits;
216 enum otg_fsm_timer next_otg_timer;
217 struct work_struct work;
218 struct workqueue_struct *wq;
219
220 struct dma_pool *qh_pool;
221 struct dma_pool *td_pool;
222
223 struct usb_gadget gadget;
224 struct usb_gadget_driver *driver;
225 unsigned hw_ep_max;
226 struct ci_hw_ep ci_hw_ep[ENDPT_MAX];
227 u32 ep0_dir;
228 struct ci_hw_ep *ep0out, *ep0in;
229
230 struct usb_request *status;
231 bool setaddr;
232 u8 address;
233 u8 remote_wakeup;
234 u8 suspended;
235 u8 test_mode;
236
237 struct ci_hdrc_platform_data *platdata;
238 int vbus_active;
239 struct phy *phy;
240 /* old usb_phy interface */
241 struct usb_phy *usb_phy;
242 struct usb_hcd *hcd;
243 struct dentry *debugfs;
244 bool id_event;
245 bool b_sess_valid_event;
246 bool imx28_write_fix;
247 bool supports_runtime_pm;
248 bool in_lpm;
249 bool wakeup_int;
250 enum ci_revision rev;
251 };
252
ci_role(struct ci_hdrc * ci)253 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
254 {
255 BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
256 return ci->roles[ci->role];
257 }
258
ci_role_start(struct ci_hdrc * ci,enum ci_role role)259 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
260 {
261 int ret;
262
263 if (role >= CI_ROLE_END)
264 return -EINVAL;
265
266 if (!ci->roles[role])
267 return -ENXIO;
268
269 ret = ci->roles[role]->start(ci);
270 if (!ret)
271 ci->role = role;
272 return ret;
273 }
274
ci_role_stop(struct ci_hdrc * ci)275 static inline void ci_role_stop(struct ci_hdrc *ci)
276 {
277 enum ci_role role = ci->role;
278
279 if (role == CI_ROLE_END)
280 return;
281
282 ci->role = CI_ROLE_END;
283
284 ci->roles[role]->stop(ci);
285 }
286
287 /**
288 * hw_read_id_reg: reads from a identification register
289 * @ci: the controller
290 * @offset: offset from the beginning of identification registers region
291 * @mask: bitfield mask
292 *
293 * This function returns register contents
294 */
hw_read_id_reg(struct ci_hdrc * ci,u32 offset,u32 mask)295 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
296 {
297 return ioread32(ci->hw_bank.abs + offset) & mask;
298 }
299
300 /**
301 * hw_write_id_reg: writes to a identification register
302 * @ci: the controller
303 * @offset: offset from the beginning of identification registers region
304 * @mask: bitfield mask
305 * @data: new value
306 */
hw_write_id_reg(struct ci_hdrc * ci,u32 offset,u32 mask,u32 data)307 static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
308 u32 mask, u32 data)
309 {
310 if (~mask)
311 data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
312 | (data & mask);
313
314 iowrite32(data, ci->hw_bank.abs + offset);
315 }
316
317 /**
318 * hw_read: reads from a hw register
319 * @ci: the controller
320 * @reg: register index
321 * @mask: bitfield mask
322 *
323 * This function returns register contents
324 */
hw_read(struct ci_hdrc * ci,enum ci_hw_regs reg,u32 mask)325 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
326 {
327 return ioread32(ci->hw_bank.regmap[reg]) & mask;
328 }
329
330 #ifdef CONFIG_SOC_IMX28
imx28_ci_writel(u32 val,volatile void __iomem * addr)331 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
332 {
333 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
334 }
335 #else
imx28_ci_writel(u32 val,volatile void __iomem * addr)336 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
337 {
338 }
339 #endif
340
__hw_write(struct ci_hdrc * ci,u32 val,void __iomem * addr)341 static inline void __hw_write(struct ci_hdrc *ci, u32 val,
342 void __iomem *addr)
343 {
344 if (ci->imx28_write_fix)
345 imx28_ci_writel(val, addr);
346 else
347 iowrite32(val, addr);
348 }
349
350 /**
351 * hw_write: writes to a hw register
352 * @ci: the controller
353 * @reg: register index
354 * @mask: bitfield mask
355 * @data: new value
356 */
hw_write(struct ci_hdrc * ci,enum ci_hw_regs reg,u32 mask,u32 data)357 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
358 u32 mask, u32 data)
359 {
360 if (~mask)
361 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
362 | (data & mask);
363
364 __hw_write(ci, data, ci->hw_bank.regmap[reg]);
365 }
366
367 /**
368 * hw_test_and_clear: tests & clears a hw register
369 * @ci: the controller
370 * @reg: register index
371 * @mask: bitfield mask
372 *
373 * This function returns register contents
374 */
hw_test_and_clear(struct ci_hdrc * ci,enum ci_hw_regs reg,u32 mask)375 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
376 u32 mask)
377 {
378 u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
379
380 __hw_write(ci, val, ci->hw_bank.regmap[reg]);
381 return val;
382 }
383
384 /**
385 * hw_test_and_write: tests & writes a hw register
386 * @ci: the controller
387 * @reg: register index
388 * @mask: bitfield mask
389 * @data: new value
390 *
391 * This function returns register contents
392 */
hw_test_and_write(struct ci_hdrc * ci,enum ci_hw_regs reg,u32 mask,u32 data)393 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
394 u32 mask, u32 data)
395 {
396 u32 val = hw_read(ci, reg, ~0);
397
398 hw_write(ci, reg, mask, data);
399 return (val & mask) >> __ffs(mask);
400 }
401
402 /**
403 * ci_otg_is_fsm_mode: runtime check if otg controller
404 * is in otg fsm mode.
405 *
406 * @ci: chipidea device
407 */
ci_otg_is_fsm_mode(struct ci_hdrc * ci)408 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
409 {
410 #ifdef CONFIG_USB_OTG_FSM
411 struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
412
413 return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
414 ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||
415 otg_caps->hnp_support || otg_caps->adp_support);
416 #else
417 return false;
418 #endif
419 }
420
421 u32 hw_read_intr_enable(struct ci_hdrc *ci);
422
423 u32 hw_read_intr_status(struct ci_hdrc *ci);
424
425 int hw_device_reset(struct ci_hdrc *ci);
426
427 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
428
429 u8 hw_port_test_get(struct ci_hdrc *ci);
430
431 void ci_platform_configure(struct ci_hdrc *ci);
432
433 #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */
434