1 /* 2 * omap3isp.h 3 * 4 * TI OMAP3 ISP - Bus Configuration 5 * 6 * Copyright (C) 2011 Nokia Corporation 7 * 8 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 9 * Sakari Ailus <sakari.ailus@iki.fi> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 */ 20 21 #ifndef __OMAP3ISP_H__ 22 #define __OMAP3ISP_H__ 23 24 enum isp_interface_type { 25 ISP_INTERFACE_PARALLEL, 26 ISP_INTERFACE_CSI2A_PHY2, 27 ISP_INTERFACE_CCP2B_PHY1, 28 ISP_INTERFACE_CCP2B_PHY2, 29 ISP_INTERFACE_CSI2C_PHY1, 30 }; 31 32 /** 33 * struct isp_parallel_cfg - Parallel interface configuration 34 * @data_lane_shift: Data lane shifter 35 * 0 - CAMEXT[13:0] -> CAM[13:0] 36 * 1 - CAMEXT[13:2] -> CAM[11:0] 37 * 2 - CAMEXT[13:4] -> CAM[9:0] 38 * 3 - CAMEXT[13:6] -> CAM[7:0] 39 * @clk_pol: Pixel clock polarity 40 * 0 - Sample on rising edge, 1 - Sample on falling edge 41 * @hs_pol: Horizontal synchronization polarity 42 * 0 - Active high, 1 - Active low 43 * @vs_pol: Vertical synchronization polarity 44 * 0 - Active high, 1 - Active low 45 * @fld_pol: Field signal polarity 46 * 0 - Positive, 1 - Negative 47 * @data_pol: Data polarity 48 * 0 - Normal, 1 - One's complement 49 */ 50 struct isp_parallel_cfg { 51 unsigned int data_lane_shift:2; 52 unsigned int clk_pol:1; 53 unsigned int hs_pol:1; 54 unsigned int vs_pol:1; 55 unsigned int fld_pol:1; 56 unsigned int data_pol:1; 57 }; 58 59 enum { 60 ISP_CCP2_PHY_DATA_CLOCK = 0, 61 ISP_CCP2_PHY_DATA_STROBE = 1, 62 }; 63 64 enum { 65 ISP_CCP2_MODE_MIPI = 0, 66 ISP_CCP2_MODE_CCP2 = 1, 67 }; 68 69 /** 70 * struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity 71 * @pos: position of the lane 72 * @pol: polarity of the lane 73 */ 74 struct isp_csiphy_lane { 75 u8 pos; 76 u8 pol; 77 }; 78 79 #define ISP_CSIPHY1_NUM_DATA_LANES 1 80 #define ISP_CSIPHY2_NUM_DATA_LANES 2 81 82 /** 83 * struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration 84 * @data: Configuration of one or two data lanes 85 * @clk: Clock lane configuration 86 */ 87 struct isp_csiphy_lanes_cfg { 88 struct isp_csiphy_lane data[ISP_CSIPHY2_NUM_DATA_LANES]; 89 struct isp_csiphy_lane clk; 90 }; 91 92 /** 93 * struct isp_ccp2_cfg - CCP2 interface configuration 94 * @strobe_clk_pol: Strobe/clock polarity 95 * 0 - Non Inverted, 1 - Inverted 96 * @crc: Enable the cyclic redundancy check 97 * @ccp2_mode: Enable CCP2 compatibility mode 98 * ISP_CCP2_MODE_MIPI - MIPI-CSI1 mode 99 * ISP_CCP2_MODE_CCP2 - CCP2 mode 100 * @phy_layer: Physical layer selection 101 * ISP_CCP2_PHY_DATA_CLOCK - Data/clock physical layer 102 * ISP_CCP2_PHY_DATA_STROBE - Data/strobe physical layer 103 * @vpclk_div: Video port output clock control 104 */ 105 struct isp_ccp2_cfg { 106 unsigned int strobe_clk_pol:1; 107 unsigned int crc:1; 108 unsigned int ccp2_mode:1; 109 unsigned int phy_layer:1; 110 unsigned int vpclk_div:2; 111 struct isp_csiphy_lanes_cfg lanecfg; 112 }; 113 114 /** 115 * struct isp_csi2_cfg - CSI2 interface configuration 116 * @crc: Enable the cyclic redundancy check 117 */ 118 struct isp_csi2_cfg { 119 unsigned crc:1; 120 struct isp_csiphy_lanes_cfg lanecfg; 121 }; 122 123 struct isp_bus_cfg { 124 enum isp_interface_type interface; 125 union { 126 struct isp_parallel_cfg parallel; 127 struct isp_ccp2_cfg ccp2; 128 struct isp_csi2_cfg csi2; 129 } bus; /* gcc < 4.6.0 chokes on anonymous union initializers */ 130 }; 131 132 #endif /* __OMAP3ISP_H__ */ 133