1 /*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24 #include "gf100.h"
25 #include "ctxgf100.h"
26
27 #include <subdev/bios.h>
28 #include <subdev/bios/P0260.h>
29
30 #include <nvif/class.h>
31
32 /*******************************************************************************
33 * PGRAPH register lists
34 ******************************************************************************/
35
36 static const struct gf100_gr_init
37 gm107_gr_init_main_0[] = {
38 { 0x400080, 1, 0x04, 0x003003c2 },
39 { 0x400088, 1, 0x04, 0x0001bfe7 },
40 { 0x40008c, 1, 0x04, 0x00060000 },
41 { 0x400090, 1, 0x04, 0x00000030 },
42 { 0x40013c, 1, 0x04, 0x003901f3 },
43 { 0x400140, 1, 0x04, 0x00000100 },
44 { 0x400144, 1, 0x04, 0x00000000 },
45 { 0x400148, 1, 0x04, 0x00000110 },
46 { 0x400138, 1, 0x04, 0x00000000 },
47 { 0x400130, 2, 0x04, 0x00000000 },
48 { 0x400124, 1, 0x04, 0x00000002 },
49 {}
50 };
51
52 static const struct gf100_gr_init
53 gm107_gr_init_ds_0[] = {
54 { 0x405844, 1, 0x04, 0x00ffffff },
55 { 0x405850, 1, 0x04, 0x00000000 },
56 { 0x405900, 1, 0x04, 0x00000000 },
57 { 0x405908, 1, 0x04, 0x00000000 },
58 {}
59 };
60
61 const struct gf100_gr_init
62 gm107_gr_init_scc_0[] = {
63 { 0x40803c, 1, 0x04, 0x00000010 },
64 {}
65 };
66
67 static const struct gf100_gr_init
68 gm107_gr_init_sked_0[] = {
69 { 0x407010, 1, 0x04, 0x00000000 },
70 { 0x407040, 1, 0x04, 0x40440424 },
71 { 0x407048, 1, 0x04, 0x0000000a },
72 {}
73 };
74
75 const struct gf100_gr_init
76 gm107_gr_init_prop_0[] = {
77 { 0x418408, 1, 0x04, 0x00000000 },
78 { 0x4184a0, 1, 0x04, 0x00000000 },
79 {}
80 };
81
82 const struct gf100_gr_init
83 gm107_gr_init_setup_1[] = {
84 { 0x4188c8, 2, 0x04, 0x00000000 },
85 { 0x4188d0, 1, 0x04, 0x00010000 },
86 { 0x4188d4, 1, 0x04, 0x00010201 },
87 {}
88 };
89
90 const struct gf100_gr_init
91 gm107_gr_init_zcull_0[] = {
92 { 0x418910, 1, 0x04, 0x00010001 },
93 { 0x418914, 1, 0x04, 0x00000301 },
94 { 0x418918, 1, 0x04, 0x00800000 },
95 { 0x418930, 2, 0x04, 0x00000000 },
96 { 0x418980, 1, 0x04, 0x77777770 },
97 { 0x418984, 3, 0x04, 0x77777777 },
98 {}
99 };
100
101 const struct gf100_gr_init
102 gm107_gr_init_gpc_unk_1[] = {
103 { 0x418d00, 1, 0x04, 0x00000000 },
104 { 0x418f00, 1, 0x04, 0x00000400 },
105 { 0x418f08, 1, 0x04, 0x00000000 },
106 { 0x418e08, 1, 0x04, 0x00000000 },
107 {}
108 };
109
110 static const struct gf100_gr_init
111 gm107_gr_init_tpccs_0[] = {
112 { 0x419dc4, 1, 0x04, 0x00000000 },
113 { 0x419dc8, 1, 0x04, 0x00000501 },
114 { 0x419dd0, 1, 0x04, 0x00000000 },
115 { 0x419dd4, 1, 0x04, 0x00000100 },
116 { 0x419dd8, 1, 0x04, 0x00000001 },
117 { 0x419ddc, 1, 0x04, 0x00000002 },
118 { 0x419de0, 1, 0x04, 0x00000001 },
119 { 0x419d0c, 1, 0x04, 0x00000000 },
120 { 0x419d10, 1, 0x04, 0x00000014 },
121 {}
122 };
123
124 const struct gf100_gr_init
125 gm107_gr_init_tex_0[] = {
126 { 0x419ab0, 1, 0x04, 0x00000000 },
127 { 0x419ab8, 1, 0x04, 0x000000e7 },
128 { 0x419abc, 1, 0x04, 0x00000000 },
129 { 0x419acc, 1, 0x04, 0x000000ff },
130 { 0x419ac0, 1, 0x04, 0x00000000 },
131 { 0x419aa8, 2, 0x04, 0x00000000 },
132 { 0x419ad0, 2, 0x04, 0x00000000 },
133 { 0x419ae0, 2, 0x04, 0x00000000 },
134 { 0x419af0, 4, 0x04, 0x00000000 },
135 {}
136 };
137
138 static const struct gf100_gr_init
139 gm107_gr_init_pe_0[] = {
140 { 0x419900, 1, 0x04, 0x000000ff },
141 { 0x41980c, 1, 0x04, 0x00000010 },
142 { 0x419844, 1, 0x04, 0x00000000 },
143 { 0x419838, 1, 0x04, 0x000000ff },
144 { 0x419850, 1, 0x04, 0x00000004 },
145 { 0x419854, 2, 0x04, 0x00000000 },
146 { 0x419894, 3, 0x04, 0x00100401 },
147 {}
148 };
149
150 const struct gf100_gr_init
151 gm107_gr_init_l1c_0[] = {
152 { 0x419c98, 1, 0x04, 0x00000000 },
153 { 0x419cc0, 2, 0x04, 0x00000000 },
154 {}
155 };
156
157 static const struct gf100_gr_init
158 gm107_gr_init_sm_0[] = {
159 { 0x419e30, 1, 0x04, 0x000000ff },
160 { 0x419e00, 1, 0x04, 0x00000000 },
161 { 0x419ea0, 1, 0x04, 0x00000000 },
162 { 0x419ee4, 1, 0x04, 0x00000000 },
163 { 0x419ea4, 1, 0x04, 0x00000100 },
164 { 0x419ea8, 1, 0x04, 0x01000000 },
165 { 0x419ee8, 1, 0x04, 0x00000091 },
166 { 0x419eb4, 1, 0x04, 0x00000000 },
167 { 0x419ebc, 2, 0x04, 0x00000000 },
168 { 0x419edc, 1, 0x04, 0x000c1810 },
169 { 0x419ed8, 1, 0x04, 0x00000000 },
170 { 0x419ee0, 1, 0x04, 0x00000000 },
171 { 0x419f74, 1, 0x04, 0x00005155 },
172 { 0x419f80, 4, 0x04, 0x00000000 },
173 {}
174 };
175
176 static const struct gf100_gr_init
177 gm107_gr_init_l1c_1[] = {
178 { 0x419ccc, 2, 0x04, 0x00000000 },
179 { 0x419c80, 1, 0x04, 0x3f006022 },
180 { 0x419c88, 1, 0x04, 0x00000000 },
181 {}
182 };
183
184 static const struct gf100_gr_init
185 gm107_gr_init_pes_0[] = {
186 { 0x41be50, 1, 0x04, 0x000000ff },
187 { 0x41be04, 1, 0x04, 0x00000000 },
188 { 0x41be08, 1, 0x04, 0x00000004 },
189 { 0x41be0c, 1, 0x04, 0x00000008 },
190 { 0x41be10, 1, 0x04, 0x0e3b8bc7 },
191 { 0x41be14, 2, 0x04, 0x00000000 },
192 { 0x41be3c, 5, 0x04, 0x00100401 },
193 {}
194 };
195
196 const struct gf100_gr_init
197 gm107_gr_init_wwdx_0[] = {
198 { 0x41bfd4, 1, 0x04, 0x00800000 },
199 { 0x41bfdc, 1, 0x04, 0x00000000 },
200 {}
201 };
202
203 const struct gf100_gr_init
204 gm107_gr_init_cbm_0[] = {
205 { 0x41becc, 1, 0x04, 0x00000000 },
206 {}
207 };
208
209 static const struct gf100_gr_init
210 gm107_gr_init_be_0[] = {
211 { 0x408890, 1, 0x04, 0x000000ff },
212 { 0x40880c, 1, 0x04, 0x00000000 },
213 { 0x408850, 1, 0x04, 0x00000004 },
214 { 0x408878, 1, 0x04, 0x00c81603 },
215 { 0x40887c, 1, 0x04, 0x80543432 },
216 { 0x408880, 1, 0x04, 0x0010581e },
217 { 0x408884, 1, 0x04, 0x00001205 },
218 { 0x408974, 1, 0x04, 0x000000ff },
219 { 0x408910, 9, 0x04, 0x00000000 },
220 { 0x408950, 1, 0x04, 0x00000000 },
221 { 0x408954, 1, 0x04, 0x0000ffff },
222 { 0x408958, 1, 0x04, 0x00000034 },
223 { 0x40895c, 1, 0x04, 0x8531a003 },
224 { 0x408960, 1, 0x04, 0x0561985a },
225 { 0x408964, 1, 0x04, 0x04e15c4f },
226 { 0x408968, 1, 0x04, 0x02808833 },
227 { 0x40896c, 1, 0x04, 0x01f02438 },
228 { 0x408970, 1, 0x04, 0x00012c00 },
229 { 0x408984, 1, 0x04, 0x00000000 },
230 { 0x408988, 1, 0x04, 0x08040201 },
231 { 0x40898c, 1, 0x04, 0x80402010 },
232 {}
233 };
234
235 static const struct gf100_gr_init
236 gm107_gr_init_sm_1[] = {
237 { 0x419e5c, 1, 0x04, 0x00000000 },
238 { 0x419e58, 1, 0x04, 0x00000000 },
239 {}
240 };
241
242 static const struct gf100_gr_pack
243 gm107_gr_pack_mmio[] = {
244 { gm107_gr_init_main_0 },
245 { gk110_gr_init_fe_0 },
246 { gf100_gr_init_pri_0 },
247 { gf100_gr_init_rstr2d_0 },
248 { gf100_gr_init_pd_0 },
249 { gm107_gr_init_ds_0 },
250 { gm107_gr_init_scc_0 },
251 { gm107_gr_init_sked_0 },
252 { gk110_gr_init_cwd_0 },
253 { gm107_gr_init_prop_0 },
254 { gk208_gr_init_gpc_unk_0 },
255 { gf100_gr_init_setup_0 },
256 { gf100_gr_init_crstr_0 },
257 { gm107_gr_init_setup_1 },
258 { gm107_gr_init_zcull_0 },
259 { gf100_gr_init_gpm_0 },
260 { gm107_gr_init_gpc_unk_1 },
261 { gf100_gr_init_gcc_0 },
262 { gm107_gr_init_tpccs_0 },
263 { gm107_gr_init_tex_0 },
264 { gm107_gr_init_pe_0 },
265 { gm107_gr_init_l1c_0 },
266 { gf100_gr_init_mpc_0 },
267 { gm107_gr_init_sm_0 },
268 { gm107_gr_init_l1c_1 },
269 { gm107_gr_init_pes_0 },
270 { gm107_gr_init_wwdx_0 },
271 { gm107_gr_init_cbm_0 },
272 { gm107_gr_init_be_0 },
273 { gm107_gr_init_sm_1 },
274 {}
275 };
276
277 /*******************************************************************************
278 * PGRAPH engine/subdev functions
279 ******************************************************************************/
280
281 void
gm107_gr_init_bios(struct gf100_gr * gr)282 gm107_gr_init_bios(struct gf100_gr *gr)
283 {
284 static const struct {
285 u32 ctrl;
286 u32 data;
287 } regs[] = {
288 { 0x419ed8, 0x419ee0 },
289 { 0x419ad0, 0x419ad4 },
290 { 0x419ae0, 0x419ae4 },
291 { 0x419af0, 0x419af4 },
292 { 0x419af8, 0x419afc },
293 };
294 struct nvkm_device *device = gr->base.engine.subdev.device;
295 struct nvkm_bios *bios = device->bios;
296 struct nvbios_P0260E infoE;
297 struct nvbios_P0260X infoX;
298 int E = -1, X;
299 u8 ver, hdr;
300
301 while (nvbios_P0260Ep(bios, ++E, &ver, &hdr, &infoE)) {
302 if (X = -1, E < ARRAY_SIZE(regs)) {
303 nvkm_wr32(device, regs[E].ctrl, infoE.data);
304 while (nvbios_P0260Xp(bios, ++X, &ver, &hdr, &infoX))
305 nvkm_wr32(device, regs[E].data, infoX.data);
306 }
307 }
308 }
309
310 int
gm107_gr_init(struct gf100_gr * gr)311 gm107_gr_init(struct gf100_gr *gr)
312 {
313 struct nvkm_device *device = gr->base.engine.subdev.device;
314 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
315 u32 data[TPC_MAX / 8] = {};
316 u8 tpcnr[GPC_MAX];
317 int gpc, tpc, ppc, rop;
318 int i;
319
320 nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000);
321 nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000);
322 nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000);
323 nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8);
324 nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8);
325
326 gf100_gr_mmio(gr, gr->func->mmio);
327
328 gm107_gr_init_bios(gr);
329
330 nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001);
331
332 memset(data, 0x00, sizeof(data));
333 memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
334 for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
335 do {
336 gpc = (gpc + 1) % gr->gpc_nr;
337 } while (!tpcnr[gpc]);
338 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
339
340 data[i / 8] |= tpc << ((i % 8) * 4);
341 }
342
343 nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
344 nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
345 nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
346 nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
347
348 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
349 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
350 gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
351 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
352 gr->tpc_total);
353 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
354 }
355
356 nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
357 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
358
359 nvkm_wr32(device, 0x400500, 0x00010001);
360
361 nvkm_wr32(device, 0x400100, 0xffffffff);
362 nvkm_wr32(device, 0x40013c, 0xffffffff);
363 nvkm_wr32(device, 0x400124, 0x00000002);
364 nvkm_wr32(device, 0x409c24, 0x000e0000);
365
366 nvkm_wr32(device, 0x404000, 0xc0000000);
367 nvkm_wr32(device, 0x404600, 0xc0000000);
368 nvkm_wr32(device, 0x408030, 0xc0000000);
369 nvkm_wr32(device, 0x404490, 0xc0000000);
370 nvkm_wr32(device, 0x406018, 0xc0000000);
371 nvkm_wr32(device, 0x407020, 0x40000000);
372 nvkm_wr32(device, 0x405840, 0xc0000000);
373 nvkm_wr32(device, 0x405844, 0x00ffffff);
374 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
375
376 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
377 for (ppc = 0; ppc < 2 /* gr->ppc_nr[gpc] */; ppc++)
378 nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
379 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
380 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
381 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
382 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
383 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
384 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
385 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
386 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
387 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
388 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
389 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
390 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
391 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005);
392 }
393 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
394 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
395 }
396
397 for (rop = 0; rop < gr->rop_nr; rop++) {
398 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000);
399 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000);
400 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
401 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
402 }
403
404 nvkm_wr32(device, 0x400108, 0xffffffff);
405 nvkm_wr32(device, 0x400138, 0xffffffff);
406 nvkm_wr32(device, 0x400118, 0xffffffff);
407 nvkm_wr32(device, 0x400130, 0xffffffff);
408 nvkm_wr32(device, 0x40011c, 0xffffffff);
409 nvkm_wr32(device, 0x400134, 0xffffffff);
410
411 nvkm_wr32(device, 0x400054, 0x2c350f63);
412
413 gf100_gr_zbc_init(gr);
414
415 return gf100_gr_init_ctxctl(gr);
416 }
417
418 #include "fuc/hubgm107.fuc5.h"
419
420 static struct gf100_gr_ucode
421 gm107_gr_fecs_ucode = {
422 .code.data = gm107_grhub_code,
423 .code.size = sizeof(gm107_grhub_code),
424 .data.data = gm107_grhub_data,
425 .data.size = sizeof(gm107_grhub_data),
426 };
427
428 #include "fuc/gpcgm107.fuc5.h"
429
430 static struct gf100_gr_ucode
431 gm107_gr_gpccs_ucode = {
432 .code.data = gm107_grgpc_code,
433 .code.size = sizeof(gm107_grgpc_code),
434 .data.data = gm107_grgpc_data,
435 .data.size = sizeof(gm107_grgpc_data),
436 };
437
438 static const struct gf100_gr_func
439 gm107_gr = {
440 .init = gm107_gr_init,
441 .mmio = gm107_gr_pack_mmio,
442 .fecs.ucode = &gm107_gr_fecs_ucode,
443 .gpccs.ucode = &gm107_gr_gpccs_ucode,
444 .ppc_nr = 2,
445 .grctx = &gm107_grctx,
446 .sclass = {
447 { -1, -1, FERMI_TWOD_A },
448 { -1, -1, KEPLER_INLINE_TO_MEMORY_B },
449 { -1, -1, MAXWELL_A, &gf100_fermi },
450 { -1, -1, MAXWELL_COMPUTE_A },
451 {}
452 }
453 };
454
455 int
gm107_gr_new(struct nvkm_device * device,int index,struct nvkm_gr ** pgr)456 gm107_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
457 {
458 return gf100_gr_new_(&gm107_gr, device, index, pgr);
459 }
460