1 /*
2 * Copyright 2015 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24 #include "gf100.h"
25 #include "ctxgf100.h"
26
27 #include <nvif/class.h>
28
29 /*******************************************************************************
30 * PGRAPH register lists
31 ******************************************************************************/
32
33 static const struct gf100_gr_init
34 gm204_gr_init_main_0[] = {
35 { 0x400080, 1, 0x04, 0x003003e2 },
36 { 0x400088, 1, 0x04, 0xe007bfe7 },
37 { 0x40008c, 1, 0x04, 0x00060000 },
38 { 0x400090, 1, 0x04, 0x00000030 },
39 { 0x40013c, 1, 0x04, 0x003901f3 },
40 { 0x400140, 1, 0x04, 0x00000100 },
41 { 0x400144, 1, 0x04, 0x00000000 },
42 { 0x400148, 1, 0x04, 0x00000110 },
43 { 0x400138, 1, 0x04, 0x00000000 },
44 { 0x400130, 2, 0x04, 0x00000000 },
45 { 0x400124, 1, 0x04, 0x00000002 },
46 {}
47 };
48
49 static const struct gf100_gr_init
50 gm204_gr_init_fe_0[] = {
51 { 0x40415c, 1, 0x04, 0x00000000 },
52 { 0x404170, 1, 0x04, 0x00000000 },
53 { 0x4041b4, 1, 0x04, 0x00000000 },
54 { 0x4041b8, 1, 0x04, 0x00000010 },
55 {}
56 };
57
58 static const struct gf100_gr_init
59 gm204_gr_init_ds_0[] = {
60 { 0x40583c, 1, 0x04, 0x00000000 },
61 { 0x405844, 1, 0x04, 0x00ffffff },
62 { 0x40584c, 1, 0x04, 0x00000001 },
63 { 0x405850, 1, 0x04, 0x00000000 },
64 { 0x405900, 1, 0x04, 0x00000000 },
65 { 0x405908, 1, 0x04, 0x00000000 },
66 {}
67 };
68
69 static const struct gf100_gr_init
70 gm204_gr_init_sked_0[] = {
71 { 0x407010, 1, 0x04, 0x00000000 },
72 { 0x407040, 1, 0x04, 0x80440434 },
73 { 0x407048, 1, 0x04, 0x00000008 },
74 {}
75 };
76
77 static const struct gf100_gr_init
78 gm204_gr_init_tpccs_0[] = {
79 { 0x419d60, 1, 0x04, 0x0000003f },
80 { 0x419d88, 3, 0x04, 0x00000000 },
81 { 0x419dc4, 1, 0x04, 0x00000000 },
82 { 0x419dc8, 1, 0x04, 0x00000501 },
83 { 0x419dd0, 1, 0x04, 0x00000000 },
84 { 0x419dd4, 1, 0x04, 0x00000100 },
85 { 0x419dd8, 1, 0x04, 0x00000001 },
86 { 0x419ddc, 1, 0x04, 0x00000002 },
87 { 0x419de0, 1, 0x04, 0x00000001 },
88 { 0x419de8, 1, 0x04, 0x000000cc },
89 { 0x419dec, 1, 0x04, 0x00000000 },
90 { 0x419df0, 1, 0x04, 0x000000cc },
91 { 0x419df4, 1, 0x04, 0x00000000 },
92 { 0x419d0c, 1, 0x04, 0x00000000 },
93 { 0x419d10, 1, 0x04, 0x00000014 },
94 {}
95 };
96
97 static const struct gf100_gr_init
98 gm204_gr_init_pe_0[] = {
99 { 0x419900, 1, 0x04, 0x000000ff },
100 { 0x419810, 1, 0x04, 0x00000000 },
101 { 0x41980c, 1, 0x04, 0x00000010 },
102 { 0x419844, 1, 0x04, 0x00000000 },
103 { 0x419838, 1, 0x04, 0x000000ff },
104 { 0x419850, 1, 0x04, 0x00000004 },
105 { 0x419854, 2, 0x04, 0x00000000 },
106 { 0x419894, 3, 0x04, 0x00100401 },
107 {}
108 };
109
110 static const struct gf100_gr_init
111 gm204_gr_init_sm_0[] = {
112 { 0x419e30, 1, 0x04, 0x000000ff },
113 { 0x419e00, 1, 0x04, 0x00000000 },
114 { 0x419ea0, 1, 0x04, 0x00000000 },
115 { 0x419ee4, 1, 0x04, 0x00000000 },
116 { 0x419ea4, 1, 0x04, 0x00000100 },
117 { 0x419ea8, 1, 0x04, 0x00000000 },
118 { 0x419ee8, 1, 0x04, 0x00000091 },
119 { 0x419eb4, 1, 0x04, 0x00000000 },
120 { 0x419ebc, 2, 0x04, 0x00000000 },
121 { 0x419edc, 1, 0x04, 0x000c1810 },
122 { 0x419ed8, 1, 0x04, 0x00000000 },
123 { 0x419ee0, 1, 0x04, 0x00000000 },
124 {}
125 };
126
127 static const struct gf100_gr_init
128 gm204_gr_init_l1c_1[] = {
129 { 0x419cf8, 2, 0x04, 0x00000000 },
130 {}
131 };
132
133 static const struct gf100_gr_init
134 gm204_gr_init_sm_1[] = {
135 { 0x419f74, 1, 0x04, 0x00055155 },
136 { 0x419f80, 4, 0x04, 0x00000000 },
137 {}
138 };
139
140 static const struct gf100_gr_init
141 gm204_gr_init_l1c_2[] = {
142 { 0x419ccc, 2, 0x04, 0x00000000 },
143 { 0x419c80, 1, 0x04, 0x3f006022 },
144 { 0x419c88, 1, 0x04, 0x00210000 },
145 {}
146 };
147
148 static const struct gf100_gr_init
149 gm204_gr_init_pes_0[] = {
150 { 0x41be50, 1, 0x04, 0x000000ff },
151 { 0x41be04, 1, 0x04, 0x00000000 },
152 { 0x41be08, 1, 0x04, 0x00000004 },
153 { 0x41be0c, 1, 0x04, 0x00000008 },
154 { 0x41be10, 1, 0x04, 0x2e3b8bc7 },
155 { 0x41be14, 2, 0x04, 0x00000000 },
156 { 0x41be3c, 5, 0x04, 0x00100401 },
157 {}
158 };
159
160 static const struct gf100_gr_init
161 gm204_gr_init_be_0[] = {
162 { 0x408890, 1, 0x04, 0x000000ff },
163 { 0x40880c, 1, 0x04, 0x00000000 },
164 { 0x408850, 1, 0x04, 0x00000004 },
165 { 0x408878, 1, 0x04, 0x01b4201c },
166 { 0x40887c, 1, 0x04, 0x80004c55 },
167 { 0x408880, 1, 0x04, 0x0018c258 },
168 { 0x408884, 1, 0x04, 0x0000160f },
169 { 0x408974, 1, 0x04, 0x000000ff },
170 { 0x408910, 9, 0x04, 0x00000000 },
171 { 0x408950, 1, 0x04, 0x00000000 },
172 { 0x408954, 1, 0x04, 0x0000ffff },
173 { 0x408958, 1, 0x04, 0x00000034 },
174 { 0x40895c, 1, 0x04, 0x84b17403 },
175 { 0x408960, 1, 0x04, 0x04c1884f },
176 { 0x408964, 1, 0x04, 0x04714445 },
177 { 0x408968, 1, 0x04, 0x0280802f },
178 { 0x40896c, 1, 0x04, 0x04304856 },
179 { 0x408970, 1, 0x04, 0x00012800 },
180 { 0x408984, 1, 0x04, 0x00000000 },
181 { 0x408988, 1, 0x04, 0x08040201 },
182 { 0x40898c, 1, 0x04, 0x80402010 },
183 {}
184 };
185
186 const struct gf100_gr_pack
187 gm204_gr_pack_mmio[] = {
188 { gm204_gr_init_main_0 },
189 { gm204_gr_init_fe_0 },
190 { gf100_gr_init_pri_0 },
191 { gf100_gr_init_rstr2d_0 },
192 { gf100_gr_init_pd_0 },
193 { gm204_gr_init_ds_0 },
194 { gm107_gr_init_scc_0 },
195 { gm204_gr_init_sked_0 },
196 { gk110_gr_init_cwd_0 },
197 { gm107_gr_init_prop_0 },
198 { gk208_gr_init_gpc_unk_0 },
199 { gf100_gr_init_setup_0 },
200 { gf100_gr_init_crstr_0 },
201 { gm107_gr_init_setup_1 },
202 { gm107_gr_init_zcull_0 },
203 { gf100_gr_init_gpm_0 },
204 { gm107_gr_init_gpc_unk_1 },
205 { gf100_gr_init_gcc_0 },
206 { gm204_gr_init_tpccs_0 },
207 { gm107_gr_init_tex_0 },
208 { gm204_gr_init_pe_0 },
209 { gm107_gr_init_l1c_0 },
210 { gf100_gr_init_mpc_0 },
211 { gm204_gr_init_sm_0 },
212 { gm204_gr_init_l1c_1 },
213 { gm204_gr_init_sm_1 },
214 { gm204_gr_init_l1c_2 },
215 { gm204_gr_init_pes_0 },
216 { gm107_gr_init_wwdx_0 },
217 { gm107_gr_init_cbm_0 },
218 { gm204_gr_init_be_0 },
219 {}
220 };
221
222 const struct gf100_gr_pack *
223 gm204_gr_data[] = {
224 gm204_gr_pack_mmio,
225 NULL
226 };
227
228 /*******************************************************************************
229 * PGRAPH engine/subdev functions
230 ******************************************************************************/
231
232 static int
gm204_gr_init_ctxctl(struct gf100_gr * gr)233 gm204_gr_init_ctxctl(struct gf100_gr *gr)
234 {
235 return 0;
236 }
237
238 int
gm204_gr_init(struct gf100_gr * gr)239 gm204_gr_init(struct gf100_gr *gr)
240 {
241 struct nvkm_device *device = gr->base.engine.subdev.device;
242 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
243 u32 data[TPC_MAX / 8] = {}, tmp;
244 u8 tpcnr[GPC_MAX];
245 int gpc, tpc, ppc, rop;
246 int i;
247
248 tmp = nvkm_rd32(device, 0x100c80); /*XXX: mask? */
249 nvkm_wr32(device, 0x418880, 0x00001000 | (tmp & 0x00000fff));
250 nvkm_wr32(device, 0x418890, 0x00000000);
251 nvkm_wr32(device, 0x418894, 0x00000000);
252 nvkm_wr32(device, 0x4188b4, nvkm_memory_addr(gr->unk4188b4) >> 8);
253 nvkm_wr32(device, 0x4188b8, nvkm_memory_addr(gr->unk4188b8) >> 8);
254 nvkm_mask(device, 0x4188b0, 0x00040000, 0x00040000);
255
256 /*XXX: belongs in fb */
257 nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(gr->unk4188b4) >> 8);
258 nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(gr->unk4188b8) >> 8);
259 nvkm_mask(device, 0x100cc4, 0x00040000, 0x00040000);
260
261 gf100_gr_mmio(gr, gr->func->mmio);
262
263 gm107_gr_init_bios(gr);
264
265 nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001);
266
267 memset(data, 0x00, sizeof(data));
268 memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
269 for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
270 do {
271 gpc = (gpc + 1) % gr->gpc_nr;
272 } while (!tpcnr[gpc]);
273 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
274
275 data[i / 8] |= tpc << ((i % 8) * 4);
276 }
277
278 nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
279 nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
280 nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
281 nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
282
283 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
284 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
285 gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
286 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
287 gr->tpc_total);
288 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
289 }
290
291 nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
292 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
293 nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804));
294
295 nvkm_wr32(device, 0x400500, 0x00010001);
296 nvkm_wr32(device, 0x400100, 0xffffffff);
297 nvkm_wr32(device, 0x40013c, 0xffffffff);
298 nvkm_wr32(device, 0x400124, 0x00000002);
299 nvkm_wr32(device, 0x409c24, 0x000e0000);
300 nvkm_wr32(device, 0x405848, 0xc0000000);
301 nvkm_wr32(device, 0x40584c, 0x00000001);
302 nvkm_wr32(device, 0x404000, 0xc0000000);
303 nvkm_wr32(device, 0x404600, 0xc0000000);
304 nvkm_wr32(device, 0x408030, 0xc0000000);
305 nvkm_wr32(device, 0x404490, 0xc0000000);
306 nvkm_wr32(device, 0x406018, 0xc0000000);
307 nvkm_wr32(device, 0x407020, 0x40000000);
308 nvkm_wr32(device, 0x405840, 0xc0000000);
309 nvkm_wr32(device, 0x405844, 0x00ffffff);
310 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
311
312 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
313 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++)
314 nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
315 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
316 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
317 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
318 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
319 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
320 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
321 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
322 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
323 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
324 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
325 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
326 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
327 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005);
328 }
329 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
330 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
331 }
332
333 for (rop = 0; rop < gr->rop_nr; rop++) {
334 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000);
335 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000);
336 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
337 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
338 }
339
340 nvkm_wr32(device, 0x400108, 0xffffffff);
341 nvkm_wr32(device, 0x400138, 0xffffffff);
342 nvkm_wr32(device, 0x400118, 0xffffffff);
343 nvkm_wr32(device, 0x400130, 0xffffffff);
344 nvkm_wr32(device, 0x40011c, 0xffffffff);
345 nvkm_wr32(device, 0x400134, 0xffffffff);
346
347 nvkm_wr32(device, 0x400054, 0x2c350f63);
348
349 gf100_gr_zbc_init(gr);
350
351 return gm204_gr_init_ctxctl(gr);
352 }
353
354 static const struct gf100_gr_func
355 gm204_gr = {
356 .init = gm204_gr_init,
357 .mmio = gm204_gr_pack_mmio,
358 .ppc_nr = 2,
359 .grctx = &gm204_grctx,
360 .sclass = {
361 { -1, -1, FERMI_TWOD_A },
362 { -1, -1, KEPLER_INLINE_TO_MEMORY_B },
363 { -1, -1, MAXWELL_B, &gf100_fermi },
364 { -1, -1, MAXWELL_COMPUTE_B },
365 {}
366 }
367 };
368
369 int
gm204_gr_new(struct nvkm_device * device,int index,struct nvkm_gr ** pgr)370 gm204_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
371 {
372 return gf100_gr_new_(&gm204_gr, device, index, pgr);
373 }
374