1 /*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22 #include "ctxgf100.h"
23
24 static void
gm20b_grctx_generate_r406028(struct gf100_gr * gr)25 gm20b_grctx_generate_r406028(struct gf100_gr *gr)
26 {
27 struct nvkm_device *device = gr->base.engine.subdev.device;
28 u32 tpc_per_gpc = 0;
29 int i;
30
31 for (i = 0; i < gr->gpc_nr; i++)
32 tpc_per_gpc |= gr->tpc_nr[i] << (4 * i);
33
34 nvkm_wr32(device, 0x406028, tpc_per_gpc);
35 nvkm_wr32(device, 0x405870, tpc_per_gpc);
36 }
37
38 static void
gm20b_grctx_generate_main(struct gf100_gr * gr,struct gf100_grctx * info)39 gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
40 {
41 struct nvkm_device *device = gr->base.engine.subdev.device;
42 const struct gf100_grctx_func *grctx = gr->func->grctx;
43 int idle_timeout_save;
44 int i, tmp;
45
46 gf100_gr_mmio(gr, gr->fuc_sw_ctx);
47
48 gf100_gr_wait_idle(gr);
49
50 idle_timeout_save = nvkm_rd32(device, 0x404154);
51 nvkm_wr32(device, 0x404154, 0x00000000);
52
53 grctx->attrib(info);
54
55 grctx->unkn(gr);
56
57 gm204_grctx_generate_tpcid(gr);
58 gm20b_grctx_generate_r406028(gr);
59 gk104_grctx_generate_r418bb8(gr);
60
61 for (i = 0; i < 8; i++)
62 nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
63
64 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
65
66 gk104_grctx_generate_rop_active_fbps(gr);
67 nvkm_wr32(device, 0x408908, nvkm_rd32(device, 0x410108) | 0x80000000);
68
69 for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
70 tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4);
71 nvkm_wr32(device, 0x4041c4, tmp);
72
73 gm204_grctx_generate_405b60(gr);
74
75 gf100_gr_wait_idle(gr);
76
77 nvkm_wr32(device, 0x404154, idle_timeout_save);
78 gf100_gr_wait_idle(gr);
79
80 gf100_gr_mthd(gr, gr->fuc_method);
81 gf100_gr_wait_idle(gr);
82
83 gf100_gr_icmd(gr, gr->fuc_bundle);
84 grctx->pagepool(info);
85 grctx->bundle(info);
86 }
87
88 const struct gf100_grctx_func
89 gm20b_grctx = {
90 .main = gm20b_grctx_generate_main,
91 .unkn = gk104_grctx_generate_unkn,
92 .bundle = gm107_grctx_generate_bundle,
93 .bundle_size = 0x1800,
94 .bundle_min_gpm_fifo_depth = 0x182,
95 .bundle_token_limit = 0x1c0,
96 .pagepool = gm107_grctx_generate_pagepool,
97 .pagepool_size = 0x8000,
98 .attrib = gm107_grctx_generate_attrib,
99 .attrib_nr_max = 0x600,
100 .attrib_nr = 0x400,
101 .alpha_nr_max = 0xc00,
102 .alpha_nr = 0x800,
103 };
104