1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 #include <uapi/drm/drm_fourcc.h> 35 36 #include "i915_reg.h" 37 #include "intel_bios.h" 38 #include "intel_ringbuffer.h" 39 #include "intel_lrc.h" 40 #include "i915_gem_gtt.h" 41 #include "i915_gem_render_state.h" 42 #include <linux/io-mapping.h> 43 #include <linux/i2c.h> 44 #include <linux/i2c-algo-bit.h> 45 #include <drm/intel-gtt.h> 46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ 47 #include <drm/drm_gem.h> 48 #include <linux/backlight.h> 49 #include <linux/hashtable.h> 50 #include <linux/intel-iommu.h> 51 #include <linux/kref.h> 52 #include <linux/pm_qos.h> 53 #include "intel_guc.h" 54 55 /* General customization: 56 */ 57 58 #define DRIVER_NAME "i915" 59 #define DRIVER_DESC "Intel Graphics" 60 #define DRIVER_DATE "20151010" 61 62 #undef WARN_ON 63 /* Many gcc seem to no see through this and fall over :( */ 64 #if 0 65 #define WARN_ON(x) ({ \ 66 bool __i915_warn_cond = (x); \ 67 if (__builtin_constant_p(__i915_warn_cond)) \ 68 BUILD_BUG_ON(__i915_warn_cond); \ 69 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) 70 #else 71 #define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x ) 72 #endif 73 74 #undef WARN_ON_ONCE 75 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x ) 76 77 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ 78 (long) (x), __func__); 79 80 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and 81 * WARN_ON()) for hw state sanity checks to check for unexpected conditions 82 * which may not necessarily be a user visible problem. This will either 83 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to 84 * enable distros and users to tailor their preferred amount of i915 abrt 85 * spam. 86 */ 87 #define I915_STATE_WARN(condition, format...) ({ \ 88 int __ret_warn_on = !!(condition); \ 89 if (unlikely(__ret_warn_on)) { \ 90 if (i915.verbose_state_checks) \ 91 WARN(1, format); \ 92 else \ 93 DRM_ERROR(format); \ 94 } \ 95 unlikely(__ret_warn_on); \ 96 }) 97 98 #define I915_STATE_WARN_ON(condition) ({ \ 99 int __ret_warn_on = !!(condition); \ 100 if (unlikely(__ret_warn_on)) { \ 101 if (i915.verbose_state_checks) \ 102 WARN(1, "WARN_ON(" #condition ")\n"); \ 103 else \ 104 DRM_ERROR("WARN_ON(" #condition ")\n"); \ 105 } \ 106 unlikely(__ret_warn_on); \ 107 }) 108 yesno(bool v)109 static inline const char *yesno(bool v) 110 { 111 return v ? "yes" : "no"; 112 } 113 114 enum pipe { 115 INVALID_PIPE = -1, 116 PIPE_A = 0, 117 PIPE_B, 118 PIPE_C, 119 _PIPE_EDP, 120 I915_MAX_PIPES = _PIPE_EDP 121 }; 122 #define pipe_name(p) ((p) + 'A') 123 124 enum transcoder { 125 TRANSCODER_A = 0, 126 TRANSCODER_B, 127 TRANSCODER_C, 128 TRANSCODER_EDP, 129 I915_MAX_TRANSCODERS 130 }; 131 #define transcoder_name(t) ((t) + 'A') 132 133 /* 134 * I915_MAX_PLANES in the enum below is the maximum (across all platforms) 135 * number of planes per CRTC. Not all platforms really have this many planes, 136 * which means some arrays of size I915_MAX_PLANES may have unused entries 137 * between the topmost sprite plane and the cursor plane. 138 */ 139 enum plane { 140 PLANE_A = 0, 141 PLANE_B, 142 PLANE_C, 143 PLANE_CURSOR, 144 I915_MAX_PLANES, 145 }; 146 #define plane_name(p) ((p) + 'A') 147 148 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') 149 150 enum port { 151 PORT_A = 0, 152 PORT_B, 153 PORT_C, 154 PORT_D, 155 PORT_E, 156 I915_MAX_PORTS 157 }; 158 #define port_name(p) ((p) + 'A') 159 160 #define I915_NUM_PHYS_VLV 2 161 162 enum dpio_channel { 163 DPIO_CH0, 164 DPIO_CH1 165 }; 166 167 enum dpio_phy { 168 DPIO_PHY0, 169 DPIO_PHY1 170 }; 171 172 enum intel_display_power_domain { 173 POWER_DOMAIN_PIPE_A, 174 POWER_DOMAIN_PIPE_B, 175 POWER_DOMAIN_PIPE_C, 176 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 177 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 178 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 179 POWER_DOMAIN_TRANSCODER_A, 180 POWER_DOMAIN_TRANSCODER_B, 181 POWER_DOMAIN_TRANSCODER_C, 182 POWER_DOMAIN_TRANSCODER_EDP, 183 POWER_DOMAIN_PORT_DDI_A_2_LANES, 184 POWER_DOMAIN_PORT_DDI_A_4_LANES, 185 POWER_DOMAIN_PORT_DDI_B_2_LANES, 186 POWER_DOMAIN_PORT_DDI_B_4_LANES, 187 POWER_DOMAIN_PORT_DDI_C_2_LANES, 188 POWER_DOMAIN_PORT_DDI_C_4_LANES, 189 POWER_DOMAIN_PORT_DDI_D_2_LANES, 190 POWER_DOMAIN_PORT_DDI_D_4_LANES, 191 POWER_DOMAIN_PORT_DDI_E_2_LANES, 192 POWER_DOMAIN_PORT_DSI, 193 POWER_DOMAIN_PORT_CRT, 194 POWER_DOMAIN_PORT_OTHER, 195 POWER_DOMAIN_VGA, 196 POWER_DOMAIN_AUDIO, 197 POWER_DOMAIN_PLLS, 198 POWER_DOMAIN_AUX_A, 199 POWER_DOMAIN_AUX_B, 200 POWER_DOMAIN_AUX_C, 201 POWER_DOMAIN_AUX_D, 202 POWER_DOMAIN_GMBUS, 203 POWER_DOMAIN_INIT, 204 205 POWER_DOMAIN_NUM, 206 }; 207 208 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 209 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 210 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 211 #define POWER_DOMAIN_TRANSCODER(tran) \ 212 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 213 (tran) + POWER_DOMAIN_TRANSCODER_A) 214 215 enum hpd_pin { 216 HPD_NONE = 0, 217 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 218 HPD_CRT, 219 HPD_SDVO_B, 220 HPD_SDVO_C, 221 HPD_PORT_A, 222 HPD_PORT_B, 223 HPD_PORT_C, 224 HPD_PORT_D, 225 HPD_PORT_E, 226 HPD_NUM_PINS 227 }; 228 229 #define for_each_hpd_pin(__pin) \ 230 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 231 232 struct i915_hotplug { 233 struct work_struct hotplug_work; 234 235 struct { 236 unsigned long last_jiffies; 237 int count; 238 enum { 239 HPD_ENABLED = 0, 240 HPD_DISABLED = 1, 241 HPD_MARK_DISABLED = 2 242 } state; 243 } stats[HPD_NUM_PINS]; 244 u32 event_bits; 245 struct delayed_work reenable_work; 246 247 struct intel_digital_port *irq_port[I915_MAX_PORTS]; 248 u32 long_port_mask; 249 u32 short_port_mask; 250 struct work_struct dig_port_work; 251 252 /* 253 * if we get a HPD irq from DP and a HPD irq from non-DP 254 * the non-DP HPD could block the workqueue on a mode config 255 * mutex getting, that userspace may have taken. However 256 * userspace is waiting on the DP workqueue to run which is 257 * blocked behind the non-DP one. 258 */ 259 struct workqueue_struct *dp_wq; 260 }; 261 262 #define I915_GEM_GPU_DOMAINS \ 263 (I915_GEM_DOMAIN_RENDER | \ 264 I915_GEM_DOMAIN_SAMPLER | \ 265 I915_GEM_DOMAIN_COMMAND | \ 266 I915_GEM_DOMAIN_INSTRUCTION | \ 267 I915_GEM_DOMAIN_VERTEX) 268 269 #define for_each_pipe(__dev_priv, __p) \ 270 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) 271 #define for_each_plane(__dev_priv, __pipe, __p) \ 272 for ((__p) = 0; \ 273 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ 274 (__p)++) 275 #define for_each_sprite(__dev_priv, __p, __s) \ 276 for ((__s) = 0; \ 277 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ 278 (__s)++) 279 280 #define for_each_crtc(dev, crtc) \ 281 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 282 283 #define for_each_intel_plane(dev, intel_plane) \ 284 list_for_each_entry(intel_plane, \ 285 &dev->mode_config.plane_list, \ 286 base.head) 287 288 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ 289 list_for_each_entry(intel_plane, \ 290 &(dev)->mode_config.plane_list, \ 291 base.head) \ 292 if ((intel_plane)->pipe == (intel_crtc)->pipe) 293 294 #define for_each_intel_crtc(dev, intel_crtc) \ 295 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) 296 297 #define for_each_intel_encoder(dev, intel_encoder) \ 298 list_for_each_entry(intel_encoder, \ 299 &(dev)->mode_config.encoder_list, \ 300 base.head) 301 302 #define for_each_intel_connector(dev, intel_connector) \ 303 list_for_each_entry(intel_connector, \ 304 &dev->mode_config.connector_list, \ 305 base.head) 306 307 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 308 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 309 if ((intel_encoder)->base.crtc == (__crtc)) 310 311 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 312 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 313 if ((intel_connector)->base.encoder == (__encoder)) 314 315 #define for_each_power_domain(domain, mask) \ 316 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 317 if ((1 << (domain)) & (mask)) 318 319 struct drm_i915_private; 320 struct i915_mm_struct; 321 struct i915_mmu_object; 322 323 struct drm_i915_file_private { 324 struct drm_i915_private *dev_priv; 325 struct drm_file *file; 326 327 struct { 328 spinlock_t lock; 329 struct list_head request_list; 330 /* 20ms is a fairly arbitrary limit (greater than the average frame time) 331 * chosen to prevent the CPU getting more than a frame ahead of the GPU 332 * (when using lax throttling for the frontbuffer). We also use it to 333 * offer free GPU waitboosts for severely congested workloads. 334 */ 335 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) 336 } mm; 337 struct idr context_idr; 338 339 struct intel_rps_client { 340 struct list_head link; 341 unsigned boosts; 342 } rps; 343 344 struct intel_engine_cs *bsd_ring; 345 }; 346 347 enum intel_dpll_id { 348 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ 349 /* real shared dpll ids must be >= 0 */ 350 DPLL_ID_PCH_PLL_A = 0, 351 DPLL_ID_PCH_PLL_B = 1, 352 /* hsw/bdw */ 353 DPLL_ID_WRPLL1 = 0, 354 DPLL_ID_WRPLL2 = 1, 355 DPLL_ID_SPLL = 2, 356 357 /* skl */ 358 DPLL_ID_SKL_DPLL1 = 0, 359 DPLL_ID_SKL_DPLL2 = 1, 360 DPLL_ID_SKL_DPLL3 = 2, 361 }; 362 #define I915_NUM_PLLS 3 363 364 struct intel_dpll_hw_state { 365 /* i9xx, pch plls */ 366 uint32_t dpll; 367 uint32_t dpll_md; 368 uint32_t fp0; 369 uint32_t fp1; 370 371 /* hsw, bdw */ 372 uint32_t wrpll; 373 uint32_t spll; 374 375 /* skl */ 376 /* 377 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in 378 * lower part of ctrl1 and they get shifted into position when writing 379 * the register. This allows us to easily compare the state to share 380 * the DPLL. 381 */ 382 uint32_t ctrl1; 383 /* HDMI only, 0 when used for DP */ 384 uint32_t cfgcr1, cfgcr2; 385 386 /* bxt */ 387 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, 388 pcsdw12; 389 }; 390 391 struct intel_shared_dpll_config { 392 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */ 393 struct intel_dpll_hw_state hw_state; 394 }; 395 396 struct intel_shared_dpll { 397 struct intel_shared_dpll_config config; 398 399 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 400 bool on; /* is the PLL actually active? Disabled during modeset */ 401 const char *name; 402 /* should match the index in the dev_priv->shared_dplls array */ 403 enum intel_dpll_id id; 404 /* The mode_set hook is optional and should be used together with the 405 * intel_prepare_shared_dpll function. */ 406 void (*mode_set)(struct drm_i915_private *dev_priv, 407 struct intel_shared_dpll *pll); 408 void (*enable)(struct drm_i915_private *dev_priv, 409 struct intel_shared_dpll *pll); 410 void (*disable)(struct drm_i915_private *dev_priv, 411 struct intel_shared_dpll *pll); 412 bool (*get_hw_state)(struct drm_i915_private *dev_priv, 413 struct intel_shared_dpll *pll, 414 struct intel_dpll_hw_state *hw_state); 415 }; 416 417 #define SKL_DPLL0 0 418 #define SKL_DPLL1 1 419 #define SKL_DPLL2 2 420 #define SKL_DPLL3 3 421 422 /* Used by dp and fdi links */ 423 struct intel_link_m_n { 424 uint32_t tu; 425 uint32_t gmch_m; 426 uint32_t gmch_n; 427 uint32_t link_m; 428 uint32_t link_n; 429 }; 430 431 void intel_link_compute_m_n(int bpp, int nlanes, 432 int pixel_clock, int link_clock, 433 struct intel_link_m_n *m_n); 434 435 /* Interface history: 436 * 437 * 1.1: Original. 438 * 1.2: Add Power Management 439 * 1.3: Add vblank support 440 * 1.4: Fix cmdbuffer path, add heap destroy 441 * 1.5: Add vblank pipe configuration 442 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 443 * - Support vertical blank on secondary display pipe 444 */ 445 #define DRIVER_MAJOR 1 446 #define DRIVER_MINOR 6 447 #define DRIVER_PATCHLEVEL 0 448 449 #define WATCH_LISTS 0 450 451 struct opregion_header; 452 struct opregion_acpi; 453 struct opregion_swsci; 454 struct opregion_asle; 455 456 struct intel_opregion { 457 struct opregion_header *header; 458 struct opregion_acpi *acpi; 459 struct opregion_swsci *swsci; 460 u32 swsci_gbda_sub_functions; 461 u32 swsci_sbcb_sub_functions; 462 struct opregion_asle *asle; 463 void *vbt; 464 u32 *lid_state; 465 struct work_struct asle_work; 466 }; 467 #define OPREGION_SIZE (8*1024) 468 469 struct intel_overlay; 470 struct intel_overlay_error_state; 471 472 #define I915_FENCE_REG_NONE -1 473 #define I915_MAX_NUM_FENCES 32 474 /* 32 fences + sign bit for FENCE_REG_NONE */ 475 #define I915_MAX_NUM_FENCE_BITS 6 476 477 struct drm_i915_fence_reg { 478 struct list_head lru_list; 479 struct drm_i915_gem_object *obj; 480 int pin_count; 481 }; 482 483 struct sdvo_device_mapping { 484 u8 initialized; 485 u8 dvo_port; 486 u8 slave_addr; 487 u8 dvo_wiring; 488 u8 i2c_pin; 489 u8 ddc_pin; 490 }; 491 492 struct intel_display_error_state; 493 494 struct drm_i915_error_state { 495 struct kref ref; 496 struct timeval time; 497 498 char error_msg[128]; 499 int iommu; 500 u32 reset_count; 501 u32 suspend_count; 502 503 /* Generic register state */ 504 u32 eir; 505 u32 pgtbl_er; 506 u32 ier; 507 u32 gtier[4]; 508 u32 ccid; 509 u32 derrmr; 510 u32 forcewake; 511 u32 error; /* gen6+ */ 512 u32 err_int; /* gen7 */ 513 u32 fault_data0; /* gen8, gen9 */ 514 u32 fault_data1; /* gen8, gen9 */ 515 u32 done_reg; 516 u32 gac_eco; 517 u32 gam_ecochk; 518 u32 gab_ctl; 519 u32 gfx_mode; 520 u32 extra_instdone[I915_NUM_INSTDONE_REG]; 521 u64 fence[I915_MAX_NUM_FENCES]; 522 struct intel_overlay_error_state *overlay; 523 struct intel_display_error_state *display; 524 struct drm_i915_error_object *semaphore_obj; 525 526 struct drm_i915_error_ring { 527 bool valid; 528 /* Software tracked state */ 529 bool waiting; 530 int hangcheck_score; 531 enum intel_ring_hangcheck_action hangcheck_action; 532 int num_requests; 533 534 /* our own tracking of ring head and tail */ 535 u32 cpu_ring_head; 536 u32 cpu_ring_tail; 537 538 u32 semaphore_seqno[I915_NUM_RINGS - 1]; 539 540 /* Register state */ 541 u32 start; 542 u32 tail; 543 u32 head; 544 u32 ctl; 545 u32 hws; 546 u32 ipeir; 547 u32 ipehr; 548 u32 instdone; 549 u32 bbstate; 550 u32 instpm; 551 u32 instps; 552 u32 seqno; 553 u64 bbaddr; 554 u64 acthd; 555 u32 fault_reg; 556 u64 faddr; 557 u32 rc_psmi; /* sleep state */ 558 u32 semaphore_mboxes[I915_NUM_RINGS - 1]; 559 560 struct drm_i915_error_object { 561 int page_count; 562 u64 gtt_offset; 563 u32 *pages[0]; 564 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; 565 566 struct drm_i915_error_request { 567 long jiffies; 568 u32 seqno; 569 u32 tail; 570 } *requests; 571 572 struct { 573 u32 gfx_mode; 574 union { 575 u64 pdp[4]; 576 u32 pp_dir_base; 577 }; 578 } vm_info; 579 580 pid_t pid; 581 char comm[TASK_COMM_LEN]; 582 } ring[I915_NUM_RINGS]; 583 584 struct drm_i915_error_buffer { 585 u32 size; 586 u32 name; 587 u32 rseqno[I915_NUM_RINGS], wseqno; 588 u64 gtt_offset; 589 u32 read_domains; 590 u32 write_domain; 591 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 592 s32 pinned:2; 593 u32 tiling:2; 594 u32 dirty:1; 595 u32 purgeable:1; 596 u32 userptr:1; 597 s32 ring:4; 598 u32 cache_level:3; 599 } **active_bo, **pinned_bo; 600 601 u32 *active_bo_count, *pinned_bo_count; 602 u32 vm_count; 603 }; 604 605 struct intel_connector; 606 struct intel_encoder; 607 struct intel_crtc_state; 608 struct intel_initial_plane_config; 609 struct intel_crtc; 610 struct intel_limit; 611 struct dpll; 612 613 struct drm_i915_display_funcs { 614 int (*get_display_clock_speed)(struct drm_device *dev); 615 int (*get_fifo_size)(struct drm_device *dev, int plane); 616 /** 617 * find_dpll() - Find the best values for the PLL 618 * @limit: limits for the PLL 619 * @crtc: current CRTC 620 * @target: target frequency in kHz 621 * @refclk: reference clock frequency in kHz 622 * @match_clock: if provided, @best_clock P divider must 623 * match the P divider from @match_clock 624 * used for LVDS downclocking 625 * @best_clock: best PLL values found 626 * 627 * Returns true on success, false on failure. 628 */ 629 bool (*find_dpll)(const struct intel_limit *limit, 630 struct intel_crtc_state *crtc_state, 631 int target, int refclk, 632 struct dpll *match_clock, 633 struct dpll *best_clock); 634 void (*update_wm)(struct drm_crtc *crtc); 635 void (*update_sprite_wm)(struct drm_plane *plane, 636 struct drm_crtc *crtc, 637 uint32_t sprite_width, uint32_t sprite_height, 638 int pixel_size, bool enable, bool scaled); 639 int (*modeset_calc_cdclk)(struct drm_atomic_state *state); 640 void (*modeset_commit_cdclk)(struct drm_atomic_state *state); 641 /* Returns the active state of the crtc, and if the crtc is active, 642 * fills out the pipe-config with the hw state. */ 643 bool (*get_pipe_config)(struct intel_crtc *, 644 struct intel_crtc_state *); 645 void (*get_initial_plane_config)(struct intel_crtc *, 646 struct intel_initial_plane_config *); 647 int (*crtc_compute_clock)(struct intel_crtc *crtc, 648 struct intel_crtc_state *crtc_state); 649 void (*crtc_enable)(struct drm_crtc *crtc); 650 void (*crtc_disable)(struct drm_crtc *crtc); 651 void (*audio_codec_enable)(struct drm_connector *connector, 652 struct intel_encoder *encoder, 653 const struct drm_display_mode *adjusted_mode); 654 void (*audio_codec_disable)(struct intel_encoder *encoder); 655 void (*fdi_link_train)(struct drm_crtc *crtc); 656 void (*init_clock_gating)(struct drm_device *dev); 657 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 658 struct drm_framebuffer *fb, 659 struct drm_i915_gem_object *obj, 660 struct drm_i915_gem_request *req, 661 uint32_t flags); 662 void (*update_primary_plane)(struct drm_crtc *crtc, 663 struct drm_framebuffer *fb, 664 int x, int y); 665 void (*hpd_irq_setup)(struct drm_device *dev); 666 /* clock updates for mode set */ 667 /* cursor updates */ 668 /* render clock increase/decrease */ 669 /* display clock increase/decrease */ 670 /* pll clock increase/decrease */ 671 }; 672 673 enum forcewake_domain_id { 674 FW_DOMAIN_ID_RENDER = 0, 675 FW_DOMAIN_ID_BLITTER, 676 FW_DOMAIN_ID_MEDIA, 677 678 FW_DOMAIN_ID_COUNT 679 }; 680 681 enum forcewake_domains { 682 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), 683 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), 684 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), 685 FORCEWAKE_ALL = (FORCEWAKE_RENDER | 686 FORCEWAKE_BLITTER | 687 FORCEWAKE_MEDIA) 688 }; 689 690 struct intel_uncore_funcs { 691 void (*force_wake_get)(struct drm_i915_private *dev_priv, 692 enum forcewake_domains domains); 693 void (*force_wake_put)(struct drm_i915_private *dev_priv, 694 enum forcewake_domains domains); 695 696 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 697 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 698 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 699 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 700 701 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, 702 uint8_t val, bool trace); 703 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, 704 uint16_t val, bool trace); 705 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, 706 uint32_t val, bool trace); 707 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, 708 uint64_t val, bool trace); 709 }; 710 711 struct intel_uncore { 712 spinlock_t lock; /** lock is also taken in irq contexts. */ 713 714 struct intel_uncore_funcs funcs; 715 716 unsigned fifo_count; 717 enum forcewake_domains fw_domains; 718 719 struct intel_uncore_forcewake_domain { 720 struct drm_i915_private *i915; 721 enum forcewake_domain_id id; 722 unsigned wake_count; 723 struct timer_list timer; 724 u32 reg_set; 725 u32 val_set; 726 u32 val_clear; 727 u32 reg_ack; 728 u32 reg_post; 729 u32 val_reset; 730 } fw_domain[FW_DOMAIN_ID_COUNT]; 731 }; 732 733 /* Iterate over initialised fw domains */ 734 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \ 735 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ 736 (i__) < FW_DOMAIN_ID_COUNT; \ 737 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \ 738 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__))) 739 740 #define for_each_fw_domain(domain__, dev_priv__, i__) \ 741 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) 742 743 enum csr_state { 744 FW_UNINITIALIZED = 0, 745 FW_LOADED, 746 FW_FAILED 747 }; 748 749 struct intel_csr { 750 const char *fw_path; 751 uint32_t *dmc_payload; 752 uint32_t dmc_fw_size; 753 uint32_t mmio_count; 754 uint32_t mmioaddr[8]; 755 uint32_t mmiodata[8]; 756 enum csr_state state; 757 }; 758 759 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ 760 func(is_mobile) sep \ 761 func(is_i85x) sep \ 762 func(is_i915g) sep \ 763 func(is_i945gm) sep \ 764 func(is_g33) sep \ 765 func(need_gfx_hws) sep \ 766 func(is_g4x) sep \ 767 func(is_pineview) sep \ 768 func(is_broadwater) sep \ 769 func(is_crestline) sep \ 770 func(is_ivybridge) sep \ 771 func(is_valleyview) sep \ 772 func(is_haswell) sep \ 773 func(is_skylake) sep \ 774 func(is_preliminary) sep \ 775 func(has_fbc) sep \ 776 func(has_pipe_cxsr) sep \ 777 func(has_hotplug) sep \ 778 func(cursor_needs_physical) sep \ 779 func(has_overlay) sep \ 780 func(overlay_needs_physical) sep \ 781 func(supports_tv) sep \ 782 func(has_llc) sep \ 783 func(has_ddi) sep \ 784 func(has_fpga_dbg) 785 786 #define DEFINE_FLAG(name) u8 name:1 787 #define SEP_SEMICOLON ; 788 789 struct intel_device_info { 790 u32 display_mmio_offset; 791 u16 device_id; 792 u8 num_pipes:3; 793 u8 num_sprites[I915_MAX_PIPES]; 794 u8 gen; 795 u8 ring_mask; /* Rings supported by the HW */ 796 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); 797 /* Register offsets for the various display pipes and transcoders */ 798 int pipe_offsets[I915_MAX_TRANSCODERS]; 799 int trans_offsets[I915_MAX_TRANSCODERS]; 800 int palette_offsets[I915_MAX_PIPES]; 801 int cursor_offsets[I915_MAX_PIPES]; 802 803 /* Slice/subslice/EU info */ 804 u8 slice_total; 805 u8 subslice_total; 806 u8 subslice_per_slice; 807 u8 eu_total; 808 u8 eu_per_subslice; 809 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ 810 u8 subslice_7eu[3]; 811 u8 has_slice_pg:1; 812 u8 has_subslice_pg:1; 813 u8 has_eu_pg:1; 814 }; 815 816 #undef DEFINE_FLAG 817 #undef SEP_SEMICOLON 818 819 enum i915_cache_level { 820 I915_CACHE_NONE = 0, 821 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 822 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 823 caches, eg sampler/render caches, and the 824 large Last-Level-Cache. LLC is coherent with 825 the CPU, but L3 is only visible to the GPU. */ 826 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 827 }; 828 829 struct i915_ctx_hang_stats { 830 /* This context had batch pending when hang was declared */ 831 unsigned batch_pending; 832 833 /* This context had batch active when hang was declared */ 834 unsigned batch_active; 835 836 /* Time when this context was last blamed for a GPU reset */ 837 unsigned long guilty_ts; 838 839 /* If the contexts causes a second GPU hang within this time, 840 * it is permanently banned from submitting any more work. 841 */ 842 unsigned long ban_period_seconds; 843 844 /* This context is banned to submit more work */ 845 bool banned; 846 }; 847 848 /* This must match up with the value previously used for execbuf2.rsvd1. */ 849 #define DEFAULT_CONTEXT_HANDLE 0 850 851 #define CONTEXT_NO_ZEROMAP (1<<0) 852 /** 853 * struct intel_context - as the name implies, represents a context. 854 * @ref: reference count. 855 * @user_handle: userspace tracking identity for this context. 856 * @remap_slice: l3 row remapping information. 857 * @flags: context specific flags: 858 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0. 859 * @file_priv: filp associated with this context (NULL for global default 860 * context). 861 * @hang_stats: information about the role of this context in possible GPU 862 * hangs. 863 * @ppgtt: virtual memory space used by this context. 864 * @legacy_hw_ctx: render context backing object and whether it is correctly 865 * initialized (legacy ring submission mechanism only). 866 * @link: link in the global list of contexts. 867 * 868 * Contexts are memory images used by the hardware to store copies of their 869 * internal state. 870 */ 871 struct intel_context { 872 struct kref ref; 873 int user_handle; 874 uint8_t remap_slice; 875 struct drm_i915_private *i915; 876 int flags; 877 struct drm_i915_file_private *file_priv; 878 struct i915_ctx_hang_stats hang_stats; 879 struct i915_hw_ppgtt *ppgtt; 880 881 /* Legacy ring buffer submission */ 882 struct { 883 struct drm_i915_gem_object *rcs_state; 884 bool initialized; 885 } legacy_hw_ctx; 886 887 /* Execlists */ 888 struct { 889 struct drm_i915_gem_object *state; 890 struct intel_ringbuffer *ringbuf; 891 int pin_count; 892 } engine[I915_NUM_RINGS]; 893 894 /* jump_whitelist: Bit array for tracking cmds during cmdparsing */ 895 unsigned long *jump_whitelist; 896 897 /* jump_whitelist_cmds: No of cmd slots available */ 898 uint32_t jump_whitelist_cmds; 899 900 struct list_head link; 901 }; 902 903 enum fb_op_origin { 904 ORIGIN_GTT, 905 ORIGIN_CPU, 906 ORIGIN_CS, 907 ORIGIN_FLIP, 908 ORIGIN_DIRTYFB, 909 }; 910 911 struct i915_fbc { 912 /* This is always the inner lock when overlapping with struct_mutex and 913 * it's the outer lock when overlapping with stolen_lock. */ 914 struct mutex lock; 915 unsigned long uncompressed_size; 916 unsigned threshold; 917 unsigned int fb_id; 918 unsigned int possible_framebuffer_bits; 919 unsigned int busy_bits; 920 struct intel_crtc *crtc; 921 int y; 922 923 struct drm_mm_node compressed_fb; 924 struct drm_mm_node *compressed_llb; 925 926 bool false_color; 927 928 /* Tracks whether the HW is actually enabled, not whether the feature is 929 * possible. */ 930 bool enabled; 931 932 struct intel_fbc_work { 933 struct delayed_work work; 934 struct intel_crtc *crtc; 935 struct drm_framebuffer *fb; 936 } *fbc_work; 937 938 enum no_fbc_reason { 939 FBC_OK, /* FBC is enabled */ 940 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ 941 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 942 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ 943 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 944 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 945 FBC_BAD_PLANE, /* fbc not supported on plane */ 946 FBC_NOT_TILED, /* buffer not tiled */ 947 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 948 FBC_MODULE_PARAM, 949 FBC_CHIP_DEFAULT, /* disabled by default on this chip */ 950 FBC_ROTATION, /* rotation is not supported */ 951 FBC_IN_DBG_MASTER, /* kernel debugger is active */ 952 FBC_BAD_STRIDE, /* stride is not supported */ 953 FBC_PIXEL_RATE, /* pixel rate is too big */ 954 FBC_PIXEL_FORMAT /* pixel format is invalid */ 955 } no_fbc_reason; 956 957 bool (*fbc_enabled)(struct drm_i915_private *dev_priv); 958 void (*enable_fbc)(struct intel_crtc *crtc); 959 void (*disable_fbc)(struct drm_i915_private *dev_priv); 960 }; 961 962 /** 963 * HIGH_RR is the highest eDP panel refresh rate read from EDID 964 * LOW_RR is the lowest eDP panel refresh rate found from EDID 965 * parsing for same resolution. 966 */ 967 enum drrs_refresh_rate_type { 968 DRRS_HIGH_RR, 969 DRRS_LOW_RR, 970 DRRS_MAX_RR, /* RR count */ 971 }; 972 973 enum drrs_support_type { 974 DRRS_NOT_SUPPORTED = 0, 975 STATIC_DRRS_SUPPORT = 1, 976 SEAMLESS_DRRS_SUPPORT = 2 977 }; 978 979 struct intel_dp; 980 struct i915_drrs { 981 struct mutex mutex; 982 struct delayed_work work; 983 struct intel_dp *dp; 984 unsigned busy_frontbuffer_bits; 985 enum drrs_refresh_rate_type refresh_rate_type; 986 enum drrs_support_type type; 987 }; 988 989 struct i915_psr { 990 struct mutex lock; 991 bool sink_support; 992 bool source_ok; 993 struct intel_dp *enabled; 994 bool active; 995 struct delayed_work work; 996 unsigned busy_frontbuffer_bits; 997 bool psr2_support; 998 bool aux_frame_sync; 999 }; 1000 1001 enum intel_pch { 1002 PCH_NONE = 0, /* No PCH present */ 1003 PCH_IBX, /* Ibexpeak PCH */ 1004 PCH_CPT, /* Cougarpoint PCH */ 1005 PCH_LPT, /* Lynxpoint PCH */ 1006 PCH_SPT, /* Sunrisepoint PCH */ 1007 PCH_NOP, 1008 }; 1009 1010 enum intel_sbi_destination { 1011 SBI_ICLK, 1012 SBI_MPHY, 1013 }; 1014 1015 #define QUIRK_PIPEA_FORCE (1<<0) 1016 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 1017 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 1018 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 1019 #define QUIRK_PIPEB_FORCE (1<<4) 1020 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) 1021 1022 struct intel_fbdev; 1023 struct intel_fbc_work; 1024 1025 struct intel_gmbus { 1026 struct i2c_adapter adapter; 1027 u32 force_bit; 1028 u32 reg0; 1029 u32 gpio_reg; 1030 struct i2c_algo_bit_data bit_algo; 1031 struct drm_i915_private *dev_priv; 1032 }; 1033 1034 struct i915_suspend_saved_registers { 1035 u32 saveDSPARB; 1036 u32 saveLVDS; 1037 u32 savePP_ON_DELAYS; 1038 u32 savePP_OFF_DELAYS; 1039 u32 savePP_ON; 1040 u32 savePP_OFF; 1041 u32 savePP_CONTROL; 1042 u32 savePP_DIVISOR; 1043 u32 saveFBC_CONTROL; 1044 u32 saveCACHE_MODE_0; 1045 u32 saveMI_ARB_STATE; 1046 u32 saveSWF0[16]; 1047 u32 saveSWF1[16]; 1048 u32 saveSWF3[3]; 1049 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 1050 u32 savePCH_PORT_HOTPLUG; 1051 u16 saveGCDGMBUS; 1052 }; 1053 1054 struct vlv_s0ix_state { 1055 /* GAM */ 1056 u32 wr_watermark; 1057 u32 gfx_prio_ctrl; 1058 u32 arb_mode; 1059 u32 gfx_pend_tlb0; 1060 u32 gfx_pend_tlb1; 1061 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; 1062 u32 media_max_req_count; 1063 u32 gfx_max_req_count; 1064 u32 render_hwsp; 1065 u32 ecochk; 1066 u32 bsd_hwsp; 1067 u32 blt_hwsp; 1068 u32 tlb_rd_addr; 1069 1070 /* MBC */ 1071 u32 g3dctl; 1072 u32 gsckgctl; 1073 u32 mbctl; 1074 1075 /* GCP */ 1076 u32 ucgctl1; 1077 u32 ucgctl3; 1078 u32 rcgctl1; 1079 u32 rcgctl2; 1080 u32 rstctl; 1081 u32 misccpctl; 1082 1083 /* GPM */ 1084 u32 gfxpause; 1085 u32 rpdeuhwtc; 1086 u32 rpdeuc; 1087 u32 ecobus; 1088 u32 pwrdwnupctl; 1089 u32 rp_down_timeout; 1090 u32 rp_deucsw; 1091 u32 rcubmabdtmr; 1092 u32 rcedata; 1093 u32 spare2gh; 1094 1095 /* Display 1 CZ domain */ 1096 u32 gt_imr; 1097 u32 gt_ier; 1098 u32 pm_imr; 1099 u32 pm_ier; 1100 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; 1101 1102 /* GT SA CZ domain */ 1103 u32 tilectl; 1104 u32 gt_fifoctl; 1105 u32 gtlc_wake_ctrl; 1106 u32 gtlc_survive; 1107 u32 pmwgicz; 1108 1109 /* Display 2 CZ domain */ 1110 u32 gu_ctl0; 1111 u32 gu_ctl1; 1112 u32 pcbr; 1113 u32 clock_gate_dis2; 1114 }; 1115 1116 struct intel_rps_ei { 1117 u32 cz_clock; 1118 u32 render_c0; 1119 u32 media_c0; 1120 }; 1121 1122 struct intel_gen6_power_mgmt { 1123 /* 1124 * work, interrupts_enabled and pm_iir are protected by 1125 * dev_priv->irq_lock 1126 */ 1127 struct work_struct work; 1128 bool interrupts_enabled; 1129 u32 pm_iir; 1130 1131 /* Frequencies are stored in potentially platform dependent multiples. 1132 * In other words, *_freq needs to be multiplied by X to be interesting. 1133 * Soft limits are those which are used for the dynamic reclocking done 1134 * by the driver (raise frequencies under heavy loads, and lower for 1135 * lighter loads). Hard limits are those imposed by the hardware. 1136 * 1137 * A distinction is made for overclocking, which is never enabled by 1138 * default, and is considered to be above the hard limit if it's 1139 * possible at all. 1140 */ 1141 u8 cur_freq; /* Current frequency (cached, may not == HW) */ 1142 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ 1143 u8 max_freq_softlimit; /* Max frequency permitted by the driver */ 1144 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ 1145 u8 min_freq; /* AKA RPn. Minimum frequency */ 1146 u8 idle_freq; /* Frequency to request when we are idle */ 1147 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ 1148 u8 rp1_freq; /* "less than" RP0 power/freqency */ 1149 u8 rp0_freq; /* Non-overclocked max frequency. */ 1150 1151 u8 up_threshold; /* Current %busy required to uplock */ 1152 u8 down_threshold; /* Current %busy required to downclock */ 1153 1154 int last_adj; 1155 enum { LOW_POWER, BETWEEN, HIGH_POWER } power; 1156 1157 spinlock_t client_lock; 1158 struct list_head clients; 1159 bool client_boost; 1160 1161 bool enabled; 1162 bool ctx_corrupted; 1163 struct delayed_work delayed_resume_work; 1164 unsigned boosts; 1165 1166 struct intel_rps_client semaphores, mmioflips; 1167 1168 /* manual wa residency calculations */ 1169 struct intel_rps_ei ei; 1170 1171 /* 1172 * Protects RPS/RC6 register access and PCU communication. 1173 * Must be taken after struct_mutex if nested. Note that 1174 * this lock may be held for long periods of time when 1175 * talking to hw - so only take it when talking to hw! 1176 */ 1177 struct mutex hw_lock; 1178 }; 1179 1180 /* defined intel_pm.c */ 1181 extern spinlock_t mchdev_lock; 1182 1183 struct intel_ilk_power_mgmt { 1184 u8 cur_delay; 1185 u8 min_delay; 1186 u8 max_delay; 1187 u8 fmax; 1188 u8 fstart; 1189 1190 u64 last_count1; 1191 unsigned long last_time1; 1192 unsigned long chipset_power; 1193 u64 last_count2; 1194 u64 last_time2; 1195 unsigned long gfx_power; 1196 u8 corr; 1197 1198 int c_m; 1199 int r_t; 1200 }; 1201 1202 struct drm_i915_private; 1203 struct i915_power_well; 1204 1205 struct i915_power_well_ops { 1206 /* 1207 * Synchronize the well's hw state to match the current sw state, for 1208 * example enable/disable it based on the current refcount. Called 1209 * during driver init and resume time, possibly after first calling 1210 * the enable/disable handlers. 1211 */ 1212 void (*sync_hw)(struct drm_i915_private *dev_priv, 1213 struct i915_power_well *power_well); 1214 /* 1215 * Enable the well and resources that depend on it (for example 1216 * interrupts located on the well). Called after the 0->1 refcount 1217 * transition. 1218 */ 1219 void (*enable)(struct drm_i915_private *dev_priv, 1220 struct i915_power_well *power_well); 1221 /* 1222 * Disable the well and resources that depend on it. Called after 1223 * the 1->0 refcount transition. 1224 */ 1225 void (*disable)(struct drm_i915_private *dev_priv, 1226 struct i915_power_well *power_well); 1227 /* Returns the hw enabled state. */ 1228 bool (*is_enabled)(struct drm_i915_private *dev_priv, 1229 struct i915_power_well *power_well); 1230 }; 1231 1232 /* Power well structure for haswell */ 1233 struct i915_power_well { 1234 const char *name; 1235 bool always_on; 1236 /* power well enable/disable usage count */ 1237 int count; 1238 /* cached hw enabled state */ 1239 bool hw_enabled; 1240 unsigned long domains; 1241 unsigned long data; 1242 const struct i915_power_well_ops *ops; 1243 }; 1244 1245 struct i915_power_domains { 1246 /* 1247 * Power wells needed for initialization at driver init and suspend 1248 * time are on. They are kept on until after the first modeset. 1249 */ 1250 bool init_power_on; 1251 bool initializing; 1252 int power_well_count; 1253 1254 struct mutex lock; 1255 int domain_use_count[POWER_DOMAIN_NUM]; 1256 struct i915_power_well *power_wells; 1257 }; 1258 1259 #define MAX_L3_SLICES 2 1260 struct intel_l3_parity { 1261 u32 *remap_info[MAX_L3_SLICES]; 1262 struct work_struct error_work; 1263 int which_slice; 1264 }; 1265 1266 struct i915_gem_mm { 1267 /** Memory allocator for GTT stolen memory */ 1268 struct drm_mm stolen; 1269 /** Protects the usage of the GTT stolen memory allocator. This is 1270 * always the inner lock when overlapping with struct_mutex. */ 1271 struct mutex stolen_lock; 1272 1273 /** List of all objects in gtt_space. Used to restore gtt 1274 * mappings on resume */ 1275 struct list_head bound_list; 1276 /** 1277 * List of objects which are not bound to the GTT (thus 1278 * are idle and not used by the GPU) but still have 1279 * (presumably uncached) pages still attached. 1280 */ 1281 struct list_head unbound_list; 1282 1283 /** Usable portion of the GTT for GEM */ 1284 unsigned long stolen_base; /* limited to low memory (32-bit) */ 1285 1286 /** PPGTT used for aliasing the PPGTT with the GTT */ 1287 struct i915_hw_ppgtt *aliasing_ppgtt; 1288 1289 struct notifier_block oom_notifier; 1290 struct shrinker shrinker; 1291 bool shrinker_no_lock_stealing; 1292 1293 /** LRU list of objects with fence regs on them. */ 1294 struct list_head fence_list; 1295 1296 /** 1297 * We leave the user IRQ off as much as possible, 1298 * but this means that requests will finish and never 1299 * be retired once the system goes idle. Set a timer to 1300 * fire periodically while the ring is running. When it 1301 * fires, go retire requests. 1302 */ 1303 struct delayed_work retire_work; 1304 1305 /** 1306 * When we detect an idle GPU, we want to turn on 1307 * powersaving features. So once we see that there 1308 * are no more requests outstanding and no more 1309 * arrive within a small period of time, we fire 1310 * off the idle_work. 1311 */ 1312 struct delayed_work idle_work; 1313 1314 /** 1315 * Are we in a non-interruptible section of code like 1316 * modesetting? 1317 */ 1318 bool interruptible; 1319 1320 /** 1321 * Is the GPU currently considered idle, or busy executing userspace 1322 * requests? Whilst idle, we attempt to power down the hardware and 1323 * display clocks. In order to reduce the effect on performance, there 1324 * is a slight delay before we do so. 1325 */ 1326 bool busy; 1327 1328 /* the indicator for dispatch video commands on two BSD rings */ 1329 int bsd_ring_dispatch_index; 1330 1331 /** Bit 6 swizzling required for X tiling */ 1332 uint32_t bit_6_swizzle_x; 1333 /** Bit 6 swizzling required for Y tiling */ 1334 uint32_t bit_6_swizzle_y; 1335 1336 /* accounting, useful for userland debugging */ 1337 spinlock_t object_stat_lock; 1338 size_t object_memory; 1339 u32 object_count; 1340 }; 1341 1342 struct drm_i915_error_state_buf { 1343 struct drm_i915_private *i915; 1344 unsigned bytes; 1345 unsigned size; 1346 int err; 1347 u8 *buf; 1348 loff_t start; 1349 loff_t pos; 1350 }; 1351 1352 struct i915_error_state_file_priv { 1353 struct drm_device *dev; 1354 struct drm_i915_error_state *error; 1355 }; 1356 1357 struct i915_gpu_error { 1358 /* For hangcheck timer */ 1359 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 1360 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 1361 /* Hang gpu twice in this window and your context gets banned */ 1362 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) 1363 1364 struct workqueue_struct *hangcheck_wq; 1365 struct delayed_work hangcheck_work; 1366 1367 /* For reset and error_state handling. */ 1368 spinlock_t lock; 1369 /* Protected by the above dev->gpu_error.lock. */ 1370 struct drm_i915_error_state *first_error; 1371 1372 unsigned long missed_irq_rings; 1373 1374 /** 1375 * State variable controlling the reset flow and count 1376 * 1377 * This is a counter which gets incremented when reset is triggered, 1378 * and again when reset has been handled. So odd values (lowest bit set) 1379 * means that reset is in progress and even values that 1380 * (reset_counter >> 1):th reset was successfully completed. 1381 * 1382 * If reset is not completed succesfully, the I915_WEDGE bit is 1383 * set meaning that hardware is terminally sour and there is no 1384 * recovery. All waiters on the reset_queue will be woken when 1385 * that happens. 1386 * 1387 * This counter is used by the wait_seqno code to notice that reset 1388 * event happened and it needs to restart the entire ioctl (since most 1389 * likely the seqno it waited for won't ever signal anytime soon). 1390 * 1391 * This is important for lock-free wait paths, where no contended lock 1392 * naturally enforces the correct ordering between the bail-out of the 1393 * waiter and the gpu reset work code. 1394 */ 1395 atomic_t reset_counter; 1396 1397 #define I915_RESET_IN_PROGRESS_FLAG 1 1398 #define I915_WEDGED (1 << 31) 1399 1400 /** 1401 * Waitqueue to signal when the reset has completed. Used by clients 1402 * that wait for dev_priv->mm.wedged to settle. 1403 */ 1404 wait_queue_head_t reset_queue; 1405 1406 /* Userspace knobs for gpu hang simulation; 1407 * combines both a ring mask, and extra flags 1408 */ 1409 u32 stop_rings; 1410 #define I915_STOP_RING_ALLOW_BAN (1 << 31) 1411 #define I915_STOP_RING_ALLOW_WARN (1 << 30) 1412 1413 /* For missed irq/seqno simulation. */ 1414 unsigned int test_irq_rings; 1415 1416 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ 1417 bool reload_in_reset; 1418 }; 1419 1420 enum modeset_restore { 1421 MODESET_ON_LID_OPEN, 1422 MODESET_DONE, 1423 MODESET_SUSPENDED, 1424 }; 1425 1426 #define DP_AUX_A 0x40 1427 #define DP_AUX_B 0x10 1428 #define DP_AUX_C 0x20 1429 #define DP_AUX_D 0x30 1430 1431 #define DDC_PIN_B 0x05 1432 #define DDC_PIN_C 0x04 1433 #define DDC_PIN_D 0x06 1434 1435 struct ddi_vbt_port_info { 1436 /* 1437 * This is an index in the HDMI/DVI DDI buffer translation table. 1438 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't 1439 * populate this field. 1440 */ 1441 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff 1442 uint8_t hdmi_level_shift; 1443 1444 uint8_t supports_dvi:1; 1445 uint8_t supports_hdmi:1; 1446 uint8_t supports_dp:1; 1447 1448 uint8_t alternate_aux_channel; 1449 uint8_t alternate_ddc_pin; 1450 1451 uint8_t dp_boost_level; 1452 uint8_t hdmi_boost_level; 1453 }; 1454 1455 enum psr_lines_to_wait { 1456 PSR_0_LINES_TO_WAIT = 0, 1457 PSR_1_LINE_TO_WAIT, 1458 PSR_4_LINES_TO_WAIT, 1459 PSR_8_LINES_TO_WAIT 1460 }; 1461 1462 struct intel_vbt_data { 1463 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 1464 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 1465 1466 /* Feature bits */ 1467 unsigned int int_tv_support:1; 1468 unsigned int lvds_dither:1; 1469 unsigned int lvds_vbt:1; 1470 unsigned int int_crt_support:1; 1471 unsigned int lvds_use_ssc:1; 1472 unsigned int display_clock_mode:1; 1473 unsigned int fdi_rx_polarity_inverted:1; 1474 unsigned int has_mipi:1; 1475 int lvds_ssc_freq; 1476 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 1477 1478 enum drrs_support_type drrs_type; 1479 1480 /* eDP */ 1481 int edp_rate; 1482 int edp_lanes; 1483 int edp_preemphasis; 1484 int edp_vswing; 1485 bool edp_initialized; 1486 bool edp_support; 1487 int edp_bpp; 1488 struct edp_power_seq edp_pps; 1489 1490 struct { 1491 bool full_link; 1492 bool require_aux_wakeup; 1493 int idle_frames; 1494 enum psr_lines_to_wait lines_to_wait; 1495 int tp1_wakeup_time; 1496 int tp2_tp3_wakeup_time; 1497 } psr; 1498 1499 struct { 1500 u16 pwm_freq_hz; 1501 bool present; 1502 bool active_low_pwm; 1503 u8 min_brightness; /* min_brightness/255 of max */ 1504 } backlight; 1505 1506 /* MIPI DSI */ 1507 struct { 1508 u16 port; 1509 u16 panel_id; 1510 struct mipi_config *config; 1511 struct mipi_pps_data *pps; 1512 u8 seq_version; 1513 u32 size; 1514 u8 *data; 1515 u8 *sequence[MIPI_SEQ_MAX]; 1516 } dsi; 1517 1518 int crt_ddc_pin; 1519 1520 int child_dev_num; 1521 union child_device_config *child_dev; 1522 1523 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 1524 }; 1525 1526 enum intel_ddb_partitioning { 1527 INTEL_DDB_PART_1_2, 1528 INTEL_DDB_PART_5_6, /* IVB+ */ 1529 }; 1530 1531 struct intel_wm_level { 1532 bool enable; 1533 uint32_t pri_val; 1534 uint32_t spr_val; 1535 uint32_t cur_val; 1536 uint32_t fbc_val; 1537 }; 1538 1539 struct ilk_wm_values { 1540 uint32_t wm_pipe[3]; 1541 uint32_t wm_lp[3]; 1542 uint32_t wm_lp_spr[3]; 1543 uint32_t wm_linetime[3]; 1544 bool enable_fbc_wm; 1545 enum intel_ddb_partitioning partitioning; 1546 }; 1547 1548 struct vlv_pipe_wm { 1549 uint16_t primary; 1550 uint16_t sprite[2]; 1551 uint8_t cursor; 1552 }; 1553 1554 struct vlv_sr_wm { 1555 uint16_t plane; 1556 uint8_t cursor; 1557 }; 1558 1559 struct vlv_wm_values { 1560 struct vlv_pipe_wm pipe[3]; 1561 struct vlv_sr_wm sr; 1562 struct { 1563 uint8_t cursor; 1564 uint8_t sprite[2]; 1565 uint8_t primary; 1566 } ddl[3]; 1567 uint8_t level; 1568 bool cxsr; 1569 }; 1570 1571 struct skl_ddb_entry { 1572 uint16_t start, end; /* in number of blocks, 'end' is exclusive */ 1573 }; 1574 skl_ddb_entry_size(const struct skl_ddb_entry * entry)1575 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) 1576 { 1577 return entry->end - entry->start; 1578 } 1579 skl_ddb_entry_equal(const struct skl_ddb_entry * e1,const struct skl_ddb_entry * e2)1580 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, 1581 const struct skl_ddb_entry *e2) 1582 { 1583 if (e1->start == e2->start && e1->end == e2->end) 1584 return true; 1585 1586 return false; 1587 } 1588 1589 struct skl_ddb_allocation { 1590 struct skl_ddb_entry pipe[I915_MAX_PIPES]; 1591 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ 1592 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; 1593 }; 1594 1595 struct skl_wm_values { 1596 bool dirty[I915_MAX_PIPES]; 1597 struct skl_ddb_allocation ddb; 1598 uint32_t wm_linetime[I915_MAX_PIPES]; 1599 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; 1600 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; 1601 }; 1602 1603 struct skl_wm_level { 1604 bool plane_en[I915_MAX_PLANES]; 1605 uint16_t plane_res_b[I915_MAX_PLANES]; 1606 uint8_t plane_res_l[I915_MAX_PLANES]; 1607 }; 1608 1609 /* 1610 * This struct helps tracking the state needed for runtime PM, which puts the 1611 * device in PCI D3 state. Notice that when this happens, nothing on the 1612 * graphics device works, even register access, so we don't get interrupts nor 1613 * anything else. 1614 * 1615 * Every piece of our code that needs to actually touch the hardware needs to 1616 * either call intel_runtime_pm_get or call intel_display_power_get with the 1617 * appropriate power domain. 1618 * 1619 * Our driver uses the autosuspend delay feature, which means we'll only really 1620 * suspend if we stay with zero refcount for a certain amount of time. The 1621 * default value is currently very conservative (see intel_runtime_pm_enable), but 1622 * it can be changed with the standard runtime PM files from sysfs. 1623 * 1624 * The irqs_disabled variable becomes true exactly after we disable the IRQs and 1625 * goes back to false exactly before we reenable the IRQs. We use this variable 1626 * to check if someone is trying to enable/disable IRQs while they're supposed 1627 * to be disabled. This shouldn't happen and we'll print some error messages in 1628 * case it happens. 1629 * 1630 * For more, read the Documentation/power/runtime_pm.txt. 1631 */ 1632 struct i915_runtime_pm { 1633 bool suspended; 1634 bool irqs_enabled; 1635 }; 1636 1637 enum intel_pipe_crc_source { 1638 INTEL_PIPE_CRC_SOURCE_NONE, 1639 INTEL_PIPE_CRC_SOURCE_PLANE1, 1640 INTEL_PIPE_CRC_SOURCE_PLANE2, 1641 INTEL_PIPE_CRC_SOURCE_PF, 1642 INTEL_PIPE_CRC_SOURCE_PIPE, 1643 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 1644 INTEL_PIPE_CRC_SOURCE_TV, 1645 INTEL_PIPE_CRC_SOURCE_DP_B, 1646 INTEL_PIPE_CRC_SOURCE_DP_C, 1647 INTEL_PIPE_CRC_SOURCE_DP_D, 1648 INTEL_PIPE_CRC_SOURCE_AUTO, 1649 INTEL_PIPE_CRC_SOURCE_MAX, 1650 }; 1651 1652 struct intel_pipe_crc_entry { 1653 uint32_t frame; 1654 uint32_t crc[5]; 1655 }; 1656 1657 #define INTEL_PIPE_CRC_ENTRIES_NR 128 1658 struct intel_pipe_crc { 1659 spinlock_t lock; 1660 bool opened; /* exclusive access to the result file */ 1661 struct intel_pipe_crc_entry *entries; 1662 enum intel_pipe_crc_source source; 1663 int head, tail; 1664 wait_queue_head_t wq; 1665 }; 1666 1667 struct i915_frontbuffer_tracking { 1668 struct mutex lock; 1669 1670 /* 1671 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 1672 * scheduled flips. 1673 */ 1674 unsigned busy_bits; 1675 unsigned flip_bits; 1676 }; 1677 1678 struct i915_wa_reg { 1679 u32 addr; 1680 u32 value; 1681 /* bitmask representing WA bits */ 1682 u32 mask; 1683 }; 1684 1685 #define I915_MAX_WA_REGS 16 1686 1687 struct i915_workarounds { 1688 struct i915_wa_reg reg[I915_MAX_WA_REGS]; 1689 u32 count; 1690 }; 1691 1692 struct i915_virtual_gpu { 1693 bool active; 1694 }; 1695 1696 struct i915_execbuffer_params { 1697 struct drm_device *dev; 1698 struct drm_file *file; 1699 uint32_t dispatch_flags; 1700 uint32_t args_batch_start_offset; 1701 uint64_t batch_obj_vm_offset; 1702 struct intel_engine_cs *ring; 1703 struct drm_i915_gem_object *batch_obj; 1704 struct intel_context *ctx; 1705 struct drm_i915_gem_request *request; 1706 }; 1707 1708 struct drm_i915_private { 1709 struct drm_device *dev; 1710 struct kmem_cache *objects; 1711 struct kmem_cache *vmas; 1712 struct kmem_cache *requests; 1713 1714 const struct intel_device_info info; 1715 1716 int relative_constants_mode; 1717 1718 void __iomem *regs; 1719 1720 struct intel_uncore uncore; 1721 1722 struct mutex tlb_invalidate_lock; 1723 1724 struct i915_virtual_gpu vgpu; 1725 1726 struct intel_guc guc; 1727 1728 struct intel_csr csr; 1729 1730 /* Display CSR-related protection */ 1731 struct mutex csr_lock; 1732 1733 struct intel_gmbus gmbus[GMBUS_NUM_PINS]; 1734 1735 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 1736 * controller on different i2c buses. */ 1737 struct mutex gmbus_mutex; 1738 1739 /** 1740 * Base address of the gmbus and gpio block. 1741 */ 1742 uint32_t gpio_mmio_base; 1743 1744 /* MMIO base address for MIPI regs */ 1745 uint32_t mipi_mmio_base; 1746 1747 wait_queue_head_t gmbus_wait_queue; 1748 1749 struct pci_dev *bridge_dev; 1750 struct intel_engine_cs ring[I915_NUM_RINGS]; 1751 struct drm_i915_gem_object *semaphore_obj; 1752 uint32_t last_seqno, next_seqno; 1753 1754 struct drm_dma_handle *status_page_dmah; 1755 struct resource mch_res; 1756 1757 /* protects the irq masks */ 1758 spinlock_t irq_lock; 1759 1760 /* protects the mmio flip data */ 1761 spinlock_t mmio_flip_lock; 1762 1763 bool display_irqs_enabled; 1764 1765 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1766 struct pm_qos_request pm_qos; 1767 1768 /* Sideband mailbox protection */ 1769 struct mutex sb_lock; 1770 1771 /** Cached value of IMR to avoid reads in updating the bitfield */ 1772 union { 1773 u32 irq_mask; 1774 u32 de_irq_mask[I915_MAX_PIPES]; 1775 }; 1776 u32 gt_irq_mask; 1777 u32 pm_irq_mask; 1778 u32 pm_rps_events; 1779 u32 pipestat_irq_mask[I915_MAX_PIPES]; 1780 1781 struct i915_hotplug hotplug; 1782 struct i915_fbc fbc; 1783 struct i915_drrs drrs; 1784 struct intel_opregion opregion; 1785 struct intel_vbt_data vbt; 1786 1787 bool preserve_bios_swizzle; 1788 1789 /* overlay */ 1790 struct intel_overlay *overlay; 1791 1792 /* backlight registers and fields in struct intel_panel */ 1793 struct mutex backlight_lock; 1794 1795 /* LVDS info */ 1796 bool no_aux_handshake; 1797 1798 /* protects panel power sequencer state */ 1799 struct mutex pps_mutex; 1800 1801 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 1802 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 1803 1804 unsigned int fsb_freq, mem_freq, is_ddr3; 1805 unsigned int skl_boot_cdclk; 1806 unsigned int cdclk_freq, max_cdclk_freq; 1807 unsigned int max_dotclk_freq; 1808 unsigned int hpll_freq; 1809 unsigned int czclk_freq; 1810 1811 /** 1812 * wq - Driver workqueue for GEM. 1813 * 1814 * NOTE: Work items scheduled here are not allowed to grab any modeset 1815 * locks, for otherwise the flushing done in the pageflip code will 1816 * result in deadlocks. 1817 */ 1818 struct workqueue_struct *wq; 1819 1820 /* Display functions */ 1821 struct drm_i915_display_funcs display; 1822 1823 /* PCH chipset type */ 1824 enum intel_pch pch_type; 1825 unsigned short pch_id; 1826 1827 unsigned long quirks; 1828 1829 enum modeset_restore modeset_restore; 1830 struct mutex modeset_restore_lock; 1831 1832 struct list_head vm_list; /* Global list of all address spaces */ 1833 struct i915_gtt gtt; /* VM representing the global address space */ 1834 1835 struct i915_gem_mm mm; 1836 DECLARE_HASHTABLE(mm_structs, 7); 1837 struct mutex mm_lock; 1838 1839 /* Kernel Modesetting */ 1840 1841 struct sdvo_device_mapping sdvo_mappings[2]; 1842 1843 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 1844 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 1845 wait_queue_head_t pending_flip_queue; 1846 1847 #ifdef CONFIG_DEBUG_FS 1848 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; 1849 #endif 1850 1851 int num_shared_dpll; 1852 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1853 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1854 1855 struct i915_workarounds workarounds; 1856 1857 /* Reclocking support */ 1858 bool render_reclock_avail; 1859 1860 struct i915_frontbuffer_tracking fb_tracking; 1861 1862 u16 orig_clock; 1863 1864 bool mchbar_need_disable; 1865 1866 struct intel_l3_parity l3_parity; 1867 1868 /* Cannot be determined by PCIID. You must always read a register. */ 1869 size_t ellc_size; 1870 1871 /* gen6+ rps state */ 1872 struct intel_gen6_power_mgmt rps; 1873 1874 /* ilk-only ips/rps state. Everything in here is protected by the global 1875 * mchdev_lock in intel_pm.c */ 1876 struct intel_ilk_power_mgmt ips; 1877 1878 struct i915_power_domains power_domains; 1879 1880 struct i915_psr psr; 1881 1882 struct i915_gpu_error gpu_error; 1883 1884 struct drm_i915_gem_object *vlv_pctx; 1885 1886 #ifdef CONFIG_DRM_FBDEV_EMULATION 1887 /* list of fbdev register on this device */ 1888 struct intel_fbdev *fbdev; 1889 struct work_struct fbdev_suspend_work; 1890 #endif 1891 1892 struct drm_property *broadcast_rgb_property; 1893 struct drm_property *force_audio_property; 1894 1895 /* hda/i915 audio component */ 1896 struct i915_audio_component *audio_component; 1897 bool audio_component_registered; 1898 /** 1899 * av_mutex - mutex for audio/video sync 1900 * 1901 */ 1902 struct mutex av_mutex; 1903 1904 uint32_t hw_context_size; 1905 struct list_head context_list; 1906 1907 u32 fdi_rx_config; 1908 1909 u32 chv_phy_control; 1910 1911 u32 suspend_count; 1912 struct i915_suspend_saved_registers regfile; 1913 struct vlv_s0ix_state vlv_s0ix_state; 1914 1915 struct { 1916 /* 1917 * Raw watermark latency values: 1918 * in 0.1us units for WM0, 1919 * in 0.5us units for WM1+. 1920 */ 1921 /* primary */ 1922 uint16_t pri_latency[5]; 1923 /* sprite */ 1924 uint16_t spr_latency[5]; 1925 /* cursor */ 1926 uint16_t cur_latency[5]; 1927 /* 1928 * Raw watermark memory latency values 1929 * for SKL for all 8 levels 1930 * in 1us units. 1931 */ 1932 uint16_t skl_latency[8]; 1933 1934 /* 1935 * The skl_wm_values structure is a bit too big for stack 1936 * allocation, so we keep the staging struct where we store 1937 * intermediate results here instead. 1938 */ 1939 struct skl_wm_values skl_results; 1940 1941 /* current hardware state */ 1942 union { 1943 struct ilk_wm_values hw; 1944 struct skl_wm_values skl_hw; 1945 struct vlv_wm_values vlv; 1946 }; 1947 1948 uint8_t max_level; 1949 } wm; 1950 1951 struct i915_runtime_pm pm; 1952 1953 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 1954 struct { 1955 int (*execbuf_submit)(struct i915_execbuffer_params *params, 1956 struct drm_i915_gem_execbuffer2 *args, 1957 struct list_head *vmas); 1958 int (*init_rings)(struct drm_device *dev); 1959 void (*cleanup_ring)(struct intel_engine_cs *ring); 1960 void (*stop_ring)(struct intel_engine_cs *ring); 1961 } gt; 1962 1963 bool edp_low_vswing; 1964 1965 /* perform PHY state sanity checks? */ 1966 bool chv_phy_assert[2]; 1967 1968 /* 1969 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1970 * will be rejected. Instead look for a better place. 1971 */ 1972 }; 1973 to_i915(const struct drm_device * dev)1974 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1975 { 1976 return dev->dev_private; 1977 } 1978 dev_to_i915(struct device * dev)1979 static inline struct drm_i915_private *dev_to_i915(struct device *dev) 1980 { 1981 return to_i915(dev_get_drvdata(dev)); 1982 } 1983 guc_to_i915(struct intel_guc * guc)1984 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) 1985 { 1986 return container_of(guc, struct drm_i915_private, guc); 1987 } 1988 1989 /* Iterate over initialised rings */ 1990 #define for_each_ring(ring__, dev_priv__, i__) \ 1991 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 1992 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 1993 1994 enum hdmi_force_audio { 1995 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 1996 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 1997 HDMI_AUDIO_AUTO, /* trust EDID */ 1998 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 1999 }; 2000 2001 #define I915_GTT_OFFSET_NONE ((u32)-1) 2002 2003 struct drm_i915_gem_object_ops { 2004 /* Interface between the GEM object and its backing storage. 2005 * get_pages() is called once prior to the use of the associated set 2006 * of pages before to binding them into the GTT, and put_pages() is 2007 * called after we no longer need them. As we expect there to be 2008 * associated cost with migrating pages between the backing storage 2009 * and making them available for the GPU (e.g. clflush), we may hold 2010 * onto the pages after they are no longer referenced by the GPU 2011 * in case they may be used again shortly (for example migrating the 2012 * pages to a different memory domain within the GTT). put_pages() 2013 * will therefore most likely be called when the object itself is 2014 * being released or under memory pressure (where we attempt to 2015 * reap pages for the shrinker). 2016 */ 2017 int (*get_pages)(struct drm_i915_gem_object *); 2018 void (*put_pages)(struct drm_i915_gem_object *); 2019 int (*dmabuf_export)(struct drm_i915_gem_object *); 2020 void (*release)(struct drm_i915_gem_object *); 2021 }; 2022 2023 /* 2024 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 2025 * considered to be the frontbuffer for the given plane interface-wise. This 2026 * doesn't mean that the hw necessarily already scans it out, but that any 2027 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 2028 * 2029 * We have one bit per pipe and per scanout plane type. 2030 */ 2031 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5 2032 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 2033 #define INTEL_FRONTBUFFER_BITS \ 2034 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) 2035 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ 2036 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) 2037 #define INTEL_FRONTBUFFER_CURSOR(pipe) \ 2038 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 2039 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \ 2040 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 2041 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 2042 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 2043 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 2044 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) 2045 2046 struct drm_i915_gem_object { 2047 struct drm_gem_object base; 2048 2049 const struct drm_i915_gem_object_ops *ops; 2050 2051 /** List of VMAs backed by this object */ 2052 struct list_head vma_list; 2053 2054 /** Stolen memory for this object, instead of being backed by shmem. */ 2055 struct drm_mm_node *stolen; 2056 struct list_head global_list; 2057 2058 struct list_head ring_list[I915_NUM_RINGS]; 2059 /** Used in execbuf to temporarily hold a ref */ 2060 struct list_head obj_exec_link; 2061 2062 struct list_head batch_pool_link; 2063 2064 /** 2065 * This is set if the object is on the active lists (has pending 2066 * rendering and so a non-zero seqno), and is not set if it i s on 2067 * inactive (ready to be unbound) list. 2068 */ 2069 unsigned int active:I915_NUM_RINGS; 2070 2071 unsigned long flags; 2072 #define I915_BO_WAS_BOUND_BIT 0 2073 2074 /** 2075 * This is set if the object has been written to since last bound 2076 * to the GTT 2077 */ 2078 unsigned int dirty:1; 2079 2080 /** 2081 * Fence register bits (if any) for this object. Will be set 2082 * as needed when mapped into the GTT. 2083 * Protected by dev->struct_mutex. 2084 */ 2085 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 2086 2087 /** 2088 * Advice: are the backing pages purgeable? 2089 */ 2090 unsigned int madv:2; 2091 2092 /** 2093 * Current tiling mode for the object. 2094 */ 2095 unsigned int tiling_mode:2; 2096 /** 2097 * Whether the tiling parameters for the currently associated fence 2098 * register have changed. Note that for the purposes of tracking 2099 * tiling changes we also treat the unfenced register, the register 2100 * slot that the object occupies whilst it executes a fenced 2101 * command (such as BLT on gen2/3), as a "fence". 2102 */ 2103 unsigned int fence_dirty:1; 2104 2105 /** 2106 * Is the object at the current location in the gtt mappable and 2107 * fenceable? Used to avoid costly recalculations. 2108 */ 2109 unsigned int map_and_fenceable:1; 2110 2111 /** 2112 * Whether the current gtt mapping needs to be mappable (and isn't just 2113 * mappable by accident). Track pin and fault separate for a more 2114 * accurate mappable working set. 2115 */ 2116 unsigned int fault_mappable:1; 2117 2118 /* 2119 * Is the object to be mapped as read-only to the GPU 2120 * Only honoured if hardware has relevant pte bit 2121 */ 2122 unsigned long gt_ro:1; 2123 unsigned int cache_level:3; 2124 unsigned int cache_dirty:1; 2125 2126 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; 2127 2128 unsigned int pin_display; 2129 2130 struct sg_table *pages; 2131 int pages_pin_count; 2132 struct get_page { 2133 struct scatterlist *sg; 2134 int last; 2135 } get_page; 2136 2137 /* prime dma-buf support */ 2138 void *dma_buf_vmapping; 2139 int vmapping_count; 2140 2141 /** Breadcrumb of last rendering to the buffer. 2142 * There can only be one writer, but we allow for multiple readers. 2143 * If there is a writer that necessarily implies that all other 2144 * read requests are complete - but we may only be lazily clearing 2145 * the read requests. A read request is naturally the most recent 2146 * request on a ring, so we may have two different write and read 2147 * requests on one ring where the write request is older than the 2148 * read request. This allows for the CPU to read from an active 2149 * buffer by only waiting for the write to complete. 2150 * */ 2151 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS]; 2152 struct drm_i915_gem_request *last_write_req; 2153 /** Breadcrumb of last fenced GPU access to the buffer. */ 2154 struct drm_i915_gem_request *last_fenced_req; 2155 2156 /** Current tiling stride for the object, if it's tiled. */ 2157 uint32_t stride; 2158 2159 /** References from framebuffers, locks out tiling changes. */ 2160 unsigned long framebuffer_references; 2161 2162 /** Record of address bit 17 of each page at last unbind. */ 2163 unsigned long *bit_17; 2164 2165 struct i915_gem_userptr { 2166 uintptr_t ptr; 2167 unsigned read_only :1; 2168 unsigned workers :4; 2169 #define I915_GEM_USERPTR_MAX_WORKERS 15 2170 2171 struct i915_mm_struct *mm; 2172 struct i915_mmu_object *mmu_object; 2173 struct work_struct *work; 2174 } userptr; 2175 2176 /** for phys allocated objects */ 2177 struct drm_dma_handle *phys_handle; 2178 }; 2179 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 2180 2181 void i915_gem_track_fb(struct drm_i915_gem_object *old, 2182 struct drm_i915_gem_object *new, 2183 unsigned frontbuffer_bits); 2184 2185 /** 2186 * Request queue structure. 2187 * 2188 * The request queue allows us to note sequence numbers that have been emitted 2189 * and may be associated with active buffers to be retired. 2190 * 2191 * By keeping this list, we can avoid having to do questionable sequence 2192 * number comparisons on buffer last_read|write_seqno. It also allows an 2193 * emission time to be associated with the request for tracking how far ahead 2194 * of the GPU the submission is. 2195 * 2196 * The requests are reference counted, so upon creation they should have an 2197 * initial reference taken using kref_init 2198 */ 2199 struct drm_i915_gem_request { 2200 struct kref ref; 2201 2202 /** On Which ring this request was generated */ 2203 struct drm_i915_private *i915; 2204 struct intel_engine_cs *ring; 2205 2206 /** GEM sequence number associated with the previous request, 2207 * when the HWS breadcrumb is equal to this the GPU is processing 2208 * this request. 2209 */ 2210 u32 previous_seqno; 2211 2212 /** GEM sequence number associated with this request, 2213 * when the HWS breadcrumb is equal or greater than this the GPU 2214 * has finished processing this request. 2215 */ 2216 u32 seqno; 2217 2218 /** Position in the ringbuffer of the start of the request */ 2219 u32 head; 2220 2221 /** 2222 * Position in the ringbuffer of the start of the postfix. 2223 * This is required to calculate the maximum available ringbuffer 2224 * space without overwriting the postfix. 2225 */ 2226 u32 postfix; 2227 2228 /** Position in the ringbuffer of the end of the whole request */ 2229 u32 tail; 2230 2231 /** 2232 * Context and ring buffer related to this request 2233 * Contexts are refcounted, so when this request is associated with a 2234 * context, we must increment the context's refcount, to guarantee that 2235 * it persists while any request is linked to it. Requests themselves 2236 * are also refcounted, so the request will only be freed when the last 2237 * reference to it is dismissed, and the code in 2238 * i915_gem_request_free() will then decrement the refcount on the 2239 * context. 2240 */ 2241 struct intel_context *ctx; 2242 struct intel_ringbuffer *ringbuf; 2243 2244 /** Batch buffer related to this request if any (used for 2245 error state dump only) */ 2246 struct drm_i915_gem_object *batch_obj; 2247 2248 /** Time at which this request was emitted, in jiffies. */ 2249 unsigned long emitted_jiffies; 2250 2251 /** global list entry for this request */ 2252 struct list_head list; 2253 2254 struct drm_i915_file_private *file_priv; 2255 /** file_priv list entry for this request */ 2256 struct list_head client_list; 2257 2258 /** process identifier submitting this request */ 2259 struct pid *pid; 2260 2261 /** 2262 * The ELSP only accepts two elements at a time, so we queue 2263 * context/tail pairs on a given queue (ring->execlist_queue) until the 2264 * hardware is available. The queue serves a double purpose: we also use 2265 * it to keep track of the up to 2 contexts currently in the hardware 2266 * (usually one in execution and the other queued up by the GPU): We 2267 * only remove elements from the head of the queue when the hardware 2268 * informs us that an element has been completed. 2269 * 2270 * All accesses to the queue are mediated by a spinlock 2271 * (ring->execlist_lock). 2272 */ 2273 2274 /** Execlist link in the submission queue.*/ 2275 struct list_head execlist_link; 2276 2277 /** Execlists no. of times this request has been sent to the ELSP */ 2278 int elsp_submitted; 2279 2280 }; 2281 2282 int i915_gem_request_alloc(struct intel_engine_cs *ring, 2283 struct intel_context *ctx, 2284 struct drm_i915_gem_request **req_out); 2285 void i915_gem_request_cancel(struct drm_i915_gem_request *req); 2286 void i915_gem_request_free(struct kref *req_ref); 2287 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, 2288 struct drm_file *file); 2289 2290 static inline uint32_t i915_gem_request_get_seqno(struct drm_i915_gem_request * req)2291 i915_gem_request_get_seqno(struct drm_i915_gem_request *req) 2292 { 2293 return req ? req->seqno : 0; 2294 } 2295 2296 static inline struct intel_engine_cs * i915_gem_request_get_ring(struct drm_i915_gem_request * req)2297 i915_gem_request_get_ring(struct drm_i915_gem_request *req) 2298 { 2299 return req ? req->ring : NULL; 2300 } 2301 2302 static inline struct drm_i915_gem_request * i915_gem_request_reference(struct drm_i915_gem_request * req)2303 i915_gem_request_reference(struct drm_i915_gem_request *req) 2304 { 2305 if (req) 2306 kref_get(&req->ref); 2307 return req; 2308 } 2309 2310 static inline void i915_gem_request_unreference(struct drm_i915_gem_request * req)2311 i915_gem_request_unreference(struct drm_i915_gem_request *req) 2312 { 2313 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); 2314 kref_put(&req->ref, i915_gem_request_free); 2315 } 2316 2317 static inline void i915_gem_request_unreference__unlocked(struct drm_i915_gem_request * req)2318 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req) 2319 { 2320 struct drm_device *dev; 2321 2322 if (!req) 2323 return; 2324 2325 dev = req->ring->dev; 2326 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex)) 2327 mutex_unlock(&dev->struct_mutex); 2328 } 2329 i915_gem_request_assign(struct drm_i915_gem_request ** pdst,struct drm_i915_gem_request * src)2330 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, 2331 struct drm_i915_gem_request *src) 2332 { 2333 if (src) 2334 i915_gem_request_reference(src); 2335 2336 if (*pdst) 2337 i915_gem_request_unreference(*pdst); 2338 2339 *pdst = src; 2340 } 2341 2342 /* 2343 * XXX: i915_gem_request_completed should be here but currently needs the 2344 * definition of i915_seqno_passed() which is below. It will be moved in 2345 * a later patch when the call to i915_seqno_passed() is obsoleted... 2346 */ 2347 2348 /* 2349 * A command that requires special handling by the command parser. 2350 */ 2351 struct drm_i915_cmd_descriptor { 2352 /* 2353 * Flags describing how the command parser processes the command. 2354 * 2355 * CMD_DESC_FIXED: The command has a fixed length if this is set, 2356 * a length mask if not set 2357 * CMD_DESC_SKIP: The command is allowed but does not follow the 2358 * standard length encoding for the opcode range in 2359 * which it falls 2360 * CMD_DESC_REJECT: The command is never allowed 2361 * CMD_DESC_REGISTER: The command should be checked against the 2362 * register whitelist for the appropriate ring 2363 * CMD_DESC_MASTER: The command is allowed if the submitting process 2364 * is the DRM master 2365 */ 2366 u32 flags; 2367 #define CMD_DESC_FIXED (1<<0) 2368 #define CMD_DESC_SKIP (1<<1) 2369 #define CMD_DESC_REJECT (1<<2) 2370 #define CMD_DESC_REGISTER (1<<3) 2371 #define CMD_DESC_BITMASK (1<<4) 2372 #define CMD_DESC_MASTER (1<<5) 2373 2374 /* 2375 * The command's unique identification bits and the bitmask to get them. 2376 * This isn't strictly the opcode field as defined in the spec and may 2377 * also include type, subtype, and/or subop fields. 2378 */ 2379 struct { 2380 u32 value; 2381 u32 mask; 2382 } cmd; 2383 2384 /* 2385 * The command's length. The command is either fixed length (i.e. does 2386 * not include a length field) or has a length field mask. The flag 2387 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has 2388 * a length mask. All command entries in a command table must include 2389 * length information. 2390 */ 2391 union { 2392 u32 fixed; 2393 u32 mask; 2394 } length; 2395 2396 /* 2397 * Describes where to find a register address in the command to check 2398 * against the ring's register whitelist. Only valid if flags has the 2399 * CMD_DESC_REGISTER bit set. 2400 * 2401 * A non-zero step value implies that the command may access multiple 2402 * registers in sequence (e.g. LRI), in that case step gives the 2403 * distance in dwords between individual offset fields. 2404 */ 2405 struct { 2406 u32 offset; 2407 u32 mask; 2408 u32 step; 2409 } reg; 2410 2411 #define MAX_CMD_DESC_BITMASKS 3 2412 /* 2413 * Describes command checks where a particular dword is masked and 2414 * compared against an expected value. If the command does not match 2415 * the expected value, the parser rejects it. Only valid if flags has 2416 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero 2417 * are valid. 2418 * 2419 * If the check specifies a non-zero condition_mask then the parser 2420 * only performs the check when the bits specified by condition_mask 2421 * are non-zero. 2422 */ 2423 struct { 2424 u32 offset; 2425 u32 mask; 2426 u32 expected; 2427 u32 condition_offset; 2428 u32 condition_mask; 2429 } bits[MAX_CMD_DESC_BITMASKS]; 2430 }; 2431 2432 /* 2433 * A table of commands requiring special handling by the command parser. 2434 * 2435 * Each ring has an array of tables. Each table consists of an array of command 2436 * descriptors, which must be sorted with command opcodes in ascending order. 2437 */ 2438 struct drm_i915_cmd_table { 2439 const struct drm_i915_cmd_descriptor *table; 2440 int count; 2441 }; 2442 2443 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ 2444 #define __I915__(p) ({ \ 2445 struct drm_i915_private *__p; \ 2446 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ 2447 __p = (struct drm_i915_private *)p; \ 2448 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ 2449 __p = to_i915((struct drm_device *)p); \ 2450 else \ 2451 BUILD_BUG(); \ 2452 __p; \ 2453 }) 2454 #define INTEL_INFO(p) (&__I915__(p)->info) 2455 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) 2456 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision) 2457 2458 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) 2459 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) 2460 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 2461 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) 2462 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 2463 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) 2464 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) 2465 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 2466 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 2467 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 2468 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) 2469 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 2470 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) 2471 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) 2472 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 2473 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 2474 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) 2475 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 2476 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ 2477 INTEL_DEVID(dev) == 0x0152 || \ 2478 INTEL_DEVID(dev) == 0x015a) 2479 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 2480 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) 2481 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 2482 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) 2483 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) 2484 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev)) 2485 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 2486 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ 2487 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) 2488 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ 2489 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ 2490 (INTEL_DEVID(dev) & 0xf) == 0xb || \ 2491 (INTEL_DEVID(dev) & 0xf) == 0xe)) 2492 /* ULX machines are also considered ULT. */ 2493 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \ 2494 (INTEL_DEVID(dev) & 0xf) == 0xe) 2495 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ 2496 (INTEL_DEVID(dev) & 0x00F0) == 0x0020) 2497 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ 2498 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) 2499 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ 2500 (INTEL_DEVID(dev) & 0x00F0) == 0x0020) 2501 /* ULX machines are also considered ULT. */ 2502 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ 2503 INTEL_DEVID(dev) == 0x0A1E) 2504 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \ 2505 INTEL_DEVID(dev) == 0x1913 || \ 2506 INTEL_DEVID(dev) == 0x1916 || \ 2507 INTEL_DEVID(dev) == 0x1921 || \ 2508 INTEL_DEVID(dev) == 0x1926) 2509 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ 2510 INTEL_DEVID(dev) == 0x1915 || \ 2511 INTEL_DEVID(dev) == 0x191E) 2512 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ 2513 (INTEL_DEVID(dev) & 0x00F0) == 0x0020) 2514 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ 2515 (INTEL_DEVID(dev) & 0x00F0) == 0x0030) 2516 2517 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) 2518 2519 #define SKL_REVID_A0 (0x0) 2520 #define SKL_REVID_B0 (0x1) 2521 #define SKL_REVID_C0 (0x2) 2522 #define SKL_REVID_D0 (0x3) 2523 #define SKL_REVID_E0 (0x4) 2524 #define SKL_REVID_F0 (0x5) 2525 2526 #define BXT_REVID_A0 (0x0) 2527 #define BXT_REVID_B0 (0x3) 2528 #define BXT_REVID_C0 (0x9) 2529 2530 /* 2531 * The genX designation typically refers to the render engine, so render 2532 * capability related checks should use IS_GEN, while display and other checks 2533 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 2534 * chips, etc.). 2535 */ 2536 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 2537 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 2538 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 2539 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 2540 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 2541 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 2542 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) 2543 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9) 2544 2545 #define RENDER_RING (1<<RCS) 2546 #define BSD_RING (1<<VCS) 2547 #define BLT_RING (1<<BCS) 2548 #define VEBOX_RING (1<<VECS) 2549 #define BSD2_RING (1<<VCS2) 2550 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) 2551 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) 2552 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) 2553 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) 2554 2555 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_INFO(dev_priv)->gen < 6) 2556 2557 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 2558 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ 2559 __I915__(dev)->ellc_size) 2560 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 2561 2562 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 2563 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) 2564 #define USES_PPGTT(dev) (i915.enable_ppgtt) 2565 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2) 2566 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3) 2567 2568 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 2569 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 2570 2571 /* 2572 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 2573 * All later gens can run the final buffer from the ppgtt 2574 */ 2575 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN7(dev_priv) 2576 2577 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 2578 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 2579 2580 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev) \ 2581 (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen == 9) 2582 2583 /* 2584 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts 2585 * even when in MSI mode. This results in spurious interrupt warnings if the 2586 * legacy irq no. is shared with another device. The kernel then disables that 2587 * interrupt source and so prevents the other device from working properly. 2588 */ 2589 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 2590 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 2591 2592 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 2593 * rows, which changed the alignment requirements and fence programming. 2594 */ 2595 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 2596 IS_I915GM(dev))) 2597 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 2598 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 2599 2600 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 2601 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 2602 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 2603 2604 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) 2605 2606 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ 2607 INTEL_INFO(dev)->gen >= 9) 2608 2609 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) 2610 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) 2611 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ 2612 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ 2613 IS_SKYLAKE(dev)) 2614 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ 2615 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ 2616 IS_SKYLAKE(dev)) 2617 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) 2618 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) 2619 2620 #define HAS_CSR(dev) (IS_GEN9(dev)) 2621 2622 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev)) 2623 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev)) 2624 2625 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \ 2626 INTEL_INFO(dev)->gen >= 8) 2627 2628 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \ 2629 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) 2630 2631 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 2632 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 2633 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 2634 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 2635 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 2636 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 2637 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 2638 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 2639 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 2640 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ 2641 2642 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) 2643 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) 2644 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 2645 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) 2646 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 2647 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 2648 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) 2649 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) 2650 2651 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) 2652 2653 /* DPF == dynamic parity feature */ 2654 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 2655 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) 2656 2657 #define GT_FREQUENCY_MULTIPLIER 50 2658 #define GEN9_FREQ_SCALER 3 2659 2660 #include "i915_trace.h" 2661 2662 extern const struct drm_ioctl_desc i915_ioctls[]; 2663 extern int i915_max_ioctl; 2664 2665 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state); 2666 extern int i915_resume_switcheroo(struct drm_device *dev); 2667 2668 /* i915_params.c */ 2669 struct i915_params { 2670 int modeset; 2671 int panel_ignore_lid; 2672 int semaphores; 2673 int lvds_channel_mode; 2674 int panel_use_ssc; 2675 int vbt_sdvo_panel_type; 2676 int enable_rc6; 2677 int enable_fbc; 2678 int enable_ppgtt; 2679 int enable_execlists; 2680 int enable_psr; 2681 unsigned int preliminary_hw_support; 2682 int disable_power_well; 2683 int enable_ips; 2684 int invert_brightness; 2685 int enable_cmd_parser; 2686 /* leave bools at the end to not create holes */ 2687 bool enable_hangcheck; 2688 bool fastboot; 2689 bool prefault_disable; 2690 bool load_detect_test; 2691 bool reset; 2692 bool disable_display; 2693 bool disable_vtd_wa; 2694 bool enable_guc_submission; 2695 int guc_log_level; 2696 int use_mmio_flip; 2697 int mmio_debug; 2698 bool verbose_state_checks; 2699 bool nuclear_pageflip; 2700 int edp_vswing; 2701 }; 2702 extern struct i915_params i915 __read_mostly; 2703 2704 /* i915_dma.c */ 2705 extern int i915_driver_load(struct drm_device *, unsigned long flags); 2706 extern int i915_driver_unload(struct drm_device *); 2707 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); 2708 extern void i915_driver_lastclose(struct drm_device * dev); 2709 extern void i915_driver_preclose(struct drm_device *dev, 2710 struct drm_file *file); 2711 extern void i915_driver_postclose(struct drm_device *dev, 2712 struct drm_file *file); 2713 #ifdef CONFIG_COMPAT 2714 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 2715 unsigned long arg); 2716 #endif 2717 extern int intel_gpu_reset(struct drm_device *dev); 2718 extern bool intel_has_gpu_reset(struct drm_device *dev); 2719 extern int i915_reset(struct drm_device *dev); 2720 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 2721 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 2722 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 2723 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 2724 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); 2725 void i915_firmware_load_error_print(const char *fw_path, int err); 2726 2727 /* intel_hotplug.c */ 2728 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask); 2729 void intel_hpd_init(struct drm_i915_private *dev_priv); 2730 void intel_hpd_init_work(struct drm_i915_private *dev_priv); 2731 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); 2732 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); 2733 2734 /* i915_irq.c */ 2735 void i915_queue_hangcheck(struct drm_device *dev); 2736 __printf(3, 4) 2737 void i915_handle_error(struct drm_device *dev, bool wedged, 2738 const char *fmt, ...); 2739 2740 extern void intel_irq_init(struct drm_i915_private *dev_priv); 2741 int intel_irq_install(struct drm_i915_private *dev_priv); 2742 void intel_irq_uninstall(struct drm_i915_private *dev_priv); 2743 2744 extern void intel_uncore_sanitize(struct drm_device *dev); 2745 extern void intel_uncore_early_sanitize(struct drm_device *dev, 2746 bool restore_forcewake); 2747 extern void intel_uncore_init(struct drm_device *dev); 2748 extern void intel_uncore_check_errors(struct drm_device *dev); 2749 extern void intel_uncore_fini(struct drm_device *dev); 2750 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); 2751 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); 2752 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, 2753 enum forcewake_domains domains); 2754 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, 2755 enum forcewake_domains domains); 2756 /* Like above but the caller must manage the uncore.lock itself. 2757 * Must be used with I915_READ_FW and friends. 2758 */ 2759 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, 2760 enum forcewake_domains domains); 2761 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, 2762 enum forcewake_domains domains); 2763 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); intel_vgpu_active(struct drm_device * dev)2764 static inline bool intel_vgpu_active(struct drm_device *dev) 2765 { 2766 return to_i915(dev)->vgpu.active; 2767 } 2768 2769 void 2770 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 2771 u32 status_mask); 2772 2773 void 2774 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 2775 u32 status_mask); 2776 2777 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); 2778 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); 2779 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, 2780 uint32_t mask, 2781 uint32_t bits); 2782 void 2783 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask); 2784 void 2785 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask); 2786 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, 2787 uint32_t interrupt_mask, 2788 uint32_t enabled_irq_mask); 2789 #define ibx_enable_display_interrupt(dev_priv, bits) \ 2790 ibx_display_interrupt_update((dev_priv), (bits), (bits)) 2791 #define ibx_disable_display_interrupt(dev_priv, bits) \ 2792 ibx_display_interrupt_update((dev_priv), (bits), 0) 2793 2794 /* i915_gem.c */ 2795 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 2796 struct drm_file *file_priv); 2797 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 2798 struct drm_file *file_priv); 2799 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2800 struct drm_file *file_priv); 2801 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 2802 struct drm_file *file_priv); 2803 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 2804 struct drm_file *file_priv); 2805 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2806 struct drm_file *file_priv); 2807 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 2808 struct drm_file *file_priv); 2809 void i915_gem_execbuffer_move_to_active(struct list_head *vmas, 2810 struct drm_i915_gem_request *req); 2811 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params); 2812 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, 2813 struct drm_i915_gem_execbuffer2 *args, 2814 struct list_head *vmas); 2815 int i915_gem_execbuffer(struct drm_device *dev, void *data, 2816 struct drm_file *file_priv); 2817 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 2818 struct drm_file *file_priv); 2819 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 2820 struct drm_file *file_priv); 2821 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 2822 struct drm_file *file); 2823 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 2824 struct drm_file *file); 2825 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 2826 struct drm_file *file_priv); 2827 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 2828 struct drm_file *file_priv); 2829 int i915_gem_set_tiling(struct drm_device *dev, void *data, 2830 struct drm_file *file_priv); 2831 int i915_gem_get_tiling(struct drm_device *dev, void *data, 2832 struct drm_file *file_priv); 2833 int i915_gem_init_userptr(struct drm_device *dev); 2834 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, 2835 struct drm_file *file); 2836 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 2837 struct drm_file *file_priv); 2838 int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 2839 struct drm_file *file_priv); 2840 void i915_gem_load(struct drm_device *dev); 2841 void *i915_gem_object_alloc(struct drm_device *dev); 2842 void i915_gem_object_free(struct drm_i915_gem_object *obj); 2843 void i915_gem_object_init(struct drm_i915_gem_object *obj, 2844 const struct drm_i915_gem_object_ops *ops); 2845 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 2846 size_t size); 2847 struct drm_i915_gem_object *i915_gem_object_create_from_data( 2848 struct drm_device *dev, const void *data, size_t size); 2849 void i915_gem_free_object(struct drm_gem_object *obj); 2850 void i915_gem_vma_destroy(struct i915_vma *vma); 2851 2852 /* Flags used by pin/bind&friends. */ 2853 #define PIN_MAPPABLE (1<<0) 2854 #define PIN_NONBLOCK (1<<1) 2855 #define PIN_GLOBAL (1<<2) 2856 #define PIN_OFFSET_BIAS (1<<3) 2857 #define PIN_USER (1<<4) 2858 #define PIN_UPDATE (1<<5) 2859 #define PIN_ZONE_4G (1<<6) 2860 #define PIN_HIGH (1<<7) 2861 #define PIN_OFFSET_MASK (~4095) 2862 int __must_check 2863 i915_gem_object_pin(struct drm_i915_gem_object *obj, 2864 struct i915_address_space *vm, 2865 uint32_t alignment, 2866 uint64_t flags); 2867 int __must_check 2868 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, 2869 const struct i915_ggtt_view *view, 2870 uint32_t alignment, 2871 uint64_t flags); 2872 2873 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, 2874 u32 flags); 2875 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma); 2876 int __must_check i915_vma_unbind(struct i915_vma *vma); 2877 /* 2878 * BEWARE: Do not use the function below unless you can _absolutely_ 2879 * _guarantee_ VMA in question is _not in use_ anywhere. 2880 */ 2881 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma); 2882 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); 2883 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); 2884 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 2885 2886 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, 2887 int *needs_clflush); 2888 2889 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); 2890 __sg_page_count(struct scatterlist * sg)2891 static inline int __sg_page_count(struct scatterlist *sg) 2892 { 2893 return sg->length >> PAGE_SHIFT; 2894 } 2895 2896 static inline struct page * i915_gem_object_get_page(struct drm_i915_gem_object * obj,int n)2897 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) 2898 { 2899 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) 2900 return NULL; 2901 2902 if (n < obj->get_page.last) { 2903 obj->get_page.sg = obj->pages->sgl; 2904 obj->get_page.last = 0; 2905 } 2906 2907 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { 2908 obj->get_page.last += __sg_page_count(obj->get_page.sg++); 2909 if (unlikely(sg_is_chain(obj->get_page.sg))) 2910 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); 2911 } 2912 2913 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); 2914 } 2915 i915_gem_object_pin_pages(struct drm_i915_gem_object * obj)2916 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 2917 { 2918 BUG_ON(obj->pages == NULL); 2919 obj->pages_pin_count++; 2920 } i915_gem_object_unpin_pages(struct drm_i915_gem_object * obj)2921 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 2922 { 2923 BUG_ON(obj->pages_pin_count == 0); 2924 obj->pages_pin_count--; 2925 } 2926 2927 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 2928 int i915_gem_object_sync(struct drm_i915_gem_object *obj, 2929 struct intel_engine_cs *to, 2930 struct drm_i915_gem_request **to_req); 2931 void i915_vma_move_to_active(struct i915_vma *vma, 2932 struct drm_i915_gem_request *req); 2933 int i915_gem_dumb_create(struct drm_file *file_priv, 2934 struct drm_device *dev, 2935 struct drm_mode_create_dumb *args); 2936 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 2937 uint32_t handle, uint64_t *offset); 2938 /** 2939 * Returns true if seq1 is later than seq2. 2940 */ 2941 static inline bool i915_seqno_passed(uint32_t seq1,uint32_t seq2)2942 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 2943 { 2944 return (int32_t)(seq1 - seq2) >= 0; 2945 } 2946 i915_gem_request_started(struct drm_i915_gem_request * req,bool lazy_coherency)2947 static inline bool i915_gem_request_started(struct drm_i915_gem_request *req, 2948 bool lazy_coherency) 2949 { 2950 u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency); 2951 return i915_seqno_passed(seqno, req->previous_seqno); 2952 } 2953 i915_gem_request_completed(struct drm_i915_gem_request * req,bool lazy_coherency)2954 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req, 2955 bool lazy_coherency) 2956 { 2957 u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency); 2958 return i915_seqno_passed(seqno, req->seqno); 2959 } 2960 2961 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); 2962 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); 2963 2964 struct drm_i915_gem_request * 2965 i915_gem_find_active_request(struct intel_engine_cs *ring); 2966 2967 bool i915_gem_retire_requests(struct drm_device *dev); 2968 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); 2969 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, 2970 bool interruptible); 2971 i915_reset_in_progress(struct i915_gpu_error * error)2972 static inline bool i915_reset_in_progress(struct i915_gpu_error *error) 2973 { 2974 return unlikely(atomic_read(&error->reset_counter) 2975 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); 2976 } 2977 i915_terminally_wedged(struct i915_gpu_error * error)2978 static inline bool i915_terminally_wedged(struct i915_gpu_error *error) 2979 { 2980 return atomic_read(&error->reset_counter) & I915_WEDGED; 2981 } 2982 i915_reset_count(struct i915_gpu_error * error)2983 static inline u32 i915_reset_count(struct i915_gpu_error *error) 2984 { 2985 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; 2986 } 2987 i915_stop_ring_allow_ban(struct drm_i915_private * dev_priv)2988 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) 2989 { 2990 return dev_priv->gpu_error.stop_rings == 0 || 2991 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; 2992 } 2993 i915_stop_ring_allow_warn(struct drm_i915_private * dev_priv)2994 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) 2995 { 2996 return dev_priv->gpu_error.stop_rings == 0 || 2997 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; 2998 } 2999 3000 void i915_gem_reset(struct drm_device *dev); 3001 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); 3002 int __must_check i915_gem_init(struct drm_device *dev); 3003 int i915_gem_init_rings(struct drm_device *dev); 3004 int __must_check i915_gem_init_hw(struct drm_device *dev); 3005 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice); 3006 void i915_gem_init_swizzling(struct drm_device *dev); 3007 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 3008 int __must_check i915_gpu_idle(struct drm_device *dev); 3009 int __must_check i915_gem_suspend(struct drm_device *dev); 3010 void __i915_add_request(struct drm_i915_gem_request *req, 3011 struct drm_i915_gem_object *batch_obj, 3012 bool flush_caches); 3013 #define i915_add_request(req) \ 3014 __i915_add_request(req, NULL, true) 3015 #define i915_add_request_no_flush(req) \ 3016 __i915_add_request(req, NULL, false) 3017 int __i915_wait_request(struct drm_i915_gem_request *req, 3018 unsigned reset_counter, 3019 bool interruptible, 3020 s64 *timeout, 3021 struct intel_rps_client *rps); 3022 int __must_check i915_wait_request(struct drm_i915_gem_request *req); 3023 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 3024 int __must_check 3025 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, 3026 bool readonly); 3027 int __must_check 3028 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 3029 bool write); 3030 int __must_check 3031 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 3032 int __must_check 3033 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 3034 u32 alignment, 3035 struct intel_engine_cs *pipelined, 3036 struct drm_i915_gem_request **pipelined_request, 3037 const struct i915_ggtt_view *view); 3038 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, 3039 const struct i915_ggtt_view *view); 3040 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, 3041 int align); 3042 int i915_gem_open(struct drm_device *dev, struct drm_file *file); 3043 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 3044 3045 uint32_t 3046 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); 3047 uint32_t 3048 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, 3049 int tiling_mode, bool fenced); 3050 3051 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 3052 enum i915_cache_level cache_level); 3053 3054 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 3055 struct dma_buf *dma_buf); 3056 3057 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 3058 struct drm_gem_object *gem_obj, int flags); 3059 3060 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, 3061 const struct i915_ggtt_view *view); 3062 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, 3063 struct i915_address_space *vm); 3064 static inline u64 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object * o)3065 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o) 3066 { 3067 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal); 3068 } 3069 3070 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); 3071 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, 3072 const struct i915_ggtt_view *view); 3073 bool i915_gem_obj_bound(struct drm_i915_gem_object *o, 3074 struct i915_address_space *vm); 3075 3076 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, 3077 struct i915_address_space *vm); 3078 struct i915_vma * 3079 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, 3080 struct i915_address_space *vm); 3081 struct i915_vma * 3082 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, 3083 const struct i915_ggtt_view *view); 3084 3085 struct i915_vma * 3086 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, 3087 struct i915_address_space *vm); 3088 struct i915_vma * 3089 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, 3090 const struct i915_ggtt_view *view); 3091 3092 static inline struct i915_vma * i915_gem_obj_to_ggtt(struct drm_i915_gem_object * obj)3093 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) 3094 { 3095 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal); 3096 } 3097 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj); 3098 3099 /* Some GGTT VM helpers */ 3100 #define i915_obj_to_ggtt(obj) \ 3101 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) i915_is_ggtt(struct i915_address_space * vm)3102 static inline bool i915_is_ggtt(struct i915_address_space *vm) 3103 { 3104 struct i915_address_space *ggtt = 3105 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; 3106 return vm == ggtt; 3107 } 3108 3109 static inline struct i915_hw_ppgtt * i915_vm_to_ppgtt(struct i915_address_space * vm)3110 i915_vm_to_ppgtt(struct i915_address_space *vm) 3111 { 3112 WARN_ON(i915_is_ggtt(vm)); 3113 3114 return container_of(vm, struct i915_hw_ppgtt, base); 3115 } 3116 3117 i915_gem_obj_ggtt_bound(struct drm_i915_gem_object * obj)3118 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) 3119 { 3120 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal); 3121 } 3122 3123 static inline unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object * obj)3124 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) 3125 { 3126 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); 3127 } 3128 3129 static inline int __must_check i915_gem_obj_ggtt_pin(struct drm_i915_gem_object * obj,uint32_t alignment,unsigned flags)3130 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, 3131 uint32_t alignment, 3132 unsigned flags) 3133 { 3134 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), 3135 alignment, flags | PIN_GLOBAL); 3136 } 3137 3138 static inline int i915_gem_object_ggtt_unbind(struct drm_i915_gem_object * obj)3139 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) 3140 { 3141 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); 3142 } 3143 3144 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, 3145 const struct i915_ggtt_view *view); 3146 static inline void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object * obj)3147 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) 3148 { 3149 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal); 3150 } 3151 3152 /* i915_gem_fence.c */ 3153 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 3154 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 3155 3156 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); 3157 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); 3158 3159 void i915_gem_restore_fences(struct drm_device *dev); 3160 3161 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 3162 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 3163 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 3164 3165 /* i915_gem_context.c */ 3166 int __must_check i915_gem_context_init(struct drm_device *dev); 3167 void i915_gem_context_fini(struct drm_device *dev); 3168 void i915_gem_context_reset(struct drm_device *dev); 3169 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); 3170 int i915_gem_context_enable(struct drm_i915_gem_request *req); 3171 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 3172 int i915_switch_context(struct drm_i915_gem_request *req); 3173 struct intel_context * 3174 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); 3175 void i915_gem_context_free(struct kref *ctx_ref); 3176 struct drm_i915_gem_object * 3177 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); i915_gem_context_reference(struct intel_context * ctx)3178 static inline void i915_gem_context_reference(struct intel_context *ctx) 3179 { 3180 kref_get(&ctx->ref); 3181 } 3182 i915_gem_context_unreference(struct intel_context * ctx)3183 static inline void i915_gem_context_unreference(struct intel_context *ctx) 3184 { 3185 kref_put(&ctx->ref, i915_gem_context_free); 3186 } 3187 i915_gem_context_is_default(const struct intel_context * c)3188 static inline bool i915_gem_context_is_default(const struct intel_context *c) 3189 { 3190 return c->user_handle == DEFAULT_CONTEXT_HANDLE; 3191 } 3192 3193 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 3194 struct drm_file *file); 3195 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 3196 struct drm_file *file); 3197 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, 3198 struct drm_file *file_priv); 3199 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, 3200 struct drm_file *file_priv); 3201 3202 /* i915_gem_evict.c */ 3203 int __must_check i915_gem_evict_something(struct drm_device *dev, 3204 struct i915_address_space *vm, 3205 int min_size, 3206 unsigned alignment, 3207 unsigned cache_level, 3208 unsigned long start, 3209 unsigned long end, 3210 unsigned flags); 3211 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); 3212 3213 /* belongs in i915_gem_gtt.h */ i915_gem_chipset_flush(struct drm_device * dev)3214 static inline void i915_gem_chipset_flush(struct drm_device *dev) 3215 { 3216 if (INTEL_INFO(dev)->gen < 6) 3217 intel_gtt_chipset_flush(); 3218 } 3219 3220 /* i915_gem_stolen.c */ 3221 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, 3222 struct drm_mm_node *node, u64 size, 3223 unsigned alignment); 3224 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, 3225 struct drm_mm_node *node, u64 size, 3226 unsigned alignment, u64 start, 3227 u64 end); 3228 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, 3229 struct drm_mm_node *node); 3230 int i915_gem_init_stolen(struct drm_device *dev); 3231 void i915_gem_cleanup_stolen(struct drm_device *dev); 3232 struct drm_i915_gem_object * 3233 i915_gem_object_create_stolen(struct drm_device *dev, u32 size); 3234 struct drm_i915_gem_object * 3235 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, 3236 u32 stolen_offset, 3237 u32 gtt_offset, 3238 u32 size); 3239 3240 /* i915_gem_shrinker.c */ 3241 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, 3242 unsigned long target, 3243 unsigned flags); 3244 #define I915_SHRINK_PURGEABLE 0x1 3245 #define I915_SHRINK_UNBOUND 0x2 3246 #define I915_SHRINK_BOUND 0x4 3247 #define I915_SHRINK_ACTIVE 0x8 3248 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); 3249 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); 3250 3251 3252 /* i915_gem_tiling.c */ i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object * obj)3253 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 3254 { 3255 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 3256 3257 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 3258 obj->tiling_mode != I915_TILING_NONE; 3259 } 3260 3261 /* i915_gem_debug.c */ 3262 #if WATCH_LISTS 3263 int i915_verify_lists(struct drm_device *dev); 3264 #else 3265 #define i915_verify_lists(dev) 0 3266 #endif 3267 3268 /* i915_debugfs.c */ 3269 int i915_debugfs_init(struct drm_minor *minor); 3270 void i915_debugfs_cleanup(struct drm_minor *minor); 3271 #ifdef CONFIG_DEBUG_FS 3272 int i915_debugfs_connector_add(struct drm_connector *connector); 3273 void intel_display_crc_init(struct drm_device *dev); 3274 #else i915_debugfs_connector_add(struct drm_connector * connector)3275 static inline int i915_debugfs_connector_add(struct drm_connector *connector) 3276 { return 0; } intel_display_crc_init(struct drm_device * dev)3277 static inline void intel_display_crc_init(struct drm_device *dev) {} 3278 #endif 3279 3280 /* i915_gpu_error.c */ 3281 __printf(2, 3) 3282 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 3283 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, 3284 const struct i915_error_state_file_priv *error); 3285 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, 3286 struct drm_i915_private *i915, 3287 size_t count, loff_t pos); i915_error_state_buf_release(struct drm_i915_error_state_buf * eb)3288 static inline void i915_error_state_buf_release( 3289 struct drm_i915_error_state_buf *eb) 3290 { 3291 kfree(eb->buf); 3292 } 3293 void i915_capture_error_state(struct drm_device *dev, bool wedge, 3294 const char *error_msg); 3295 void i915_error_state_get(struct drm_device *dev, 3296 struct i915_error_state_file_priv *error_priv); 3297 void i915_error_state_put(struct i915_error_state_file_priv *error_priv); 3298 void i915_destroy_error_state(struct drm_device *dev); 3299 3300 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); 3301 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 3302 3303 /* i915_cmd_parser.c */ 3304 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); 3305 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); 3306 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); 3307 bool i915_needs_cmd_parser(struct intel_engine_cs *ring); 3308 int i915_parse_cmds(struct intel_context *cxt, 3309 struct intel_engine_cs *ring, 3310 struct drm_i915_gem_object *batch_obj, 3311 u64 user_batch_start, 3312 u32 batch_start_offset, 3313 u32 batch_len, 3314 struct drm_i915_gem_object *shadow_batch_obj, 3315 u64 shadow_batch_start); 3316 3317 3318 /* i915_suspend.c */ 3319 extern int i915_save_state(struct drm_device *dev); 3320 extern int i915_restore_state(struct drm_device *dev); 3321 3322 /* i915_sysfs.c */ 3323 void i915_setup_sysfs(struct drm_device *dev_priv); 3324 void i915_teardown_sysfs(struct drm_device *dev_priv); 3325 3326 /* intel_i2c.c */ 3327 extern int intel_setup_gmbus(struct drm_device *dev); 3328 extern void intel_teardown_gmbus(struct drm_device *dev); 3329 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, 3330 unsigned int pin); 3331 3332 extern struct i2c_adapter * 3333 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); 3334 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 3335 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); intel_gmbus_is_forced_bit(struct i2c_adapter * adapter)3336 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 3337 { 3338 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 3339 } 3340 extern void intel_i2c_reset(struct drm_device *dev); 3341 3342 /* intel_bios.c */ 3343 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); 3344 3345 /* intel_opregion.c */ 3346 #ifdef CONFIG_ACPI 3347 extern int intel_opregion_setup(struct drm_device *dev); 3348 extern void intel_opregion_init(struct drm_device *dev); 3349 extern void intel_opregion_fini(struct drm_device *dev); 3350 extern void intel_opregion_asle_intr(struct drm_device *dev); 3351 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, 3352 bool enable); 3353 extern int intel_opregion_notify_adapter(struct drm_device *dev, 3354 pci_power_t state); 3355 #else intel_opregion_setup(struct drm_device * dev)3356 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } intel_opregion_init(struct drm_device * dev)3357 static inline void intel_opregion_init(struct drm_device *dev) { return; } intel_opregion_fini(struct drm_device * dev)3358 static inline void intel_opregion_fini(struct drm_device *dev) { return; } intel_opregion_asle_intr(struct drm_device * dev)3359 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 3360 static inline int intel_opregion_notify_encoder(struct intel_encoder * intel_encoder,bool enable)3361 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) 3362 { 3363 return 0; 3364 } 3365 static inline int intel_opregion_notify_adapter(struct drm_device * dev,pci_power_t state)3366 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) 3367 { 3368 return 0; 3369 } 3370 #endif 3371 3372 /* intel_acpi.c */ 3373 #ifdef CONFIG_ACPI 3374 extern void intel_register_dsm_handler(void); 3375 extern void intel_unregister_dsm_handler(void); 3376 #else intel_register_dsm_handler(void)3377 static inline void intel_register_dsm_handler(void) { return; } intel_unregister_dsm_handler(void)3378 static inline void intel_unregister_dsm_handler(void) { return; } 3379 #endif /* CONFIG_ACPI */ 3380 3381 /* modesetting */ 3382 extern void intel_modeset_init_hw(struct drm_device *dev); 3383 extern void intel_modeset_init(struct drm_device *dev); 3384 extern void intel_modeset_gem_init(struct drm_device *dev); 3385 extern void intel_modeset_cleanup(struct drm_device *dev); 3386 extern void intel_connector_unregister(struct intel_connector *); 3387 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 3388 extern void intel_display_resume(struct drm_device *dev); 3389 extern void i915_redisable_vga(struct drm_device *dev); 3390 extern void i915_redisable_vga_power_on(struct drm_device *dev); 3391 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 3392 extern void intel_init_pch_refclk(struct drm_device *dev); 3393 extern void intel_set_rps(struct drm_device *dev, u8 val); 3394 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, 3395 bool enable); 3396 extern void intel_detect_pch(struct drm_device *dev); 3397 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 3398 extern int intel_enable_rc6(const struct drm_device *dev); 3399 3400 extern bool i915_semaphore_is_enabled(struct drm_device *dev); 3401 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 3402 struct drm_file *file); 3403 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, 3404 struct drm_file *file); 3405 3406 /* overlay */ 3407 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 3408 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, 3409 struct intel_overlay_error_state *error); 3410 3411 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 3412 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 3413 struct drm_device *dev, 3414 struct intel_display_error_state *error); 3415 3416 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); 3417 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); 3418 3419 /* intel_sideband.c */ 3420 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); 3421 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); 3422 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); 3423 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); 3424 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3425 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); 3426 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3427 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); 3428 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3429 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); 3430 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3431 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); 3432 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3433 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); 3434 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); 3435 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, 3436 enum intel_sbi_destination destination); 3437 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 3438 enum intel_sbi_destination destination); 3439 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); 3440 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3441 3442 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); 3443 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); 3444 3445 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) 3446 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) 3447 3448 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) 3449 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) 3450 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) 3451 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) 3452 3453 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) 3454 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) 3455 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) 3456 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) 3457 3458 /* Be very careful with read/write 64-bit values. On 32-bit machines, they 3459 * will be implemented using 2 32-bit writes in an arbitrary order with 3460 * an arbitrary delay between them. This can cause the hardware to 3461 * act upon the intermediate value, possibly leading to corruption and 3462 * machine death. You have been warned. 3463 */ 3464 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) 3465 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) 3466 3467 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ 3468 u32 upper, lower, old_upper, loop = 0; \ 3469 upper = I915_READ(upper_reg); \ 3470 do { \ 3471 old_upper = upper; \ 3472 lower = I915_READ(lower_reg); \ 3473 upper = I915_READ(upper_reg); \ 3474 } while (upper != old_upper && loop++ < 2); \ 3475 (u64)upper << 32 | lower; }) 3476 3477 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 3478 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 3479 3480 /* These are untraced mmio-accessors that are only valid to be used inside 3481 * criticial sections inside IRQ handlers where forcewake is explicitly 3482 * controlled. 3483 * Think twice, and think again, before using these. 3484 * Note: Should only be used between intel_uncore_forcewake_irqlock() and 3485 * intel_uncore_forcewake_irqunlock(). 3486 */ 3487 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__)) 3488 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__)) 3489 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) 3490 3491 /* "Broadcast RGB" property */ 3492 #define INTEL_BROADCAST_RGB_AUTO 0 3493 #define INTEL_BROADCAST_RGB_FULL 1 3494 #define INTEL_BROADCAST_RGB_LIMITED 2 3495 i915_vgacntrl_reg(struct drm_device * dev)3496 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) 3497 { 3498 if (IS_VALLEYVIEW(dev)) 3499 return VLV_VGACNTRL; 3500 else if (INTEL_INFO(dev)->gen >= 5) 3501 return CPU_VGACNTRL; 3502 else 3503 return VGACNTRL; 3504 } 3505 msecs_to_jiffies_timeout(const unsigned int m)3506 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) 3507 { 3508 unsigned long j = msecs_to_jiffies(m); 3509 3510 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 3511 } 3512 nsecs_to_jiffies_timeout(const u64 n)3513 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 3514 { 3515 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 3516 } 3517 3518 static inline unsigned long timespec_to_jiffies_timeout(const struct timespec * value)3519 timespec_to_jiffies_timeout(const struct timespec *value) 3520 { 3521 unsigned long j = timespec_to_jiffies(value); 3522 3523 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 3524 } 3525 3526 /* 3527 * If you need to wait X milliseconds between events A and B, but event B 3528 * doesn't happen exactly after event A, you record the timestamp (jiffies) of 3529 * when event A happened, then just before event B you call this function and 3530 * pass the timestamp as the first argument, and X as the second argument. 3531 */ 3532 static inline void wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies,int to_wait_ms)3533 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) 3534 { 3535 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; 3536 3537 /* 3538 * Don't re-read the value of "jiffies" every time since it may change 3539 * behind our back and break the math. 3540 */ 3541 tmp_jiffies = jiffies; 3542 target_jiffies = timestamp_jiffies + 3543 msecs_to_jiffies_timeout(to_wait_ms); 3544 3545 if (time_after(target_jiffies, tmp_jiffies)) { 3546 remaining_jiffies = target_jiffies - tmp_jiffies; 3547 while (remaining_jiffies) 3548 remaining_jiffies = 3549 schedule_timeout_uninterruptible(remaining_jiffies); 3550 } 3551 } 3552 i915_trace_irq_get(struct intel_engine_cs * ring,struct drm_i915_gem_request * req)3553 static inline void i915_trace_irq_get(struct intel_engine_cs *ring, 3554 struct drm_i915_gem_request *req) 3555 { 3556 if (ring->trace_irq_req == NULL && ring->irq_get(ring)) 3557 i915_gem_request_assign(&ring->trace_irq_req, req); 3558 } 3559 3560 #endif 3561