1 #ifndef __NVKM_GRCTX_H__
2 #define __NVKM_GRCTX_H__
3 #include <core/gpuobj.h>
4
5 struct nvkm_grctx {
6 struct nvkm_device *device;
7
8 enum {
9 NVKM_GRCTX_PROG,
10 NVKM_GRCTX_VALS
11 } mode;
12 u32 *ucode;
13 struct nvkm_gpuobj *data;
14
15 u32 ctxprog_max;
16 u32 ctxprog_len;
17 u32 ctxprog_reg;
18 int ctxprog_label[32];
19 u32 ctxvals_pos;
20 u32 ctxvals_base;
21 };
22
23 static inline void
cp_out(struct nvkm_grctx * ctx,u32 inst)24 cp_out(struct nvkm_grctx *ctx, u32 inst)
25 {
26 u32 *ctxprog = ctx->ucode;
27
28 if (ctx->mode != NVKM_GRCTX_PROG)
29 return;
30
31 BUG_ON(ctx->ctxprog_len == ctx->ctxprog_max);
32 ctxprog[ctx->ctxprog_len++] = inst;
33 }
34
35 static inline void
cp_lsr(struct nvkm_grctx * ctx,u32 val)36 cp_lsr(struct nvkm_grctx *ctx, u32 val)
37 {
38 cp_out(ctx, CP_LOAD_SR | val);
39 }
40
41 static inline void
cp_ctx(struct nvkm_grctx * ctx,u32 reg,u32 length)42 cp_ctx(struct nvkm_grctx *ctx, u32 reg, u32 length)
43 {
44 ctx->ctxprog_reg = (reg - 0x00400000) >> 2;
45
46 ctx->ctxvals_base = ctx->ctxvals_pos;
47 ctx->ctxvals_pos = ctx->ctxvals_base + length;
48
49 if (length > (CP_CTX_COUNT >> CP_CTX_COUNT_SHIFT)) {
50 cp_lsr(ctx, length);
51 length = 0;
52 }
53
54 cp_out(ctx, CP_CTX | (length << CP_CTX_COUNT_SHIFT) | ctx->ctxprog_reg);
55 }
56
57 static inline void
cp_name(struct nvkm_grctx * ctx,int name)58 cp_name(struct nvkm_grctx *ctx, int name)
59 {
60 u32 *ctxprog = ctx->ucode;
61 int i;
62
63 if (ctx->mode != NVKM_GRCTX_PROG)
64 return;
65
66 ctx->ctxprog_label[name] = ctx->ctxprog_len;
67 for (i = 0; i < ctx->ctxprog_len; i++) {
68 if ((ctxprog[i] & 0xfff00000) != 0xff400000)
69 continue;
70 if ((ctxprog[i] & CP_BRA_IP) != ((name) << CP_BRA_IP_SHIFT))
71 continue;
72 ctxprog[i] = (ctxprog[i] & 0x00ff00ff) |
73 (ctx->ctxprog_len << CP_BRA_IP_SHIFT);
74 }
75 }
76
77 static inline void
_cp_bra(struct nvkm_grctx * ctx,u32 mod,int flag,int state,int name)78 _cp_bra(struct nvkm_grctx *ctx, u32 mod, int flag, int state, int name)
79 {
80 int ip = 0;
81
82 if (mod != 2) {
83 ip = ctx->ctxprog_label[name] << CP_BRA_IP_SHIFT;
84 if (ip == 0)
85 ip = 0xff000000 | (name << CP_BRA_IP_SHIFT);
86 }
87
88 cp_out(ctx, CP_BRA | (mod << 18) | ip | flag |
89 (state ? 0 : CP_BRA_IF_CLEAR));
90 }
91 #define cp_bra(c, f, s, n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
92 #define cp_cal(c, f, s, n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
93 #define cp_ret(c, f, s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0)
94
95 static inline void
_cp_wait(struct nvkm_grctx * ctx,int flag,int state)96 _cp_wait(struct nvkm_grctx *ctx, int flag, int state)
97 {
98 cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0));
99 }
100 #define cp_wait(c, f, s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
101
102 static inline void
_cp_set(struct nvkm_grctx * ctx,int flag,int state)103 _cp_set(struct nvkm_grctx *ctx, int flag, int state)
104 {
105 cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0));
106 }
107 #define cp_set(c, f, s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
108
109 static inline void
cp_pos(struct nvkm_grctx * ctx,int offset)110 cp_pos(struct nvkm_grctx *ctx, int offset)
111 {
112 ctx->ctxvals_pos = offset;
113 ctx->ctxvals_base = ctx->ctxvals_pos;
114
115 cp_lsr(ctx, ctx->ctxvals_pos);
116 cp_out(ctx, CP_SET_CONTEXT_POINTER);
117 }
118
119 static inline void
gr_def(struct nvkm_grctx * ctx,u32 reg,u32 val)120 gr_def(struct nvkm_grctx *ctx, u32 reg, u32 val)
121 {
122 if (ctx->mode != NVKM_GRCTX_VALS)
123 return;
124
125 reg = (reg - 0x00400000) / 4;
126 reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base;
127
128 nvkm_wo32(ctx->data, reg * 4, val);
129 }
130 #endif
131