1 /*
2 * DaVinci Ethernet Medium Access Controller
3 *
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
5 *
6 * Copyright (C) 2009 Texas Instruments.
7 *
8 * ---------------------------------------------------------------------------
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
24 * History:
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
29 * PHY layer usage
30 */
31
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/sched.h>
35 #include <linux/string.h>
36 #include <linux/timer.h>
37 #include <linux/errno.h>
38 #include <linux/in.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
41 #include <linux/mm.h>
42 #include <linux/interrupt.h>
43 #include <linux/init.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <linux/skbuff.h>
47 #include <linux/ethtool.h>
48 #include <linux/highmem.h>
49 #include <linux/proc_fs.h>
50 #include <linux/ctype.h>
51 #include <linux/spinlock.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/clk.h>
54 #include <linux/platform_device.h>
55 #include <linux/regmap.h>
56 #include <linux/semaphore.h>
57 #include <linux/phy.h>
58 #include <linux/bitops.h>
59 #include <linux/io.h>
60 #include <linux/uaccess.h>
61 #include <linux/pm_runtime.h>
62 #include <linux/davinci_emac.h>
63 #include <linux/of.h>
64 #include <linux/of_address.h>
65 #include <linux/of_device.h>
66 #include <linux/of_mdio.h>
67 #include <linux/of_irq.h>
68 #include <linux/of_net.h>
69 #include <linux/mfd/syscon.h>
70
71 #include <asm/irq.h>
72 #include <asm/page.h>
73
74 #include "cpsw.h"
75 #include "davinci_cpdma.h"
76
77 static int debug_level;
78 module_param(debug_level, int, 0);
79 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
80
81 /* Netif debug messages possible */
82 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
83 NETIF_MSG_PROBE | \
84 NETIF_MSG_LINK | \
85 NETIF_MSG_TIMER | \
86 NETIF_MSG_IFDOWN | \
87 NETIF_MSG_IFUP | \
88 NETIF_MSG_RX_ERR | \
89 NETIF_MSG_TX_ERR | \
90 NETIF_MSG_TX_QUEUED | \
91 NETIF_MSG_INTR | \
92 NETIF_MSG_TX_DONE | \
93 NETIF_MSG_RX_STATUS | \
94 NETIF_MSG_PKTDATA | \
95 NETIF_MSG_HW | \
96 NETIF_MSG_WOL)
97
98 /* version info */
99 #define EMAC_MAJOR_VERSION 6
100 #define EMAC_MINOR_VERSION 1
101 #define EMAC_MODULE_VERSION "6.1"
102 MODULE_VERSION(EMAC_MODULE_VERSION);
103 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
104
105 /* Configuration items */
106 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */
107 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
108 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
109 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
110 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
111 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
112 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */
113 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */
114 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
115 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
116 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
117 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
118
119 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
120 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
121
122 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
123 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
124 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
125 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
126 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
127 #define EMAC_DEF_RX_NUM_DESC (128)
128 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
129 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
130 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
131
132 /* Buffer descriptor parameters */
133 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
134 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
135
136 /* EMAC register related defines */
137 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
138 #define EMAC_NUM_MULTICAST_BITS (64)
139 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
140 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
141 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
142 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
143 #define EMAC_INT_MASK_CLEAR (0xFF)
144
145 /* RX MBP register bit positions */
146 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
147 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
148 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
149 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
150 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
151 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
152 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
153 #define EMAC_RXMBP_PROMCH_SHIFT (16)
154 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
155 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
156 #define EMAC_RXMBP_BROADCH_SHIFT (8)
157 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
158 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
159 #define EMAC_RXMBP_MULTICH_SHIFT (0)
160 #define EMAC_RXMBP_MULTICH_MASK (0x7)
161 #define EMAC_RXMBP_CHMASK (0x7)
162
163 /* EMAC register definitions/bit maps used */
164 # define EMAC_MBP_RXPROMISC (0x00200000)
165 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
166 # define EMAC_MBP_RXBCAST (0x00002000)
167 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
168 # define EMAC_MBP_RXMCAST (0x00000020)
169 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
170
171 /* EMAC mac_control register */
172 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
173 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
174 #define EMAC_MACCONTROL_GMIIEN BIT(5)
175 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
176 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
177 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
178
179 /* GIGABIT MODE related bits */
180 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
181 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
182
183 /* EMAC mac_status register */
184 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
185 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
186 #define EMAC_MACSTATUS_TXERRCH_MASK (0x70000)
187 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
188 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
189 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
190 #define EMAC_MACSTATUS_RXERRCH_MASK (0x700)
191 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
192
193 /* EMAC RX register masks */
194 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
195 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
196
197 /* MAC_IN_VECTOR (0x180) register bit fields */
198 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
199 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
200 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
201 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
202
203 /** NOTE:: For DM646x the IN_VECTOR has changed */
204 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
205 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
206 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
207 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
208
209 /* CPPI bit positions */
210 #define EMAC_CPPI_SOP_BIT BIT(31)
211 #define EMAC_CPPI_EOP_BIT BIT(30)
212 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
213 #define EMAC_CPPI_EOQ_BIT BIT(28)
214 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
215 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
216 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
217 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
218 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
219
220 /* Max hardware defines */
221 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
222 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
223
224 /* EMAC Peripheral Device Register Memory Layout structure */
225 #define EMAC_MACINVECTOR 0x90
226
227 #define EMAC_DM646X_MACEOIVECTOR 0x94
228
229 #define EMAC_MACINTSTATRAW 0xB0
230 #define EMAC_MACINTSTATMASKED 0xB4
231 #define EMAC_MACINTMASKSET 0xB8
232 #define EMAC_MACINTMASKCLEAR 0xBC
233
234 #define EMAC_RXMBPENABLE 0x100
235 #define EMAC_RXUNICASTSET 0x104
236 #define EMAC_RXUNICASTCLEAR 0x108
237 #define EMAC_RXMAXLEN 0x10C
238 #define EMAC_RXBUFFEROFFSET 0x110
239 #define EMAC_RXFILTERLOWTHRESH 0x114
240
241 #define EMAC_MACCONTROL 0x160
242 #define EMAC_MACSTATUS 0x164
243 #define EMAC_EMCONTROL 0x168
244 #define EMAC_FIFOCONTROL 0x16C
245 #define EMAC_MACCONFIG 0x170
246 #define EMAC_SOFTRESET 0x174
247 #define EMAC_MACSRCADDRLO 0x1D0
248 #define EMAC_MACSRCADDRHI 0x1D4
249 #define EMAC_MACHASH1 0x1D8
250 #define EMAC_MACHASH2 0x1DC
251 #define EMAC_MACADDRLO 0x500
252 #define EMAC_MACADDRHI 0x504
253 #define EMAC_MACINDEX 0x508
254
255 /* EMAC statistics registers */
256 #define EMAC_RXGOODFRAMES 0x200
257 #define EMAC_RXBCASTFRAMES 0x204
258 #define EMAC_RXMCASTFRAMES 0x208
259 #define EMAC_RXPAUSEFRAMES 0x20C
260 #define EMAC_RXCRCERRORS 0x210
261 #define EMAC_RXALIGNCODEERRORS 0x214
262 #define EMAC_RXOVERSIZED 0x218
263 #define EMAC_RXJABBER 0x21C
264 #define EMAC_RXUNDERSIZED 0x220
265 #define EMAC_RXFRAGMENTS 0x224
266 #define EMAC_RXFILTERED 0x228
267 #define EMAC_RXQOSFILTERED 0x22C
268 #define EMAC_RXOCTETS 0x230
269 #define EMAC_TXGOODFRAMES 0x234
270 #define EMAC_TXBCASTFRAMES 0x238
271 #define EMAC_TXMCASTFRAMES 0x23C
272 #define EMAC_TXPAUSEFRAMES 0x240
273 #define EMAC_TXDEFERRED 0x244
274 #define EMAC_TXCOLLISION 0x248
275 #define EMAC_TXSINGLECOLL 0x24C
276 #define EMAC_TXMULTICOLL 0x250
277 #define EMAC_TXEXCESSIVECOLL 0x254
278 #define EMAC_TXLATECOLL 0x258
279 #define EMAC_TXUNDERRUN 0x25C
280 #define EMAC_TXCARRIERSENSE 0x260
281 #define EMAC_TXOCTETS 0x264
282 #define EMAC_NETOCTETS 0x280
283 #define EMAC_RXSOFOVERRUNS 0x284
284 #define EMAC_RXMOFOVERRUNS 0x288
285 #define EMAC_RXDMAOVERRUNS 0x28C
286
287 /* EMAC DM644x control registers */
288 #define EMAC_CTRL_EWCTL (0x4)
289 #define EMAC_CTRL_EWINTTCNT (0x8)
290
291 /* EMAC DM644x control module masks */
292 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
293 #define EMAC_DM644X_INTMIN_INTVL 0x1
294 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
295
296 /* EMAC DM646X control module registers */
297 #define EMAC_DM646X_CMINTCTRL 0x0C
298 #define EMAC_DM646X_CMRXINTEN 0x14
299 #define EMAC_DM646X_CMTXINTEN 0x18
300 #define EMAC_DM646X_CMRXINTMAX 0x70
301 #define EMAC_DM646X_CMTXINTMAX 0x74
302
303 /* EMAC DM646X control module masks */
304 #define EMAC_DM646X_INTPACEEN (0x3 << 16)
305 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
306 #define EMAC_DM646X_CMINTMAX_CNT 63
307 #define EMAC_DM646X_CMINTMIN_CNT 2
308 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
309 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
310
311
312 /* EMAC EOI codes for C0 */
313 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
314 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
315
316 /* EMAC Stats Clear Mask */
317 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
318
319 /* emac_priv: EMAC private data structure
320 *
321 * EMAC adapter private data structure
322 */
323 struct emac_priv {
324 u32 msg_enable;
325 struct net_device *ndev;
326 struct platform_device *pdev;
327 struct napi_struct napi;
328 char mac_addr[6];
329 void __iomem *remap_addr;
330 u32 emac_base_phys;
331 void __iomem *emac_base;
332 void __iomem *ctrl_base;
333 struct cpdma_ctlr *dma;
334 struct cpdma_chan *txchan;
335 struct cpdma_chan *rxchan;
336 u32 link; /* 1=link on, 0=link off */
337 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
338 u32 duplex; /* Link duplex: 0=Half, 1=Full */
339 u32 rx_buf_size;
340 u32 isr_count;
341 u32 coal_intvl;
342 u32 bus_freq_mhz;
343 u8 rmii_en;
344 u8 version;
345 u32 mac_hash1;
346 u32 mac_hash2;
347 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
348 u32 rx_addr_type;
349 const char *phy_id;
350 struct device_node *phy_node;
351 struct phy_device *phydev;
352 spinlock_t lock;
353 /*platform specific members*/
354 void (*int_enable) (void);
355 void (*int_disable) (void);
356 };
357
358 /* EMAC TX Host Error description strings */
359 static char *emac_txhost_errcodes[16] = {
360 "No error", "SOP error", "Ownership bit not set in SOP buffer",
361 "Zero Next Buffer Descriptor Pointer Without EOP",
362 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
363 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
364 "Reserved", "Reserved", "Reserved", "Reserved"
365 };
366
367 /* EMAC RX Host Error description strings */
368 static char *emac_rxhost_errcodes[16] = {
369 "No error", "Reserved", "Ownership bit not set in input buffer",
370 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
371 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
372 "Reserved", "Reserved", "Reserved", "Reserved"
373 };
374
375 /* Helper macros */
376 #define emac_read(reg) ioread32(priv->emac_base + (reg))
377 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
378
379 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
380 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
381
382 /**
383 * emac_dump_regs - Dump important EMAC registers to debug terminal
384 * @priv: The DaVinci EMAC private adapter structure
385 *
386 * Executes ethtool set cmd & sets phy mode
387 *
388 */
emac_dump_regs(struct emac_priv * priv)389 static void emac_dump_regs(struct emac_priv *priv)
390 {
391 struct device *emac_dev = &priv->ndev->dev;
392
393 /* Print important registers in EMAC */
394 dev_info(emac_dev, "EMAC Basic registers\n");
395 if (priv->version == EMAC_VERSION_1) {
396 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
397 emac_ctrl_read(EMAC_CTRL_EWCTL),
398 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
399 }
400 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
401 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
402 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
403 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
404 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
405 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
406 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
407 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
408 dev_info(emac_dev, "EMAC Statistics\n");
409 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
410 emac_read(EMAC_RXGOODFRAMES));
411 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
412 emac_read(EMAC_RXBCASTFRAMES));
413 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
414 emac_read(EMAC_RXMCASTFRAMES));
415 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
416 emac_read(EMAC_RXPAUSEFRAMES));
417 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
418 emac_read(EMAC_RXCRCERRORS));
419 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
420 emac_read(EMAC_RXALIGNCODEERRORS));
421 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
422 emac_read(EMAC_RXOVERSIZED));
423 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
424 emac_read(EMAC_RXJABBER));
425 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
426 emac_read(EMAC_RXUNDERSIZED));
427 dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
428 emac_read(EMAC_RXFRAGMENTS));
429 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
430 emac_read(EMAC_RXFILTERED));
431 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
432 emac_read(EMAC_RXQOSFILTERED));
433 dev_info(emac_dev, "EMAC: rx_octets:%d\n",
434 emac_read(EMAC_RXOCTETS));
435 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
436 emac_read(EMAC_TXGOODFRAMES));
437 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
438 emac_read(EMAC_TXBCASTFRAMES));
439 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
440 emac_read(EMAC_TXMCASTFRAMES));
441 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
442 emac_read(EMAC_TXPAUSEFRAMES));
443 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
444 emac_read(EMAC_TXDEFERRED));
445 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
446 emac_read(EMAC_TXCOLLISION));
447 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
448 emac_read(EMAC_TXSINGLECOLL));
449 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
450 emac_read(EMAC_TXMULTICOLL));
451 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
452 emac_read(EMAC_TXEXCESSIVECOLL));
453 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
454 emac_read(EMAC_TXLATECOLL));
455 dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
456 emac_read(EMAC_TXUNDERRUN));
457 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
458 emac_read(EMAC_TXCARRIERSENSE));
459 dev_info(emac_dev, "EMAC: tx_octets:%d\n",
460 emac_read(EMAC_TXOCTETS));
461 dev_info(emac_dev, "EMAC: net_octets:%d\n",
462 emac_read(EMAC_NETOCTETS));
463 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
464 emac_read(EMAC_RXSOFOVERRUNS));
465 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
466 emac_read(EMAC_RXMOFOVERRUNS));
467 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
468 emac_read(EMAC_RXDMAOVERRUNS));
469
470 cpdma_ctlr_dump(priv->dma);
471 }
472
473 /**
474 * emac_get_drvinfo - Get EMAC driver information
475 * @ndev: The DaVinci EMAC network adapter
476 * @info: ethtool info structure containing name and version
477 *
478 * Returns EMAC driver information (name and version)
479 *
480 */
emac_get_drvinfo(struct net_device * ndev,struct ethtool_drvinfo * info)481 static void emac_get_drvinfo(struct net_device *ndev,
482 struct ethtool_drvinfo *info)
483 {
484 strlcpy(info->driver, emac_version_string, sizeof(info->driver));
485 strlcpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version));
486 }
487
488 /**
489 * emac_get_settings - Get EMAC settings
490 * @ndev: The DaVinci EMAC network adapter
491 * @ecmd: ethtool command
492 *
493 * Executes ethool get command
494 *
495 */
emac_get_settings(struct net_device * ndev,struct ethtool_cmd * ecmd)496 static int emac_get_settings(struct net_device *ndev,
497 struct ethtool_cmd *ecmd)
498 {
499 struct emac_priv *priv = netdev_priv(ndev);
500 if (priv->phydev)
501 return phy_ethtool_gset(priv->phydev, ecmd);
502 else
503 return -EOPNOTSUPP;
504
505 }
506
507 /**
508 * emac_set_settings - Set EMAC settings
509 * @ndev: The DaVinci EMAC network adapter
510 * @ecmd: ethtool command
511 *
512 * Executes ethool set command
513 *
514 */
emac_set_settings(struct net_device * ndev,struct ethtool_cmd * ecmd)515 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
516 {
517 struct emac_priv *priv = netdev_priv(ndev);
518 if (priv->phydev)
519 return phy_ethtool_sset(priv->phydev, ecmd);
520 else
521 return -EOPNOTSUPP;
522
523 }
524
525 /**
526 * emac_get_coalesce - Get interrupt coalesce settings for this device
527 * @ndev : The DaVinci EMAC network adapter
528 * @coal : ethtool coalesce settings structure
529 *
530 * Fetch the current interrupt coalesce settings
531 *
532 */
emac_get_coalesce(struct net_device * ndev,struct ethtool_coalesce * coal)533 static int emac_get_coalesce(struct net_device *ndev,
534 struct ethtool_coalesce *coal)
535 {
536 struct emac_priv *priv = netdev_priv(ndev);
537
538 coal->rx_coalesce_usecs = priv->coal_intvl;
539 return 0;
540
541 }
542
543 /**
544 * emac_set_coalesce - Set interrupt coalesce settings for this device
545 * @ndev : The DaVinci EMAC network adapter
546 * @coal : ethtool coalesce settings structure
547 *
548 * Set interrupt coalesce parameters
549 *
550 */
emac_set_coalesce(struct net_device * ndev,struct ethtool_coalesce * coal)551 static int emac_set_coalesce(struct net_device *ndev,
552 struct ethtool_coalesce *coal)
553 {
554 struct emac_priv *priv = netdev_priv(ndev);
555 u32 int_ctrl, num_interrupts = 0;
556 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
557
558 if (!coal->rx_coalesce_usecs) {
559 priv->coal_intvl = 0;
560
561 switch (priv->version) {
562 case EMAC_VERSION_2:
563 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, 0);
564 break;
565 default:
566 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, 0);
567 break;
568 }
569
570 return 0;
571 }
572
573 coal_intvl = coal->rx_coalesce_usecs;
574
575 switch (priv->version) {
576 case EMAC_VERSION_2:
577 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
578 prescale = priv->bus_freq_mhz * 4;
579
580 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
581 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
582
583 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
584 /*
585 * Interrupt pacer works with 4us Pulse, we can
586 * throttle further by dilating the 4us pulse.
587 */
588 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
589
590 if (addnl_dvdr > 1) {
591 prescale *= addnl_dvdr;
592 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
593 * addnl_dvdr))
594 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
595 * addnl_dvdr);
596 } else {
597 addnl_dvdr = 1;
598 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
599 }
600 }
601
602 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
603
604 int_ctrl |= EMAC_DM646X_INTPACEEN;
605 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
606 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
607 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
608
609 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
610 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
611
612 break;
613 default:
614 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
615 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
616 prescale = coal_intvl * priv->bus_freq_mhz;
617 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
618 prescale = EMAC_DM644X_EWINTCNT_MASK;
619 coal_intvl = prescale / priv->bus_freq_mhz;
620 }
621 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
622
623 break;
624 }
625
626 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
627 priv->coal_intvl = coal_intvl;
628
629 return 0;
630
631 }
632
633
634 /* ethtool_ops: DaVinci EMAC Ethtool structure
635 *
636 * Ethtool support for EMAC adapter
637 */
638 static const struct ethtool_ops ethtool_ops = {
639 .get_drvinfo = emac_get_drvinfo,
640 .get_settings = emac_get_settings,
641 .set_settings = emac_set_settings,
642 .get_link = ethtool_op_get_link,
643 .get_coalesce = emac_get_coalesce,
644 .set_coalesce = emac_set_coalesce,
645 .get_ts_info = ethtool_op_get_ts_info,
646 };
647
648 /**
649 * emac_update_phystatus - Update Phy status
650 * @priv: The DaVinci EMAC private adapter structure
651 *
652 * Updates phy status and takes action for network queue if required
653 * based upon link status
654 *
655 */
emac_update_phystatus(struct emac_priv * priv)656 static void emac_update_phystatus(struct emac_priv *priv)
657 {
658 u32 mac_control;
659 u32 new_duplex;
660 u32 cur_duplex;
661 struct net_device *ndev = priv->ndev;
662
663 mac_control = emac_read(EMAC_MACCONTROL);
664 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
665 DUPLEX_FULL : DUPLEX_HALF;
666 if (priv->phydev)
667 new_duplex = priv->phydev->duplex;
668 else
669 new_duplex = DUPLEX_FULL;
670
671 /* We get called only if link has changed (speed/duplex/status) */
672 if ((priv->link) && (new_duplex != cur_duplex)) {
673 priv->duplex = new_duplex;
674 if (DUPLEX_FULL == priv->duplex)
675 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
676 else
677 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
678 }
679
680 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
681 mac_control = emac_read(EMAC_MACCONTROL);
682 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
683 EMAC_DM646X_MACCONTORL_GIGFORCE);
684 } else {
685 /* Clear the GIG bit and GIGFORCE bit */
686 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
687 EMAC_DM646X_MACCONTORL_GIG);
688
689 if (priv->rmii_en && (priv->speed == SPEED_100))
690 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
691 else
692 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
693 }
694
695 /* Update mac_control if changed */
696 emac_write(EMAC_MACCONTROL, mac_control);
697
698 if (priv->link) {
699 /* link ON */
700 if (!netif_carrier_ok(ndev))
701 netif_carrier_on(ndev);
702 /* reactivate the transmit queue if it is stopped */
703 if (netif_running(ndev) && netif_queue_stopped(ndev))
704 netif_wake_queue(ndev);
705 } else {
706 /* link OFF */
707 if (netif_carrier_ok(ndev))
708 netif_carrier_off(ndev);
709 if (!netif_queue_stopped(ndev))
710 netif_stop_queue(ndev);
711 }
712 }
713
714 /**
715 * hash_get - Calculate hash value from mac address
716 * @addr: mac address to delete from hash table
717 *
718 * Calculates hash value from mac address
719 *
720 */
hash_get(u8 * addr)721 static u32 hash_get(u8 *addr)
722 {
723 u32 hash;
724 u8 tmpval;
725 int cnt;
726 hash = 0;
727
728 for (cnt = 0; cnt < 2; cnt++) {
729 tmpval = *addr++;
730 hash ^= (tmpval >> 2) ^ (tmpval << 4);
731 tmpval = *addr++;
732 hash ^= (tmpval >> 4) ^ (tmpval << 2);
733 tmpval = *addr++;
734 hash ^= (tmpval >> 6) ^ (tmpval);
735 }
736
737 return hash & 0x3F;
738 }
739
740 /**
741 * hash_add - Hash function to add mac addr from hash table
742 * @priv: The DaVinci EMAC private adapter structure
743 * @mac_addr: mac address to delete from hash table
744 *
745 * Adds mac address to the internal hash table
746 *
747 */
hash_add(struct emac_priv * priv,u8 * mac_addr)748 static int hash_add(struct emac_priv *priv, u8 *mac_addr)
749 {
750 struct device *emac_dev = &priv->ndev->dev;
751 u32 rc = 0;
752 u32 hash_bit;
753 u32 hash_value = hash_get(mac_addr);
754
755 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
756 if (netif_msg_drv(priv)) {
757 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
758 "Hash %08x, should not be greater than %08x",
759 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
760 }
761 return -1;
762 }
763
764 /* set the hash bit only if not previously set */
765 if (priv->multicast_hash_cnt[hash_value] == 0) {
766 rc = 1; /* hash value changed */
767 if (hash_value < 32) {
768 hash_bit = BIT(hash_value);
769 priv->mac_hash1 |= hash_bit;
770 } else {
771 hash_bit = BIT((hash_value - 32));
772 priv->mac_hash2 |= hash_bit;
773 }
774 }
775
776 /* incr counter for num of mcast addr's mapped to "this" hash bit */
777 ++priv->multicast_hash_cnt[hash_value];
778
779 return rc;
780 }
781
782 /**
783 * hash_del - Hash function to delete mac addr from hash table
784 * @priv: The DaVinci EMAC private adapter structure
785 * @mac_addr: mac address to delete from hash table
786 *
787 * Removes mac address from the internal hash table
788 *
789 */
hash_del(struct emac_priv * priv,u8 * mac_addr)790 static int hash_del(struct emac_priv *priv, u8 *mac_addr)
791 {
792 u32 hash_value;
793 u32 hash_bit;
794
795 hash_value = hash_get(mac_addr);
796 if (priv->multicast_hash_cnt[hash_value] > 0) {
797 /* dec cntr for num of mcast addr's mapped to this hash bit */
798 --priv->multicast_hash_cnt[hash_value];
799 }
800
801 /* if counter still > 0, at least one multicast address refers
802 * to this hash bit. so return 0 */
803 if (priv->multicast_hash_cnt[hash_value] > 0)
804 return 0;
805
806 if (hash_value < 32) {
807 hash_bit = BIT(hash_value);
808 priv->mac_hash1 &= ~hash_bit;
809 } else {
810 hash_bit = BIT((hash_value - 32));
811 priv->mac_hash2 &= ~hash_bit;
812 }
813
814 /* return 1 to indicate change in mac_hash registers reqd */
815 return 1;
816 }
817
818 /* EMAC multicast operation */
819 #define EMAC_MULTICAST_ADD 0
820 #define EMAC_MULTICAST_DEL 1
821 #define EMAC_ALL_MULTI_SET 2
822 #define EMAC_ALL_MULTI_CLR 3
823
824 /**
825 * emac_add_mcast - Set multicast address in the EMAC adapter (Internal)
826 * @priv: The DaVinci EMAC private adapter structure
827 * @action: multicast operation to perform
828 * mac_addr: mac address to set
829 *
830 * Set multicast addresses in EMAC adapter - internal function
831 *
832 */
emac_add_mcast(struct emac_priv * priv,u32 action,u8 * mac_addr)833 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
834 {
835 struct device *emac_dev = &priv->ndev->dev;
836 int update = -1;
837
838 switch (action) {
839 case EMAC_MULTICAST_ADD:
840 update = hash_add(priv, mac_addr);
841 break;
842 case EMAC_MULTICAST_DEL:
843 update = hash_del(priv, mac_addr);
844 break;
845 case EMAC_ALL_MULTI_SET:
846 update = 1;
847 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
848 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
849 break;
850 case EMAC_ALL_MULTI_CLR:
851 update = 1;
852 priv->mac_hash1 = 0;
853 priv->mac_hash2 = 0;
854 memset(&(priv->multicast_hash_cnt[0]), 0,
855 sizeof(priv->multicast_hash_cnt[0]) *
856 EMAC_NUM_MULTICAST_BITS);
857 break;
858 default:
859 if (netif_msg_drv(priv))
860 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
861 ": bad operation %d", action);
862 break;
863 }
864
865 /* write to the hardware only if the register status chances */
866 if (update > 0) {
867 emac_write(EMAC_MACHASH1, priv->mac_hash1);
868 emac_write(EMAC_MACHASH2, priv->mac_hash2);
869 }
870 }
871
872 /**
873 * emac_dev_mcast_set - Set multicast address in the EMAC adapter
874 * @ndev: The DaVinci EMAC network adapter
875 *
876 * Set multicast addresses in EMAC adapter
877 *
878 */
emac_dev_mcast_set(struct net_device * ndev)879 static void emac_dev_mcast_set(struct net_device *ndev)
880 {
881 u32 mbp_enable;
882 struct emac_priv *priv = netdev_priv(ndev);
883
884 mbp_enable = emac_read(EMAC_RXMBPENABLE);
885 if (ndev->flags & IFF_PROMISC) {
886 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
887 mbp_enable |= (EMAC_MBP_RXPROMISC);
888 } else {
889 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
890 if ((ndev->flags & IFF_ALLMULTI) ||
891 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
892 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
893 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
894 } else if (!netdev_mc_empty(ndev)) {
895 struct netdev_hw_addr *ha;
896
897 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
898 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
899 /* program multicast address list into EMAC hardware */
900 netdev_for_each_mc_addr(ha, ndev) {
901 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
902 (u8 *) ha->addr);
903 }
904 } else {
905 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
906 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
907 }
908 }
909 /* Set mbp config register */
910 emac_write(EMAC_RXMBPENABLE, mbp_enable);
911 }
912
913 /*************************************************************************
914 * EMAC Hardware manipulation
915 *************************************************************************/
916
917 /**
918 * emac_int_disable - Disable EMAC module interrupt (from adapter)
919 * @priv: The DaVinci EMAC private adapter structure
920 *
921 * Disable EMAC interrupt on the adapter
922 *
923 */
emac_int_disable(struct emac_priv * priv)924 static void emac_int_disable(struct emac_priv *priv)
925 {
926 if (priv->version == EMAC_VERSION_2) {
927 unsigned long flags;
928
929 local_irq_save(flags);
930
931 /* Program C0_Int_En to zero to turn off
932 * interrupts to the CPU */
933 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
934 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
935 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
936 if (priv->int_disable)
937 priv->int_disable();
938
939 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
940
941 /* ack rxen only then a new pulse will be generated */
942 emac_write(EMAC_DM646X_MACEOIVECTOR,
943 EMAC_DM646X_MAC_EOI_C0_RXEN);
944
945 /* ack txen- only then a new pulse will be generated */
946 emac_write(EMAC_DM646X_MACEOIVECTOR,
947 EMAC_DM646X_MAC_EOI_C0_TXEN);
948
949 local_irq_restore(flags);
950
951 } else {
952 /* Set DM644x control registers for interrupt control */
953 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
954 }
955 }
956
957 /**
958 * emac_int_enable - Enable EMAC module interrupt (from adapter)
959 * @priv: The DaVinci EMAC private adapter structure
960 *
961 * Enable EMAC interrupt on the adapter
962 *
963 */
emac_int_enable(struct emac_priv * priv)964 static void emac_int_enable(struct emac_priv *priv)
965 {
966 if (priv->version == EMAC_VERSION_2) {
967 if (priv->int_enable)
968 priv->int_enable();
969
970 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
971 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
972
973 /* In addition to turning on interrupt Enable, we need
974 * ack by writing appropriate values to the EOI
975 * register */
976
977 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
978 } else {
979 /* Set DM644x control registers for interrupt control */
980 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
981 }
982 }
983
984 /**
985 * emac_irq - EMAC interrupt handler
986 * @irq: interrupt number
987 * @dev_id: EMAC network adapter data structure ptr
988 *
989 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
990 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
991 *
992 * Returns interrupt handled condition
993 */
emac_irq(int irq,void * dev_id)994 static irqreturn_t emac_irq(int irq, void *dev_id)
995 {
996 struct net_device *ndev = (struct net_device *)dev_id;
997 struct emac_priv *priv = netdev_priv(ndev);
998
999 ++priv->isr_count;
1000 if (likely(netif_running(priv->ndev))) {
1001 emac_int_disable(priv);
1002 napi_schedule(&priv->napi);
1003 } else {
1004 /* we are closing down, so dont process anything */
1005 }
1006 return IRQ_HANDLED;
1007 }
1008
emac_rx_alloc(struct emac_priv * priv)1009 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
1010 {
1011 struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size);
1012 if (WARN_ON(!skb))
1013 return NULL;
1014 skb_reserve(skb, NET_IP_ALIGN);
1015 return skb;
1016 }
1017
emac_rx_handler(void * token,int len,int status)1018 static void emac_rx_handler(void *token, int len, int status)
1019 {
1020 struct sk_buff *skb = token;
1021 struct net_device *ndev = skb->dev;
1022 struct emac_priv *priv = netdev_priv(ndev);
1023 struct device *emac_dev = &ndev->dev;
1024 int ret;
1025
1026 /* free and bail if we are shutting down */
1027 if (unlikely(!netif_running(ndev))) {
1028 dev_kfree_skb_any(skb);
1029 return;
1030 }
1031
1032 /* recycle on receive error */
1033 if (status < 0) {
1034 ndev->stats.rx_errors++;
1035 goto recycle;
1036 }
1037
1038 /* feed received packet up the stack */
1039 skb_put(skb, len);
1040 skb->protocol = eth_type_trans(skb, ndev);
1041 netif_receive_skb(skb);
1042 ndev->stats.rx_bytes += len;
1043 ndev->stats.rx_packets++;
1044
1045 /* alloc a new packet for receive */
1046 skb = emac_rx_alloc(priv);
1047 if (!skb) {
1048 if (netif_msg_rx_err(priv) && net_ratelimit())
1049 dev_err(emac_dev, "failed rx buffer alloc\n");
1050 return;
1051 }
1052
1053 recycle:
1054 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1055 skb_tailroom(skb), 0);
1056
1057 WARN_ON(ret == -ENOMEM);
1058 if (unlikely(ret < 0))
1059 dev_kfree_skb_any(skb);
1060 }
1061
emac_tx_handler(void * token,int len,int status)1062 static void emac_tx_handler(void *token, int len, int status)
1063 {
1064 struct sk_buff *skb = token;
1065 struct net_device *ndev = skb->dev;
1066
1067 /* Check whether the queue is stopped due to stalled tx dma, if the
1068 * queue is stopped then start the queue as we have free desc for tx
1069 */
1070 if (unlikely(netif_queue_stopped(ndev)))
1071 netif_wake_queue(ndev);
1072 ndev->stats.tx_packets++;
1073 ndev->stats.tx_bytes += len;
1074 dev_kfree_skb_any(skb);
1075 }
1076
1077 /**
1078 * emac_dev_xmit - EMAC Transmit function
1079 * @skb: SKB pointer
1080 * @ndev: The DaVinci EMAC network adapter
1081 *
1082 * Called by the system to transmit a packet - we queue the packet in
1083 * EMAC hardware transmit queue
1084 *
1085 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1086 */
emac_dev_xmit(struct sk_buff * skb,struct net_device * ndev)1087 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1088 {
1089 struct device *emac_dev = &ndev->dev;
1090 int ret_code;
1091 struct emac_priv *priv = netdev_priv(ndev);
1092
1093 /* If no link, return */
1094 if (unlikely(!priv->link)) {
1095 if (netif_msg_tx_err(priv) && net_ratelimit())
1096 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1097 goto fail_tx;
1098 }
1099
1100 ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
1101 if (unlikely(ret_code < 0)) {
1102 if (netif_msg_tx_err(priv) && net_ratelimit())
1103 dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
1104 goto fail_tx;
1105 }
1106
1107 skb_tx_timestamp(skb);
1108
1109 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
1110 0);
1111 if (unlikely(ret_code != 0)) {
1112 if (netif_msg_tx_err(priv) && net_ratelimit())
1113 dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
1114 goto fail_tx;
1115 }
1116
1117 /* If there is no more tx desc left free then we need to
1118 * tell the kernel to stop sending us tx frames.
1119 */
1120 if (unlikely(!cpdma_check_free_tx_desc(priv->txchan)))
1121 netif_stop_queue(ndev);
1122
1123 return NETDEV_TX_OK;
1124
1125 fail_tx:
1126 ndev->stats.tx_dropped++;
1127 netif_stop_queue(ndev);
1128 return NETDEV_TX_BUSY;
1129 }
1130
1131 /**
1132 * emac_dev_tx_timeout - EMAC Transmit timeout function
1133 * @ndev: The DaVinci EMAC network adapter
1134 *
1135 * Called when system detects that a skb timeout period has expired
1136 * potentially due to a fault in the adapter in not being able to send
1137 * it out on the wire. We teardown the TX channel assuming a hardware
1138 * error and re-initialize the TX channel for hardware operation
1139 *
1140 */
emac_dev_tx_timeout(struct net_device * ndev)1141 static void emac_dev_tx_timeout(struct net_device *ndev)
1142 {
1143 struct emac_priv *priv = netdev_priv(ndev);
1144 struct device *emac_dev = &ndev->dev;
1145
1146 if (netif_msg_tx_err(priv))
1147 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1148
1149 emac_dump_regs(priv);
1150
1151 ndev->stats.tx_errors++;
1152 emac_int_disable(priv);
1153 cpdma_chan_stop(priv->txchan);
1154 cpdma_chan_start(priv->txchan);
1155 emac_int_enable(priv);
1156 }
1157
1158 /**
1159 * emac_set_type0addr - Set EMAC Type0 mac address
1160 * @priv: The DaVinci EMAC private adapter structure
1161 * @ch: RX channel number
1162 * @mac_addr: MAC address to set in device
1163 *
1164 * Called internally to set Type0 mac address of the adapter (Device)
1165 *
1166 * Returns success (0) or appropriate error code (none as of now)
1167 */
emac_set_type0addr(struct emac_priv * priv,u32 ch,char * mac_addr)1168 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1169 {
1170 u32 val;
1171 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1172 emac_write(EMAC_MACSRCADDRLO, val);
1173
1174 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1175 (mac_addr[1] << 8) | (mac_addr[0]));
1176 emac_write(EMAC_MACSRCADDRHI, val);
1177 val = emac_read(EMAC_RXUNICASTSET);
1178 val |= BIT(ch);
1179 emac_write(EMAC_RXUNICASTSET, val);
1180 val = emac_read(EMAC_RXUNICASTCLEAR);
1181 val &= ~BIT(ch);
1182 emac_write(EMAC_RXUNICASTCLEAR, val);
1183 }
1184
1185 /**
1186 * emac_set_type1addr - Set EMAC Type1 mac address
1187 * @priv: The DaVinci EMAC private adapter structure
1188 * @ch: RX channel number
1189 * @mac_addr: MAC address to set in device
1190 *
1191 * Called internally to set Type1 mac address of the adapter (Device)
1192 *
1193 * Returns success (0) or appropriate error code (none as of now)
1194 */
emac_set_type1addr(struct emac_priv * priv,u32 ch,char * mac_addr)1195 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1196 {
1197 u32 val;
1198 emac_write(EMAC_MACINDEX, ch);
1199 val = ((mac_addr[5] << 8) | mac_addr[4]);
1200 emac_write(EMAC_MACADDRLO, val);
1201 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1202 (mac_addr[1] << 8) | (mac_addr[0]));
1203 emac_write(EMAC_MACADDRHI, val);
1204 emac_set_type0addr(priv, ch, mac_addr);
1205 }
1206
1207 /**
1208 * emac_set_type2addr - Set EMAC Type2 mac address
1209 * @priv: The DaVinci EMAC private adapter structure
1210 * @ch: RX channel number
1211 * @mac_addr: MAC address to set in device
1212 * @index: index into RX address entries
1213 * @match: match parameter for RX address matching logic
1214 *
1215 * Called internally to set Type2 mac address of the adapter (Device)
1216 *
1217 * Returns success (0) or appropriate error code (none as of now)
1218 */
emac_set_type2addr(struct emac_priv * priv,u32 ch,char * mac_addr,int index,int match)1219 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1220 char *mac_addr, int index, int match)
1221 {
1222 u32 val;
1223 emac_write(EMAC_MACINDEX, index);
1224 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1225 (mac_addr[1] << 8) | (mac_addr[0]));
1226 emac_write(EMAC_MACADDRHI, val);
1227 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1228 (match << 19) | BIT(20));
1229 emac_write(EMAC_MACADDRLO, val);
1230 emac_set_type0addr(priv, ch, mac_addr);
1231 }
1232
1233 /**
1234 * emac_setmac - Set mac address in the adapter (internal function)
1235 * @priv: The DaVinci EMAC private adapter structure
1236 * @ch: RX channel number
1237 * @mac_addr: MAC address to set in device
1238 *
1239 * Called internally to set the mac address of the adapter (Device)
1240 *
1241 * Returns success (0) or appropriate error code (none as of now)
1242 */
emac_setmac(struct emac_priv * priv,u32 ch,char * mac_addr)1243 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1244 {
1245 struct device *emac_dev = &priv->ndev->dev;
1246
1247 if (priv->rx_addr_type == 0) {
1248 emac_set_type0addr(priv, ch, mac_addr);
1249 } else if (priv->rx_addr_type == 1) {
1250 u32 cnt;
1251 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1252 emac_set_type1addr(priv, ch, mac_addr);
1253 } else if (priv->rx_addr_type == 2) {
1254 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1255 emac_set_type0addr(priv, ch, mac_addr);
1256 } else {
1257 if (netif_msg_drv(priv))
1258 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1259 }
1260 }
1261
1262 /**
1263 * emac_dev_setmac_addr - Set mac address in the adapter
1264 * @ndev: The DaVinci EMAC network adapter
1265 * @addr: MAC address to set in device
1266 *
1267 * Called by the system to set the mac address of the adapter (Device)
1268 *
1269 * Returns success (0) or appropriate error code (none as of now)
1270 */
emac_dev_setmac_addr(struct net_device * ndev,void * addr)1271 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1272 {
1273 struct emac_priv *priv = netdev_priv(ndev);
1274 struct device *emac_dev = &priv->ndev->dev;
1275 struct sockaddr *sa = addr;
1276
1277 if (!is_valid_ether_addr(sa->sa_data))
1278 return -EADDRNOTAVAIL;
1279
1280 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1281 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1282 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1283
1284 /* MAC address is configured only after the interface is enabled. */
1285 if (netif_running(ndev)) {
1286 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1287 }
1288
1289 if (netif_msg_drv(priv))
1290 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1291 priv->mac_addr);
1292
1293 return 0;
1294 }
1295
1296 /**
1297 * emac_hw_enable - Enable EMAC hardware for packet transmission/reception
1298 * @priv: The DaVinci EMAC private adapter structure
1299 *
1300 * Enables EMAC hardware for packet processing - enables PHY, enables RX
1301 * for packet reception and enables device interrupts and then NAPI
1302 *
1303 * Returns success (0) or appropriate error code (none right now)
1304 */
emac_hw_enable(struct emac_priv * priv)1305 static int emac_hw_enable(struct emac_priv *priv)
1306 {
1307 u32 val, mbp_enable, mac_control;
1308
1309 /* Soft reset */
1310 emac_write(EMAC_SOFTRESET, 1);
1311 while (emac_read(EMAC_SOFTRESET))
1312 cpu_relax();
1313
1314 /* Disable interrupt & Set pacing for more interrupts initially */
1315 emac_int_disable(priv);
1316
1317 /* Full duplex enable bit set when auto negotiation happens */
1318 mac_control =
1319 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
1320 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
1321 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
1322 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
1323 emac_write(EMAC_MACCONTROL, mac_control);
1324
1325 mbp_enable =
1326 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
1327 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
1328 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
1329 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
1330 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
1331 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
1332 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
1333 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
1334 EMAC_RXMBP_PROMCH_SHIFT) |
1335 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
1336 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
1337 EMAC_RXMBP_BROADCH_SHIFT) |
1338 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
1339 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
1340 EMAC_RXMBP_MULTICH_SHIFT));
1341 emac_write(EMAC_RXMBPENABLE, mbp_enable);
1342 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
1343 EMAC_RX_MAX_LEN_MASK));
1344 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
1345 EMAC_RX_BUFFER_OFFSET_MASK));
1346 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
1347 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
1348 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
1349
1350 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
1351
1352 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1353
1354 /* Enable MII */
1355 val = emac_read(EMAC_MACCONTROL);
1356 val |= (EMAC_MACCONTROL_GMIIEN);
1357 emac_write(EMAC_MACCONTROL, val);
1358
1359 /* Enable NAPI and interrupts */
1360 napi_enable(&priv->napi);
1361 emac_int_enable(priv);
1362 return 0;
1363
1364 }
1365
1366 /**
1367 * emac_poll - EMAC NAPI Poll function
1368 * @ndev: The DaVinci EMAC network adapter
1369 * @budget: Number of receive packets to process (as told by NAPI layer)
1370 *
1371 * NAPI Poll function implemented to process packets as per budget. We check
1372 * the type of interrupt on the device and accordingly call the TX or RX
1373 * packet processing functions. We follow the budget for RX processing and
1374 * also put a cap on number of TX pkts processed through config param. The
1375 * NAPI schedule function is called if more packets pending.
1376 *
1377 * Returns number of packets received (in most cases; else TX pkts - rarely)
1378 */
emac_poll(struct napi_struct * napi,int budget)1379 static int emac_poll(struct napi_struct *napi, int budget)
1380 {
1381 unsigned int mask;
1382 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
1383 struct net_device *ndev = priv->ndev;
1384 struct device *emac_dev = &ndev->dev;
1385 u32 status = 0;
1386 u32 num_tx_pkts = 0, num_rx_pkts = 0;
1387
1388 /* Check interrupt vectors and call packet processing */
1389 status = emac_read(EMAC_MACINVECTOR);
1390
1391 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
1392
1393 if (priv->version == EMAC_VERSION_2)
1394 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
1395
1396 if (status & mask) {
1397 num_tx_pkts = cpdma_chan_process(priv->txchan,
1398 EMAC_DEF_TX_MAX_SERVICE);
1399 } /* TX processing */
1400
1401 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
1402
1403 if (priv->version == EMAC_VERSION_2)
1404 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
1405
1406 if (status & mask) {
1407 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
1408 } /* RX processing */
1409
1410 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
1411 if (priv->version == EMAC_VERSION_2)
1412 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
1413
1414 if (unlikely(status & mask)) {
1415 u32 ch, cause;
1416 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
1417 netif_stop_queue(ndev);
1418 napi_disable(&priv->napi);
1419
1420 status = emac_read(EMAC_MACSTATUS);
1421 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
1422 EMAC_MACSTATUS_TXERRCODE_SHIFT);
1423 if (cause) {
1424 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
1425 EMAC_MACSTATUS_TXERRCH_SHIFT);
1426 if (net_ratelimit()) {
1427 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
1428 &emac_txhost_errcodes[cause][0], ch);
1429 }
1430 }
1431 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
1432 EMAC_MACSTATUS_RXERRCODE_SHIFT);
1433 if (cause) {
1434 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
1435 EMAC_MACSTATUS_RXERRCH_SHIFT);
1436 if (netif_msg_hw(priv) && net_ratelimit())
1437 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
1438 &emac_rxhost_errcodes[cause][0], ch);
1439 }
1440 } else if (num_rx_pkts < budget) {
1441 napi_complete(napi);
1442 emac_int_enable(priv);
1443 }
1444
1445 return num_rx_pkts;
1446 }
1447
1448 #ifdef CONFIG_NET_POLL_CONTROLLER
1449 /**
1450 * emac_poll_controller - EMAC Poll controller function
1451 * @ndev: The DaVinci EMAC network adapter
1452 *
1453 * Polled functionality used by netconsole and others in non interrupt mode
1454 *
1455 */
emac_poll_controller(struct net_device * ndev)1456 static void emac_poll_controller(struct net_device *ndev)
1457 {
1458 struct emac_priv *priv = netdev_priv(ndev);
1459
1460 emac_int_disable(priv);
1461 emac_irq(ndev->irq, ndev);
1462 emac_int_enable(priv);
1463 }
1464 #endif
1465
emac_adjust_link(struct net_device * ndev)1466 static void emac_adjust_link(struct net_device *ndev)
1467 {
1468 struct emac_priv *priv = netdev_priv(ndev);
1469 struct phy_device *phydev = priv->phydev;
1470 unsigned long flags;
1471 int new_state = 0;
1472
1473 spin_lock_irqsave(&priv->lock, flags);
1474
1475 if (phydev->link) {
1476 /* check the mode of operation - full/half duplex */
1477 if (phydev->duplex != priv->duplex) {
1478 new_state = 1;
1479 priv->duplex = phydev->duplex;
1480 }
1481 if (phydev->speed != priv->speed) {
1482 new_state = 1;
1483 priv->speed = phydev->speed;
1484 }
1485 if (!priv->link) {
1486 new_state = 1;
1487 priv->link = 1;
1488 }
1489
1490 } else if (priv->link) {
1491 new_state = 1;
1492 priv->link = 0;
1493 priv->speed = 0;
1494 priv->duplex = ~0;
1495 }
1496 if (new_state) {
1497 emac_update_phystatus(priv);
1498 phy_print_status(priv->phydev);
1499 }
1500
1501 spin_unlock_irqrestore(&priv->lock, flags);
1502 }
1503
1504 /*************************************************************************
1505 * Linux Driver Model
1506 *************************************************************************/
1507
1508 /**
1509 * emac_devioctl - EMAC adapter ioctl
1510 * @ndev: The DaVinci EMAC network adapter
1511 * @ifrq: request parameter
1512 * @cmd: command parameter
1513 *
1514 * EMAC driver ioctl function
1515 *
1516 * Returns success(0) or appropriate error code
1517 */
emac_devioctl(struct net_device * ndev,struct ifreq * ifrq,int cmd)1518 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
1519 {
1520 struct emac_priv *priv = netdev_priv(ndev);
1521
1522 if (!(netif_running(ndev)))
1523 return -EINVAL;
1524
1525 /* TODO: Add phy read and write and private statistics get feature */
1526
1527 if (priv->phydev)
1528 return phy_mii_ioctl(priv->phydev, ifrq, cmd);
1529 else
1530 return -EOPNOTSUPP;
1531 }
1532
match_first_device(struct device * dev,void * data)1533 static int match_first_device(struct device *dev, void *data)
1534 {
1535 if (dev->parent && dev->parent->of_node)
1536 return of_device_is_compatible(dev->parent->of_node,
1537 "ti,davinci_mdio");
1538
1539 return !strncmp(dev_name(dev), "davinci_mdio", 12);
1540 }
1541
1542 /**
1543 * emac_dev_open - EMAC device open
1544 * @ndev: The DaVinci EMAC network adapter
1545 *
1546 * Called when system wants to start the interface. We init TX/RX channels
1547 * and enable the hardware for packet reception/transmission and start the
1548 * network queue.
1549 *
1550 * Returns 0 for a successful open, or appropriate error code
1551 */
emac_dev_open(struct net_device * ndev)1552 static int emac_dev_open(struct net_device *ndev)
1553 {
1554 struct device *emac_dev = &ndev->dev;
1555 u32 cnt;
1556 struct resource *res;
1557 int q, m, ret;
1558 int res_num = 0, irq_num = 0;
1559 int i = 0;
1560 struct emac_priv *priv = netdev_priv(ndev);
1561
1562 ret = pm_runtime_get_sync(&priv->pdev->dev);
1563 if (ret < 0) {
1564 pm_runtime_put_noidle(&priv->pdev->dev);
1565 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
1566 __func__, ret);
1567 return ret;
1568 }
1569
1570 netif_carrier_off(ndev);
1571 for (cnt = 0; cnt < ETH_ALEN; cnt++)
1572 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
1573
1574 /* Configuration items */
1575 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
1576
1577 priv->mac_hash1 = 0;
1578 priv->mac_hash2 = 0;
1579 emac_write(EMAC_MACHASH1, 0);
1580 emac_write(EMAC_MACHASH2, 0);
1581
1582 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
1583 struct sk_buff *skb = emac_rx_alloc(priv);
1584
1585 if (!skb)
1586 break;
1587
1588 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1589 skb_tailroom(skb), 0);
1590 if (WARN_ON(ret < 0))
1591 break;
1592 }
1593
1594 /* Request IRQ */
1595 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ,
1596 res_num))) {
1597 for (irq_num = res->start; irq_num <= res->end; irq_num++) {
1598 if (request_irq(irq_num, emac_irq, 0, ndev->name,
1599 ndev)) {
1600 dev_err(emac_dev,
1601 "DaVinci EMAC: request_irq() failed\n");
1602 ret = -EBUSY;
1603
1604 goto rollback;
1605 }
1606 }
1607 res_num++;
1608 }
1609 /* prepare counters for rollback in case of an error */
1610 res_num--;
1611 irq_num--;
1612
1613 /* Start/Enable EMAC hardware */
1614 emac_hw_enable(priv);
1615
1616 /* Enable Interrupt pacing if configured */
1617 if (priv->coal_intvl != 0) {
1618 struct ethtool_coalesce coal;
1619
1620 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1621 emac_set_coalesce(ndev, &coal);
1622 }
1623
1624 cpdma_ctlr_start(priv->dma);
1625
1626 priv->phydev = NULL;
1627
1628 if (priv->phy_node) {
1629 priv->phydev = of_phy_connect(ndev, priv->phy_node,
1630 &emac_adjust_link, 0, 0);
1631 if (!priv->phydev) {
1632 dev_err(emac_dev, "could not connect to phy %s\n",
1633 priv->phy_node->full_name);
1634 ret = -ENODEV;
1635 goto err;
1636 }
1637 }
1638
1639 /* use the first phy on the bus if pdata did not give us a phy id */
1640 if (!priv->phydev && !priv->phy_id) {
1641 struct device *phy;
1642
1643 phy = bus_find_device(&mdio_bus_type, NULL, NULL,
1644 match_first_device);
1645 if (phy)
1646 priv->phy_id = dev_name(phy);
1647 }
1648
1649 if (!priv->phydev && priv->phy_id && *priv->phy_id) {
1650 priv->phydev = phy_connect(ndev, priv->phy_id,
1651 &emac_adjust_link,
1652 PHY_INTERFACE_MODE_MII);
1653
1654 if (IS_ERR(priv->phydev)) {
1655 dev_err(emac_dev, "could not connect to phy %s\n",
1656 priv->phy_id);
1657 ret = PTR_ERR(priv->phydev);
1658 priv->phydev = NULL;
1659 goto err;
1660 }
1661
1662 priv->link = 0;
1663 priv->speed = 0;
1664 priv->duplex = ~0;
1665
1666 dev_info(emac_dev, "attached PHY driver [%s] "
1667 "(mii_bus:phy_addr=%s, id=%x)\n",
1668 priv->phydev->drv->name, dev_name(&priv->phydev->dev),
1669 priv->phydev->phy_id);
1670 }
1671
1672 if (!priv->phydev) {
1673 /* No PHY , fix the link, speed and duplex settings */
1674 dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
1675 priv->link = 1;
1676 priv->speed = SPEED_100;
1677 priv->duplex = DUPLEX_FULL;
1678 emac_update_phystatus(priv);
1679 }
1680
1681 if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
1682 emac_dump_regs(priv);
1683
1684 if (netif_msg_drv(priv))
1685 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
1686
1687 if (priv->phydev)
1688 phy_start(priv->phydev);
1689
1690 return 0;
1691
1692 err:
1693 emac_int_disable(priv);
1694 napi_disable(&priv->napi);
1695
1696 rollback:
1697 for (q = res_num; q >= 0; q--) {
1698 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, q);
1699 /* at the first iteration, irq_num is already set to the
1700 * right value
1701 */
1702 if (q != res_num)
1703 irq_num = res->end;
1704
1705 for (m = irq_num; m >= res->start; m--)
1706 free_irq(m, ndev);
1707 }
1708 cpdma_ctlr_stop(priv->dma);
1709 pm_runtime_put(&priv->pdev->dev);
1710 return ret;
1711 }
1712
1713 /**
1714 * emac_dev_stop - EMAC device stop
1715 * @ndev: The DaVinci EMAC network adapter
1716 *
1717 * Called when system wants to stop or down the interface. We stop the network
1718 * queue, disable interrupts and cleanup TX/RX channels.
1719 *
1720 * We return the statistics in net_device_stats structure pulled from emac
1721 */
emac_dev_stop(struct net_device * ndev)1722 static int emac_dev_stop(struct net_device *ndev)
1723 {
1724 struct resource *res;
1725 int i = 0;
1726 int irq_num;
1727 struct emac_priv *priv = netdev_priv(ndev);
1728 struct device *emac_dev = &ndev->dev;
1729
1730 /* inform the upper layers. */
1731 netif_stop_queue(ndev);
1732 napi_disable(&priv->napi);
1733
1734 netif_carrier_off(ndev);
1735 emac_int_disable(priv);
1736 cpdma_ctlr_stop(priv->dma);
1737 emac_write(EMAC_SOFTRESET, 1);
1738
1739 if (priv->phydev)
1740 phy_disconnect(priv->phydev);
1741
1742 /* Free IRQ */
1743 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
1744 for (irq_num = res->start; irq_num <= res->end; irq_num++)
1745 free_irq(irq_num, priv->ndev);
1746 i++;
1747 }
1748
1749 if (netif_msg_drv(priv))
1750 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
1751
1752 pm_runtime_put(&priv->pdev->dev);
1753 return 0;
1754 }
1755
1756 /**
1757 * emac_dev_getnetstats - EMAC get statistics function
1758 * @ndev: The DaVinci EMAC network adapter
1759 *
1760 * Called when system wants to get statistics from the device.
1761 *
1762 * We return the statistics in net_device_stats structure pulled from emac
1763 */
emac_dev_getnetstats(struct net_device * ndev)1764 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
1765 {
1766 struct emac_priv *priv = netdev_priv(ndev);
1767 u32 mac_control;
1768 u32 stats_clear_mask;
1769 int err;
1770
1771 err = pm_runtime_get_sync(&priv->pdev->dev);
1772 if (err < 0) {
1773 pm_runtime_put_noidle(&priv->pdev->dev);
1774 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
1775 __func__, err);
1776 return &ndev->stats;
1777 }
1778
1779 /* update emac hardware stats and reset the registers*/
1780
1781 mac_control = emac_read(EMAC_MACCONTROL);
1782
1783 if (mac_control & EMAC_MACCONTROL_GMIIEN)
1784 stats_clear_mask = EMAC_STATS_CLR_MASK;
1785 else
1786 stats_clear_mask = 0;
1787
1788 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
1789 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
1790
1791 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
1792 emac_read(EMAC_TXSINGLECOLL) +
1793 emac_read(EMAC_TXMULTICOLL));
1794 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
1795 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
1796 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
1797
1798 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
1799 emac_read(EMAC_RXJABBER) +
1800 emac_read(EMAC_RXUNDERSIZED));
1801 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
1802 emac_write(EMAC_RXJABBER, stats_clear_mask);
1803 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
1804
1805 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
1806 emac_read(EMAC_RXMOFOVERRUNS));
1807 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
1808 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
1809
1810 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
1811 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
1812
1813 ndev->stats.tx_carrier_errors +=
1814 emac_read(EMAC_TXCARRIERSENSE);
1815 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
1816
1817 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
1818 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
1819
1820 pm_runtime_put(&priv->pdev->dev);
1821
1822 return &ndev->stats;
1823 }
1824
1825 static const struct net_device_ops emac_netdev_ops = {
1826 .ndo_open = emac_dev_open,
1827 .ndo_stop = emac_dev_stop,
1828 .ndo_start_xmit = emac_dev_xmit,
1829 .ndo_set_rx_mode = emac_dev_mcast_set,
1830 .ndo_set_mac_address = emac_dev_setmac_addr,
1831 .ndo_do_ioctl = emac_devioctl,
1832 .ndo_tx_timeout = emac_dev_tx_timeout,
1833 .ndo_get_stats = emac_dev_getnetstats,
1834 #ifdef CONFIG_NET_POLL_CONTROLLER
1835 .ndo_poll_controller = emac_poll_controller,
1836 #endif
1837 };
1838
1839 static const struct of_device_id davinci_emac_of_match[];
1840
1841 static struct emac_platform_data *
davinci_emac_of_get_pdata(struct platform_device * pdev,struct emac_priv * priv)1842 davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv)
1843 {
1844 struct device_node *np;
1845 const struct of_device_id *match;
1846 const struct emac_platform_data *auxdata;
1847 struct emac_platform_data *pdata = NULL;
1848 const u8 *mac_addr;
1849
1850 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
1851 return dev_get_platdata(&pdev->dev);
1852
1853 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1854 if (!pdata)
1855 return NULL;
1856
1857 np = pdev->dev.of_node;
1858 pdata->version = EMAC_VERSION_2;
1859
1860 if (!is_valid_ether_addr(pdata->mac_addr)) {
1861 mac_addr = of_get_mac_address(np);
1862 if (mac_addr)
1863 ether_addr_copy(pdata->mac_addr, mac_addr);
1864 }
1865
1866 of_property_read_u32(np, "ti,davinci-ctrl-reg-offset",
1867 &pdata->ctrl_reg_offset);
1868
1869 of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset",
1870 &pdata->ctrl_mod_reg_offset);
1871
1872 of_property_read_u32(np, "ti,davinci-ctrl-ram-offset",
1873 &pdata->ctrl_ram_offset);
1874
1875 of_property_read_u32(np, "ti,davinci-ctrl-ram-size",
1876 &pdata->ctrl_ram_size);
1877
1878 of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en);
1879
1880 pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram");
1881
1882 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
1883 if (!priv->phy_node) {
1884 if (!of_phy_is_fixed_link(np))
1885 pdata->phy_id = NULL;
1886 else if (of_phy_register_fixed_link(np) >= 0)
1887 priv->phy_node = of_node_get(np);
1888 }
1889
1890 auxdata = pdev->dev.platform_data;
1891 if (auxdata) {
1892 pdata->interrupt_enable = auxdata->interrupt_enable;
1893 pdata->interrupt_disable = auxdata->interrupt_disable;
1894 }
1895
1896 match = of_match_device(davinci_emac_of_match, &pdev->dev);
1897 if (match && match->data) {
1898 auxdata = match->data;
1899 pdata->version = auxdata->version;
1900 pdata->hw_ram_addr = auxdata->hw_ram_addr;
1901 }
1902
1903 return pdata;
1904 }
1905
davinci_emac_try_get_mac(struct platform_device * pdev,int instance,u8 * mac_addr)1906 static int davinci_emac_try_get_mac(struct platform_device *pdev,
1907 int instance, u8 *mac_addr)
1908 {
1909 if (!pdev->dev.of_node)
1910 return -EINVAL;
1911
1912 return ti_cm_get_macid(&pdev->dev, instance, mac_addr);
1913 }
1914
1915 /**
1916 * davinci_emac_probe - EMAC device probe
1917 * @pdev: The DaVinci EMAC device that we are removing
1918 *
1919 * Called when probing for emac devicesr. We get details of instances and
1920 * resource information from platform init and register a network device
1921 * and allocate resources necessary for driver to perform
1922 */
davinci_emac_probe(struct platform_device * pdev)1923 static int davinci_emac_probe(struct platform_device *pdev)
1924 {
1925 int rc = 0;
1926 struct resource *res, *res_ctrl;
1927 struct net_device *ndev;
1928 struct emac_priv *priv;
1929 unsigned long hw_ram_addr;
1930 struct emac_platform_data *pdata;
1931 struct cpdma_params dma_params;
1932 struct clk *emac_clk;
1933 unsigned long emac_bus_frequency;
1934
1935
1936 /* obtain emac clock from kernel */
1937 emac_clk = devm_clk_get(&pdev->dev, NULL);
1938 if (IS_ERR(emac_clk)) {
1939 dev_err(&pdev->dev, "failed to get EMAC clock\n");
1940 return -EBUSY;
1941 }
1942 emac_bus_frequency = clk_get_rate(emac_clk);
1943 devm_clk_put(&pdev->dev, emac_clk);
1944
1945 /* TODO: Probe PHY here if possible */
1946
1947 ndev = alloc_etherdev(sizeof(struct emac_priv));
1948 if (!ndev)
1949 return -ENOMEM;
1950
1951 platform_set_drvdata(pdev, ndev);
1952 priv = netdev_priv(ndev);
1953 priv->pdev = pdev;
1954 priv->ndev = ndev;
1955 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
1956
1957 spin_lock_init(&priv->lock);
1958
1959 pdata = davinci_emac_of_get_pdata(pdev, priv);
1960 if (!pdata) {
1961 dev_err(&pdev->dev, "no platform data\n");
1962 rc = -ENODEV;
1963 goto no_pdata;
1964 }
1965
1966 /* MAC addr and PHY mask , RMII enable info from platform_data */
1967 memcpy(priv->mac_addr, pdata->mac_addr, ETH_ALEN);
1968 priv->phy_id = pdata->phy_id;
1969 priv->rmii_en = pdata->rmii_en;
1970 priv->version = pdata->version;
1971 priv->int_enable = pdata->interrupt_enable;
1972 priv->int_disable = pdata->interrupt_disable;
1973
1974 priv->coal_intvl = 0;
1975 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
1976
1977 /* Get EMAC platform data */
1978 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1979 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
1980 priv->remap_addr = devm_ioremap_resource(&pdev->dev, res);
1981 if (IS_ERR(priv->remap_addr)) {
1982 rc = PTR_ERR(priv->remap_addr);
1983 goto no_pdata;
1984 }
1985
1986 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1987 if (res_ctrl) {
1988 priv->ctrl_base =
1989 devm_ioremap_resource(&pdev->dev, res_ctrl);
1990 if (IS_ERR(priv->ctrl_base)) {
1991 rc = PTR_ERR(priv->ctrl_base);
1992 goto no_pdata;
1993 }
1994 } else {
1995 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
1996 }
1997
1998 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
1999 ndev->base_addr = (unsigned long)priv->remap_addr;
2000
2001 hw_ram_addr = pdata->hw_ram_addr;
2002 if (!hw_ram_addr)
2003 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
2004
2005 memset(&dma_params, 0, sizeof(dma_params));
2006 dma_params.dev = &pdev->dev;
2007 dma_params.dmaregs = priv->emac_base;
2008 dma_params.rxthresh = priv->emac_base + 0x120;
2009 dma_params.rxfree = priv->emac_base + 0x140;
2010 dma_params.txhdp = priv->emac_base + 0x600;
2011 dma_params.rxhdp = priv->emac_base + 0x620;
2012 dma_params.txcp = priv->emac_base + 0x640;
2013 dma_params.rxcp = priv->emac_base + 0x660;
2014 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
2015 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
2016 dma_params.desc_hw_addr = hw_ram_addr;
2017 dma_params.desc_mem_size = pdata->ctrl_ram_size;
2018 dma_params.desc_align = 16;
2019
2020 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
2021 (u32 __force)res->start + pdata->ctrl_ram_offset;
2022
2023 priv->dma = cpdma_ctlr_create(&dma_params);
2024 if (!priv->dma) {
2025 dev_err(&pdev->dev, "error initializing DMA\n");
2026 rc = -ENOMEM;
2027 goto no_pdata;
2028 }
2029
2030 priv->txchan = cpdma_chan_create(priv->dma, tx_chan_num(EMAC_DEF_TX_CH),
2031 emac_tx_handler);
2032 priv->rxchan = cpdma_chan_create(priv->dma, rx_chan_num(EMAC_DEF_RX_CH),
2033 emac_rx_handler);
2034 if (WARN_ON(!priv->txchan || !priv->rxchan)) {
2035 rc = -ENOMEM;
2036 goto no_cpdma_chan;
2037 }
2038
2039 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2040 if (!res) {
2041 dev_err(&pdev->dev, "error getting irq res\n");
2042 rc = -ENOENT;
2043 goto no_cpdma_chan;
2044 }
2045 ndev->irq = res->start;
2046
2047 rc = davinci_emac_try_get_mac(pdev, res_ctrl ? 0 : 1, priv->mac_addr);
2048 if (!rc)
2049 ether_addr_copy(ndev->dev_addr, priv->mac_addr);
2050
2051 if (!is_valid_ether_addr(priv->mac_addr)) {
2052 /* Use random MAC if none passed */
2053 eth_hw_addr_random(ndev);
2054 memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len);
2055 dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
2056 priv->mac_addr);
2057 }
2058
2059 ndev->netdev_ops = &emac_netdev_ops;
2060 ndev->ethtool_ops = ðtool_ops;
2061 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
2062
2063 pm_runtime_enable(&pdev->dev);
2064 rc = pm_runtime_get_sync(&pdev->dev);
2065 if (rc < 0) {
2066 pm_runtime_put_noidle(&pdev->dev);
2067 dev_err(&pdev->dev, "%s: failed to get_sync(%d)\n",
2068 __func__, rc);
2069 goto no_cpdma_chan;
2070 }
2071
2072 /* register the network device */
2073 SET_NETDEV_DEV(ndev, &pdev->dev);
2074 rc = register_netdev(ndev);
2075 if (rc) {
2076 dev_err(&pdev->dev, "error in register_netdev\n");
2077 rc = -ENODEV;
2078 pm_runtime_put(&pdev->dev);
2079 goto no_cpdma_chan;
2080 }
2081
2082
2083 if (netif_msg_probe(priv)) {
2084 dev_notice(&pdev->dev, "DaVinci EMAC Probe found device "
2085 "(regs: %p, irq: %d)\n",
2086 (void *)priv->emac_base_phys, ndev->irq);
2087 }
2088 pm_runtime_put(&pdev->dev);
2089
2090 return 0;
2091
2092 no_cpdma_chan:
2093 if (priv->txchan)
2094 cpdma_chan_destroy(priv->txchan);
2095 if (priv->rxchan)
2096 cpdma_chan_destroy(priv->rxchan);
2097 cpdma_ctlr_destroy(priv->dma);
2098 no_pdata:
2099 free_netdev(ndev);
2100 return rc;
2101 }
2102
2103 /**
2104 * davinci_emac_remove - EMAC device remove
2105 * @pdev: The DaVinci EMAC device that we are removing
2106 *
2107 * Called when removing the device driver. We disable clock usage and release
2108 * the resources taken up by the driver and unregister network device
2109 */
davinci_emac_remove(struct platform_device * pdev)2110 static int davinci_emac_remove(struct platform_device *pdev)
2111 {
2112 struct net_device *ndev = platform_get_drvdata(pdev);
2113 struct emac_priv *priv = netdev_priv(ndev);
2114
2115 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
2116
2117 if (priv->txchan)
2118 cpdma_chan_destroy(priv->txchan);
2119 if (priv->rxchan)
2120 cpdma_chan_destroy(priv->rxchan);
2121 cpdma_ctlr_destroy(priv->dma);
2122
2123 unregister_netdev(ndev);
2124 of_node_put(priv->phy_node);
2125 free_netdev(ndev);
2126
2127 return 0;
2128 }
2129
davinci_emac_suspend(struct device * dev)2130 static int davinci_emac_suspend(struct device *dev)
2131 {
2132 struct platform_device *pdev = to_platform_device(dev);
2133 struct net_device *ndev = platform_get_drvdata(pdev);
2134
2135 if (netif_running(ndev))
2136 emac_dev_stop(ndev);
2137
2138 return 0;
2139 }
2140
davinci_emac_resume(struct device * dev)2141 static int davinci_emac_resume(struct device *dev)
2142 {
2143 struct platform_device *pdev = to_platform_device(dev);
2144 struct net_device *ndev = platform_get_drvdata(pdev);
2145
2146 if (netif_running(ndev))
2147 emac_dev_open(ndev);
2148
2149 return 0;
2150 }
2151
2152 static const struct dev_pm_ops davinci_emac_pm_ops = {
2153 .suspend = davinci_emac_suspend,
2154 .resume = davinci_emac_resume,
2155 };
2156
2157 #if IS_ENABLED(CONFIG_OF)
2158 static const struct emac_platform_data am3517_emac_data = {
2159 .version = EMAC_VERSION_2,
2160 .hw_ram_addr = 0x01e20000,
2161 };
2162
2163 static const struct emac_platform_data dm816_emac_data = {
2164 .version = EMAC_VERSION_2,
2165 };
2166
2167 static const struct of_device_id davinci_emac_of_match[] = {
2168 {.compatible = "ti,davinci-dm6467-emac", },
2169 {.compatible = "ti,am3517-emac", .data = &am3517_emac_data, },
2170 {.compatible = "ti,dm816-emac", .data = &dm816_emac_data, },
2171 {},
2172 };
2173 MODULE_DEVICE_TABLE(of, davinci_emac_of_match);
2174 #endif
2175
2176 /* davinci_emac_driver: EMAC platform driver structure */
2177 static struct platform_driver davinci_emac_driver = {
2178 .driver = {
2179 .name = "davinci_emac",
2180 .pm = &davinci_emac_pm_ops,
2181 .of_match_table = of_match_ptr(davinci_emac_of_match),
2182 },
2183 .probe = davinci_emac_probe,
2184 .remove = davinci_emac_remove,
2185 };
2186
2187 /**
2188 * davinci_emac_init - EMAC driver module init
2189 *
2190 * Called when initializing the driver. We register the driver with
2191 * the platform.
2192 */
davinci_emac_init(void)2193 static int __init davinci_emac_init(void)
2194 {
2195 return platform_driver_register(&davinci_emac_driver);
2196 }
2197 late_initcall(davinci_emac_init);
2198
2199 /**
2200 * davinci_emac_exit - EMAC driver module exit
2201 *
2202 * Called when exiting the driver completely. We unregister the driver with
2203 * the platform and exit
2204 */
davinci_emac_exit(void)2205 static void __exit davinci_emac_exit(void)
2206 {
2207 platform_driver_unregister(&davinci_emac_driver);
2208 }
2209 module_exit(davinci_emac_exit);
2210
2211 MODULE_LICENSE("GPL");
2212 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2213 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2214 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");
2215