1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21 /*
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
24 */
25
26 /*
27 * This is used to catch non optimized PT_GUEST_(DIRTY|ACCESS)_SHIFT macro
28 * uses for EPT without A/D paging type.
29 */
30 extern u64 __pure __using_nonexistent_pte_bit(void)
31 __compiletime_error("wrong use of PT_GUEST_(DIRTY|ACCESS)_SHIFT");
32
33 #if PTTYPE == 64
34 #define pt_element_t u64
35 #define guest_walker guest_walker64
36 #define FNAME(name) paging##64_##name
37 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
38 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
39 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
40 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
41 #define PT_LEVEL_BITS PT64_LEVEL_BITS
42 #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK
43 #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK
44 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
45 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
46 #ifdef CONFIG_X86_64
47 #define PT_MAX_FULL_LEVELS 4
48 #define CMPXCHG cmpxchg
49 #else
50 #define CMPXCHG cmpxchg64
51 #define PT_MAX_FULL_LEVELS 2
52 #endif
53 #elif PTTYPE == 32
54 #define pt_element_t u32
55 #define guest_walker guest_walker32
56 #define FNAME(name) paging##32_##name
57 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
58 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
59 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
60 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
61 #define PT_LEVEL_BITS PT32_LEVEL_BITS
62 #define PT_MAX_FULL_LEVELS 2
63 #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK
64 #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK
65 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
66 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
67 #define CMPXCHG cmpxchg
68 #elif PTTYPE == PTTYPE_EPT
69 #define pt_element_t u64
70 #define guest_walker guest_walkerEPT
71 #define FNAME(name) ept_##name
72 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
73 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
74 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
75 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
76 #define PT_LEVEL_BITS PT64_LEVEL_BITS
77 #define PT_GUEST_ACCESSED_MASK 0
78 #define PT_GUEST_DIRTY_MASK 0
79 #define PT_GUEST_DIRTY_SHIFT __using_nonexistent_pte_bit()
80 #define PT_GUEST_ACCESSED_SHIFT __using_nonexistent_pte_bit()
81 #define CMPXCHG cmpxchg64
82 #define PT_MAX_FULL_LEVELS 4
83 #else
84 #error Invalid PTTYPE value
85 #endif
86
87 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
88 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
89
90 /*
91 * The guest_walker structure emulates the behavior of the hardware page
92 * table walker.
93 */
94 struct guest_walker {
95 int level;
96 unsigned max_level;
97 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
98 pt_element_t ptes[PT_MAX_FULL_LEVELS];
99 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
100 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
101 pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
102 bool pte_writable[PT_MAX_FULL_LEVELS];
103 unsigned pt_access;
104 unsigned pte_access;
105 gfn_t gfn;
106 struct x86_exception fault;
107 };
108
gpte_to_gfn_lvl(pt_element_t gpte,int lvl)109 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
110 {
111 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
112 }
113
FNAME(protect_clean_gpte)114 static inline void FNAME(protect_clean_gpte)(unsigned *access, unsigned gpte)
115 {
116 unsigned mask;
117
118 /* dirty bit is not supported, so no need to track it */
119 if (!PT_GUEST_DIRTY_MASK)
120 return;
121
122 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
123
124 mask = (unsigned)~ACC_WRITE_MASK;
125 /* Allow write access to dirty gptes */
126 mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) &
127 PT_WRITABLE_MASK;
128 *access &= mask;
129 }
130
FNAME(is_present_gpte)131 static inline int FNAME(is_present_gpte)(unsigned long pte)
132 {
133 #if PTTYPE != PTTYPE_EPT
134 return is_present_gpte(pte);
135 #else
136 return pte & 7;
137 #endif
138 }
139
FNAME(cmpxchg_gpte)140 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
141 pt_element_t __user *ptep_user, unsigned index,
142 pt_element_t orig_pte, pt_element_t new_pte)
143 {
144 int npages;
145 pt_element_t ret;
146 pt_element_t *table;
147 struct page *page;
148
149 npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
150 /* Check if the user is doing something meaningless. */
151 if (unlikely(npages != 1))
152 return -EFAULT;
153
154 table = kmap_atomic(page);
155 ret = CMPXCHG(&table[index], orig_pte, new_pte);
156 kunmap_atomic(table);
157
158 kvm_release_page_dirty(page);
159
160 return (ret != orig_pte);
161 }
162
FNAME(prefetch_invalid_gpte)163 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
164 struct kvm_mmu_page *sp, u64 *spte,
165 u64 gpte)
166 {
167 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
168 goto no_present;
169
170 if (!FNAME(is_present_gpte)(gpte))
171 goto no_present;
172
173 /* if accessed bit is not supported prefetch non accessed gpte */
174 if (PT_GUEST_ACCESSED_MASK && !(gpte & PT_GUEST_ACCESSED_MASK))
175 goto no_present;
176
177 return false;
178
179 no_present:
180 drop_spte(vcpu->kvm, spte);
181 return true;
182 }
183
FNAME(gpte_access)184 static inline unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, u64 gpte)
185 {
186 unsigned access;
187 #if PTTYPE == PTTYPE_EPT
188 access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) |
189 ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) |
190 ACC_USER_MASK;
191 #else
192 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
193 access &= ~(gpte >> PT64_NX_SHIFT);
194 #endif
195
196 return access;
197 }
198
FNAME(update_accessed_dirty_bits)199 static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
200 struct kvm_mmu *mmu,
201 struct guest_walker *walker,
202 int write_fault)
203 {
204 unsigned level, index;
205 pt_element_t pte, orig_pte;
206 pt_element_t __user *ptep_user;
207 gfn_t table_gfn;
208 int ret;
209
210 /* dirty/accessed bits are not supported, so no need to update them */
211 if (!PT_GUEST_DIRTY_MASK)
212 return 0;
213
214 for (level = walker->max_level; level >= walker->level; --level) {
215 pte = orig_pte = walker->ptes[level - 1];
216 table_gfn = walker->table_gfn[level - 1];
217 ptep_user = walker->ptep_user[level - 1];
218 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
219 if (!(pte & PT_GUEST_ACCESSED_MASK)) {
220 trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
221 pte |= PT_GUEST_ACCESSED_MASK;
222 }
223 if (level == walker->level && write_fault &&
224 !(pte & PT_GUEST_DIRTY_MASK)) {
225 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
226 pte |= PT_GUEST_DIRTY_MASK;
227 }
228 if (pte == orig_pte)
229 continue;
230
231 /*
232 * If the slot is read-only, simply do not process the accessed
233 * and dirty bits. This is the correct thing to do if the slot
234 * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
235 * are only supported if the accessed and dirty bits are already
236 * set in the ROM (so that MMIO writes are never needed).
237 *
238 * Note that NPT does not allow this at all and faults, since
239 * it always wants nested page table entries for the guest
240 * page tables to be writable. And EPT works but will simply
241 * overwrite the read-only memory to set the accessed and dirty
242 * bits.
243 */
244 if (unlikely(!walker->pte_writable[level - 1]))
245 continue;
246
247 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
248 if (ret)
249 return ret;
250
251 kvm_vcpu_mark_page_dirty(vcpu, table_gfn);
252 walker->ptes[level - 1] = pte;
253 }
254 return 0;
255 }
256
257 /*
258 * Fetch a guest pte for a guest virtual address
259 */
FNAME(walk_addr_generic)260 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
261 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
262 gva_t addr, u32 access)
263 {
264 int ret;
265 pt_element_t pte;
266 pt_element_t __user *uninitialized_var(ptep_user);
267 gfn_t table_gfn;
268 unsigned index, pt_access, pte_access, accessed_dirty;
269 gpa_t pte_gpa;
270 int offset;
271 const int write_fault = access & PFERR_WRITE_MASK;
272 const int user_fault = access & PFERR_USER_MASK;
273 const int fetch_fault = access & PFERR_FETCH_MASK;
274 u16 errcode = 0;
275 gpa_t real_gpa;
276 gfn_t gfn;
277
278 trace_kvm_mmu_pagetable_walk(addr, access);
279 retry_walk:
280 walker->level = mmu->root_level;
281 pte = mmu->get_cr3(vcpu);
282
283 #if PTTYPE == 64
284 if (walker->level == PT32E_ROOT_LEVEL) {
285 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
286 trace_kvm_mmu_paging_element(pte, walker->level);
287 if (!FNAME(is_present_gpte)(pte))
288 goto error;
289 --walker->level;
290 }
291 #endif
292 walker->max_level = walker->level;
293 ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu)));
294
295 accessed_dirty = PT_GUEST_ACCESSED_MASK;
296 pt_access = pte_access = ACC_ALL;
297 ++walker->level;
298
299 do {
300 gfn_t real_gfn;
301 unsigned long host_addr;
302
303 pt_access &= pte_access;
304 --walker->level;
305
306 index = PT_INDEX(addr, walker->level);
307
308 table_gfn = gpte_to_gfn(pte);
309 offset = index * sizeof(pt_element_t);
310 pte_gpa = gfn_to_gpa(table_gfn) + offset;
311 walker->table_gfn[walker->level - 1] = table_gfn;
312 walker->pte_gpa[walker->level - 1] = pte_gpa;
313
314 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
315 PFERR_USER_MASK|PFERR_WRITE_MASK,
316 &walker->fault);
317
318 /*
319 * FIXME: This can happen if emulation (for of an INS/OUTS
320 * instruction) triggers a nested page fault. The exit
321 * qualification / exit info field will incorrectly have
322 * "guest page access" as the nested page fault's cause,
323 * instead of "guest page structure access". To fix this,
324 * the x86_exception struct should be augmented with enough
325 * information to fix the exit_qualification or exit_info_1
326 * fields.
327 */
328 if (unlikely(real_gfn == UNMAPPED_GVA))
329 return 0;
330
331 real_gfn = gpa_to_gfn(real_gfn);
332
333 host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, real_gfn,
334 &walker->pte_writable[walker->level - 1]);
335 if (unlikely(kvm_is_error_hva(host_addr)))
336 goto error;
337
338 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
339 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
340 goto error;
341 walker->ptep_user[walker->level - 1] = ptep_user;
342
343 trace_kvm_mmu_paging_element(pte, walker->level);
344
345 if (unlikely(!FNAME(is_present_gpte)(pte)))
346 goto error;
347
348 if (unlikely(is_rsvd_bits_set(mmu, pte, walker->level))) {
349 errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
350 goto error;
351 }
352
353 accessed_dirty &= pte;
354 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
355
356 walker->ptes[walker->level - 1] = pte;
357 } while (!is_last_gpte(mmu, walker->level, pte));
358
359 if (unlikely(permission_fault(vcpu, mmu, pte_access, access))) {
360 errcode |= PFERR_PRESENT_MASK;
361 goto error;
362 }
363
364 gfn = gpte_to_gfn_lvl(pte, walker->level);
365 gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
366
367 if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36())
368 gfn += pse36_gfn_delta(pte);
369
370 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault);
371 if (real_gpa == UNMAPPED_GVA)
372 return 0;
373
374 walker->gfn = real_gpa >> PAGE_SHIFT;
375
376 if (!write_fault)
377 FNAME(protect_clean_gpte)(&pte_access, pte);
378 else
379 /*
380 * On a write fault, fold the dirty bit into accessed_dirty.
381 * For modes without A/D bits support accessed_dirty will be
382 * always clear.
383 */
384 accessed_dirty &= pte >>
385 (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT);
386
387 if (unlikely(!accessed_dirty)) {
388 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault);
389 if (unlikely(ret < 0))
390 goto error;
391 else if (ret)
392 goto retry_walk;
393 }
394
395 walker->pt_access = pt_access;
396 walker->pte_access = pte_access;
397 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
398 __func__, (u64)pte, pte_access, pt_access);
399 return 1;
400
401 error:
402 errcode |= write_fault | user_fault;
403 if (fetch_fault && (mmu->nx ||
404 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
405 errcode |= PFERR_FETCH_MASK;
406
407 walker->fault.vector = PF_VECTOR;
408 walker->fault.error_code_valid = true;
409 walker->fault.error_code = errcode;
410
411 #if PTTYPE == PTTYPE_EPT
412 /*
413 * Use PFERR_RSVD_MASK in error_code to to tell if EPT
414 * misconfiguration requires to be injected. The detection is
415 * done by is_rsvd_bits_set() above.
416 *
417 * We set up the value of exit_qualification to inject:
418 * [2:0] - Derive from [2:0] of real exit_qualification at EPT violation
419 * [5:3] - Calculated by the page walk of the guest EPT page tables
420 * [7:8] - Derived from [7:8] of real exit_qualification
421 *
422 * The other bits are set to 0.
423 */
424 if (!(errcode & PFERR_RSVD_MASK)) {
425 vcpu->arch.exit_qualification &= 0x187;
426 vcpu->arch.exit_qualification |= ((pt_access & pte) & 0x7) << 3;
427 }
428 #endif
429 walker->fault.address = addr;
430 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
431
432 trace_kvm_mmu_walker_error(walker->fault.error_code);
433 return 0;
434 }
435
FNAME(walk_addr)436 static int FNAME(walk_addr)(struct guest_walker *walker,
437 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
438 {
439 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
440 access);
441 }
442
443 #if PTTYPE != PTTYPE_EPT
FNAME(walk_addr_nested)444 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
445 struct kvm_vcpu *vcpu, gva_t addr,
446 u32 access)
447 {
448 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
449 addr, access);
450 }
451 #endif
452
453 static bool
FNAME(prefetch_gpte)454 FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
455 u64 *spte, pt_element_t gpte, bool no_dirty_log)
456 {
457 unsigned pte_access;
458 gfn_t gfn;
459 pfn_t pfn;
460
461 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
462 return false;
463
464 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
465
466 gfn = gpte_to_gfn(gpte);
467 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
468 FNAME(protect_clean_gpte)(&pte_access, gpte);
469 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
470 no_dirty_log && (pte_access & ACC_WRITE_MASK));
471 if (is_error_pfn(pfn))
472 return false;
473
474 /*
475 * we call mmu_set_spte() with host_writable = true because
476 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
477 */
478 mmu_set_spte(vcpu, spte, pte_access, 0, NULL, PT_PAGE_TABLE_LEVEL,
479 gfn, pfn, true, true);
480
481 return true;
482 }
483
FNAME(update_pte)484 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
485 u64 *spte, const void *pte)
486 {
487 pt_element_t gpte = *(const pt_element_t *)pte;
488
489 FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
490 }
491
FNAME(gpte_changed)492 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
493 struct guest_walker *gw, int level)
494 {
495 pt_element_t curr_pte;
496 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
497 u64 mask;
498 int r, index;
499
500 if (level == PT_PAGE_TABLE_LEVEL) {
501 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
502 base_gpa = pte_gpa & ~mask;
503 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
504
505 r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa,
506 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
507 curr_pte = gw->prefetch_ptes[index];
508 } else
509 r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa,
510 &curr_pte, sizeof(curr_pte));
511
512 return r || curr_pte != gw->ptes[level - 1];
513 }
514
FNAME(pte_prefetch)515 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
516 u64 *sptep)
517 {
518 struct kvm_mmu_page *sp;
519 pt_element_t *gptep = gw->prefetch_ptes;
520 u64 *spte;
521 int i;
522
523 sp = page_header(__pa(sptep));
524
525 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
526 return;
527
528 if (sp->role.direct)
529 return __direct_pte_prefetch(vcpu, sp, sptep);
530
531 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
532 spte = sp->spt + i;
533
534 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
535 if (spte == sptep)
536 continue;
537
538 if (is_shadow_present_pte(*spte))
539 continue;
540
541 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
542 break;
543 }
544 }
545
546 /*
547 * Fetch a shadow pte for a specific level in the paging hierarchy.
548 * If the guest tries to write a write-protected page, we need to
549 * emulate this operation, return 1 to indicate this case.
550 */
FNAME(fetch)551 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
552 struct guest_walker *gw,
553 int write_fault, int hlevel,
554 pfn_t pfn, bool map_writable, bool prefault)
555 {
556 struct kvm_mmu_page *sp = NULL;
557 struct kvm_shadow_walk_iterator it;
558 unsigned direct_access, access = gw->pt_access;
559 int top_level, emulate = 0;
560
561 direct_access = gw->pte_access;
562
563 top_level = vcpu->arch.mmu.root_level;
564 if (top_level == PT32E_ROOT_LEVEL)
565 top_level = PT32_ROOT_LEVEL;
566 /*
567 * Verify that the top-level gpte is still there. Since the page
568 * is a root page, it is either write protected (and cannot be
569 * changed from now on) or it is invalid (in which case, we don't
570 * really care if it changes underneath us after this point).
571 */
572 if (FNAME(gpte_changed)(vcpu, gw, top_level))
573 goto out_gpte_changed;
574
575 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
576 goto out_gpte_changed;
577
578 for (shadow_walk_init(&it, vcpu, addr);
579 shadow_walk_okay(&it) && it.level > gw->level;
580 shadow_walk_next(&it)) {
581 gfn_t table_gfn;
582
583 clear_sp_write_flooding_count(it.sptep);
584 drop_large_spte(vcpu, it.sptep);
585
586 sp = NULL;
587 if (!is_shadow_present_pte(*it.sptep)) {
588 table_gfn = gw->table_gfn[it.level - 2];
589 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
590 false, access, it.sptep);
591 }
592
593 /*
594 * Verify that the gpte in the page we've just write
595 * protected is still there.
596 */
597 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
598 goto out_gpte_changed;
599
600 if (sp)
601 link_shadow_page(it.sptep, sp, PT_GUEST_ACCESSED_MASK);
602 }
603
604 for (;
605 shadow_walk_okay(&it) && it.level > hlevel;
606 shadow_walk_next(&it)) {
607 gfn_t direct_gfn;
608
609 clear_sp_write_flooding_count(it.sptep);
610 validate_direct_spte(vcpu, it.sptep, direct_access);
611
612 drop_large_spte(vcpu, it.sptep);
613
614 if (is_shadow_present_pte(*it.sptep))
615 continue;
616
617 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
618
619 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
620 true, direct_access, it.sptep);
621 link_shadow_page(it.sptep, sp, PT_GUEST_ACCESSED_MASK);
622 }
623
624 clear_sp_write_flooding_count(it.sptep);
625 mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, &emulate,
626 it.level, gw->gfn, pfn, prefault, map_writable);
627 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
628
629 return emulate;
630
631 out_gpte_changed:
632 if (sp)
633 kvm_mmu_put_page(sp, it.sptep);
634 kvm_release_pfn_clean(pfn);
635 return 0;
636 }
637
638 /*
639 * To see whether the mapped gfn can write its page table in the current
640 * mapping.
641 *
642 * It is the helper function of FNAME(page_fault). When guest uses large page
643 * size to map the writable gfn which is used as current page table, we should
644 * force kvm to use small page size to map it because new shadow page will be
645 * created when kvm establishes shadow page table that stop kvm using large
646 * page size. Do it early can avoid unnecessary #PF and emulation.
647 *
648 * @write_fault_to_shadow_pgtable will return true if the fault gfn is
649 * currently used as its page table.
650 *
651 * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
652 * since the PDPT is always shadowed, that means, we can not use large page
653 * size to map the gfn which is used as PDPT.
654 */
655 static bool
FNAME(is_self_change_mapping)656 FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
657 struct guest_walker *walker, int user_fault,
658 bool *write_fault_to_shadow_pgtable)
659 {
660 int level;
661 gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
662 bool self_changed = false;
663
664 if (!(walker->pte_access & ACC_WRITE_MASK ||
665 (!is_write_protection(vcpu) && !user_fault)))
666 return false;
667
668 for (level = walker->level; level <= walker->max_level; level++) {
669 gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
670
671 self_changed |= !(gfn & mask);
672 *write_fault_to_shadow_pgtable |= !gfn;
673 }
674
675 return self_changed;
676 }
677
678 /*
679 * Page fault handler. There are several causes for a page fault:
680 * - there is no shadow pte for the guest pte
681 * - write access through a shadow pte marked read only so that we can set
682 * the dirty bit
683 * - write access to a shadow pte marked read only so we can update the page
684 * dirty bitmap, when userspace requests it
685 * - mmio access; in this case we will never install a present shadow pte
686 * - normal guest page fault due to the guest pte marked not present, not
687 * writable, or not executable
688 *
689 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
690 * a negative value on error.
691 */
FNAME(page_fault)692 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
693 bool prefault)
694 {
695 int write_fault = error_code & PFERR_WRITE_MASK;
696 int user_fault = error_code & PFERR_USER_MASK;
697 struct guest_walker walker;
698 int r;
699 pfn_t pfn;
700 int level = PT_PAGE_TABLE_LEVEL;
701 bool force_pt_level = false;
702 unsigned long mmu_seq;
703 bool map_writable, is_self_change_mapping;
704
705 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
706
707 if (unlikely(error_code & PFERR_RSVD_MASK)) {
708 r = handle_mmio_page_fault(vcpu, addr, mmu_is_nested(vcpu));
709 if (likely(r != RET_MMIO_PF_INVALID))
710 return r;
711
712 /*
713 * page fault with PFEC.RSVD = 1 is caused by shadow
714 * page fault, should not be used to walk guest page
715 * table.
716 */
717 error_code &= ~PFERR_RSVD_MASK;
718 };
719
720 r = mmu_topup_memory_caches(vcpu);
721 if (r)
722 return r;
723
724 /*
725 * Look up the guest pte for the faulting address.
726 */
727 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
728
729 /*
730 * The page is not mapped by the guest. Let the guest handle it.
731 */
732 if (!r) {
733 pgprintk("%s: guest page fault\n", __func__);
734 if (!prefault)
735 inject_page_fault(vcpu, &walker.fault);
736
737 return 0;
738 }
739
740 vcpu->arch.write_fault_to_shadow_pgtable = false;
741
742 is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
743 &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable);
744
745 if (walker.level >= PT_DIRECTORY_LEVEL && !is_self_change_mapping) {
746 level = mapping_level(vcpu, walker.gfn, &force_pt_level);
747 if (likely(!force_pt_level)) {
748 level = min(walker.level, level);
749 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
750 }
751 } else
752 force_pt_level = true;
753
754 mmu_seq = vcpu->kvm->mmu_notifier_seq;
755 smp_rmb();
756
757 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
758 &map_writable))
759 return 0;
760
761 if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr,
762 walker.gfn, pfn, walker.pte_access, &r))
763 return r;
764
765 /*
766 * Do not change pte_access if the pfn is a mmio page, otherwise
767 * we will cache the incorrect access into mmio spte.
768 */
769 if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) &&
770 !is_write_protection(vcpu) && !user_fault &&
771 !is_noslot_pfn(pfn)) {
772 walker.pte_access |= ACC_WRITE_MASK;
773 walker.pte_access &= ~ACC_USER_MASK;
774
775 /*
776 * If we converted a user page to a kernel page,
777 * so that the kernel can write to it when cr0.wp=0,
778 * then we should prevent the kernel from executing it
779 * if SMEP is enabled.
780 */
781 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
782 walker.pte_access &= ~ACC_EXEC_MASK;
783 }
784
785 spin_lock(&vcpu->kvm->mmu_lock);
786 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
787 goto out_unlock;
788
789 kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
790 make_mmu_pages_available(vcpu);
791 if (!force_pt_level)
792 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
793 r = FNAME(fetch)(vcpu, addr, &walker, write_fault,
794 level, pfn, map_writable, prefault);
795 ++vcpu->stat.pf_fixed;
796 kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
797 spin_unlock(&vcpu->kvm->mmu_lock);
798
799 return r;
800
801 out_unlock:
802 spin_unlock(&vcpu->kvm->mmu_lock);
803 kvm_release_pfn_clean(pfn);
804 return 0;
805 }
806
FNAME(get_level1_sp_gpa)807 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
808 {
809 int offset = 0;
810
811 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
812
813 if (PTTYPE == 32)
814 offset = sp->role.quadrant << PT64_LEVEL_BITS;
815
816 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
817 }
818
FNAME(invlpg)819 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
820 {
821 struct kvm_shadow_walk_iterator iterator;
822 struct kvm_mmu_page *sp;
823 int level;
824 u64 *sptep;
825
826 vcpu_clear_mmio_info(vcpu, gva);
827
828 /*
829 * No need to check return value here, rmap_can_add() can
830 * help us to skip pte prefetch later.
831 */
832 mmu_topup_memory_caches(vcpu);
833
834 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
835 WARN_ON(1);
836 return;
837 }
838
839 spin_lock(&vcpu->kvm->mmu_lock);
840 for_each_shadow_entry(vcpu, gva, iterator) {
841 level = iterator.level;
842 sptep = iterator.sptep;
843
844 sp = page_header(__pa(sptep));
845 if (is_last_spte(*sptep, level)) {
846 pt_element_t gpte;
847 gpa_t pte_gpa;
848
849 if (!sp->unsync)
850 break;
851
852 pte_gpa = FNAME(get_level1_sp_gpa)(sp);
853 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
854
855 if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
856 kvm_flush_remote_tlbs(vcpu->kvm);
857
858 if (!rmap_can_add(vcpu))
859 break;
860
861 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
862 sizeof(pt_element_t)))
863 break;
864
865 FNAME(update_pte)(vcpu, sp, sptep, &gpte);
866 }
867
868 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
869 break;
870 }
871 spin_unlock(&vcpu->kvm->mmu_lock);
872 }
873
FNAME(gva_to_gpa)874 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
875 struct x86_exception *exception)
876 {
877 struct guest_walker walker;
878 gpa_t gpa = UNMAPPED_GVA;
879 int r;
880
881 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
882
883 if (r) {
884 gpa = gfn_to_gpa(walker.gfn);
885 gpa |= vaddr & ~PAGE_MASK;
886 } else if (exception)
887 *exception = walker.fault;
888
889 return gpa;
890 }
891
892 #if PTTYPE != PTTYPE_EPT
FNAME(gva_to_gpa_nested)893 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
894 u32 access,
895 struct x86_exception *exception)
896 {
897 struct guest_walker walker;
898 gpa_t gpa = UNMAPPED_GVA;
899 int r;
900
901 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
902
903 if (r) {
904 gpa = gfn_to_gpa(walker.gfn);
905 gpa |= vaddr & ~PAGE_MASK;
906 } else if (exception)
907 *exception = walker.fault;
908
909 return gpa;
910 }
911 #endif
912
913 /*
914 * Using the cached information from sp->gfns is safe because:
915 * - The spte has a reference to the struct page, so the pfn for a given gfn
916 * can't change unless all sptes pointing to it are nuked first.
917 *
918 * Note:
919 * We should flush all tlbs if spte is dropped even though guest is
920 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
921 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
922 * used by guest then tlbs are not flushed, so guest is allowed to access the
923 * freed pages.
924 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
925 */
FNAME(sync_page)926 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
927 {
928 int i, nr_present = 0;
929 bool host_writable;
930 gpa_t first_pte_gpa;
931
932 /* direct kvm_mmu_page can not be unsync. */
933 BUG_ON(sp->role.direct);
934
935 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
936
937 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
938 unsigned pte_access;
939 pt_element_t gpte;
940 gpa_t pte_gpa;
941 gfn_t gfn;
942
943 if (!sp->spt[i])
944 continue;
945
946 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
947
948 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
949 sizeof(pt_element_t)))
950 return -EINVAL;
951
952 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
953 vcpu->kvm->tlbs_dirty++;
954 continue;
955 }
956
957 gfn = gpte_to_gfn(gpte);
958 pte_access = sp->role.access;
959 pte_access &= FNAME(gpte_access)(vcpu, gpte);
960 FNAME(protect_clean_gpte)(&pte_access, gpte);
961
962 if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access,
963 &nr_present))
964 continue;
965
966 if (gfn != sp->gfns[i]) {
967 drop_spte(vcpu->kvm, &sp->spt[i]);
968 vcpu->kvm->tlbs_dirty++;
969 continue;
970 }
971
972 nr_present++;
973
974 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
975
976 set_spte(vcpu, &sp->spt[i], pte_access,
977 PT_PAGE_TABLE_LEVEL, gfn,
978 spte_to_pfn(sp->spt[i]), true, false,
979 host_writable);
980 }
981
982 return !nr_present;
983 }
984
985 #undef pt_element_t
986 #undef guest_walker
987 #undef FNAME
988 #undef PT_BASE_ADDR_MASK
989 #undef PT_INDEX
990 #undef PT_LVL_ADDR_MASK
991 #undef PT_LVL_OFFSET_MASK
992 #undef PT_LEVEL_BITS
993 #undef PT_MAX_FULL_LEVELS
994 #undef gpte_to_gfn
995 #undef gpte_to_gfn_lvl
996 #undef CMPXCHG
997 #undef PT_GUEST_ACCESSED_MASK
998 #undef PT_GUEST_DIRTY_MASK
999 #undef PT_GUEST_DIRTY_SHIFT
1000 #undef PT_GUEST_ACCESSED_SHIFT
1001