1 /*
2 * Support of MSI, HPET and DMAR interrupts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
6 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Convert to hierarchical irqdomain
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #include <linux/mm.h>
14 #include <linux/interrupt.h>
15 #include <linux/pci.h>
16 #include <linux/dmar.h>
17 #include <linux/hpet.h>
18 #include <linux/msi.h>
19 #include <asm/irqdomain.h>
20 #include <asm/msidef.h>
21 #include <asm/hpet.h>
22 #include <asm/hw_irq.h>
23 #include <asm/apic.h>
24 #include <asm/irq_remapping.h>
25
26 static struct irq_domain *msi_default_domain;
27
irq_msi_compose_msg(struct irq_data * data,struct msi_msg * msg)28 static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
29 {
30 struct irq_cfg *cfg = irqd_cfg(data);
31
32 msg->address_hi = MSI_ADDR_BASE_HI;
33
34 if (x2apic_enabled())
35 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
36
37 msg->address_lo =
38 MSI_ADDR_BASE_LO |
39 ((apic->irq_dest_mode == 0) ?
40 MSI_ADDR_DEST_MODE_PHYSICAL :
41 MSI_ADDR_DEST_MODE_LOGICAL) |
42 ((apic->irq_delivery_mode != dest_LowestPrio) ?
43 MSI_ADDR_REDIRECTION_CPU :
44 MSI_ADDR_REDIRECTION_LOWPRI) |
45 MSI_ADDR_DEST_ID(cfg->dest_apicid);
46
47 msg->data =
48 MSI_DATA_TRIGGER_EDGE |
49 MSI_DATA_LEVEL_ASSERT |
50 ((apic->irq_delivery_mode != dest_LowestPrio) ?
51 MSI_DATA_DELIVERY_FIXED :
52 MSI_DATA_DELIVERY_LOWPRI) |
53 MSI_DATA_VECTOR(cfg->vector);
54 }
55
56 /*
57 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
58 * which implement the MSI or MSI-X Capability Structure.
59 */
60 static struct irq_chip pci_msi_controller = {
61 .name = "PCI-MSI",
62 .irq_unmask = pci_msi_unmask_irq,
63 .irq_mask = pci_msi_mask_irq,
64 .irq_ack = irq_chip_ack_parent,
65 .irq_retrigger = irq_chip_retrigger_hierarchy,
66 .irq_compose_msi_msg = irq_msi_compose_msg,
67 .flags = IRQCHIP_SKIP_SET_WAKE,
68 };
69
native_setup_msi_irqs(struct pci_dev * dev,int nvec,int type)70 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
71 {
72 struct irq_domain *domain;
73 struct irq_alloc_info info;
74
75 init_irq_alloc_info(&info, NULL);
76 info.type = X86_IRQ_ALLOC_TYPE_MSI;
77 info.msi_dev = dev;
78
79 domain = irq_remapping_get_irq_domain(&info);
80 if (domain == NULL)
81 domain = msi_default_domain;
82 if (domain == NULL)
83 return -ENOSYS;
84
85 return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
86 }
87
native_teardown_msi_irq(unsigned int irq)88 void native_teardown_msi_irq(unsigned int irq)
89 {
90 irq_domain_free_irqs(irq, 1);
91 }
92
pci_msi_get_hwirq(struct msi_domain_info * info,msi_alloc_info_t * arg)93 static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
94 msi_alloc_info_t *arg)
95 {
96 return arg->msi_hwirq;
97 }
98
pci_msi_prepare(struct irq_domain * domain,struct device * dev,int nvec,msi_alloc_info_t * arg)99 static int pci_msi_prepare(struct irq_domain *domain, struct device *dev,
100 int nvec, msi_alloc_info_t *arg)
101 {
102 struct pci_dev *pdev = to_pci_dev(dev);
103 struct msi_desc *desc = first_pci_msi_entry(pdev);
104
105 init_irq_alloc_info(arg, NULL);
106 arg->msi_dev = pdev;
107 if (desc->msi_attrib.is_msix) {
108 arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
109 } else {
110 arg->type = X86_IRQ_ALLOC_TYPE_MSI;
111 arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
112 }
113
114 return 0;
115 }
116
pci_msi_set_desc(msi_alloc_info_t * arg,struct msi_desc * desc)117 static void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
118 {
119 arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
120 }
121
122 static struct msi_domain_ops pci_msi_domain_ops = {
123 .get_hwirq = pci_msi_get_hwirq,
124 .msi_prepare = pci_msi_prepare,
125 .set_desc = pci_msi_set_desc,
126 };
127
128 static struct msi_domain_info pci_msi_domain_info = {
129 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
130 MSI_FLAG_PCI_MSIX,
131 .ops = &pci_msi_domain_ops,
132 .chip = &pci_msi_controller,
133 .handler = handle_edge_irq,
134 .handler_name = "edge",
135 };
136
arch_init_msi_domain(struct irq_domain * parent)137 void arch_init_msi_domain(struct irq_domain *parent)
138 {
139 if (disable_apic)
140 return;
141
142 msi_default_domain = pci_msi_create_irq_domain(NULL,
143 &pci_msi_domain_info, parent);
144 if (!msi_default_domain)
145 pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
146 }
147
148 #ifdef CONFIG_IRQ_REMAP
149 static struct irq_chip pci_msi_ir_controller = {
150 .name = "IR-PCI-MSI",
151 .irq_unmask = pci_msi_unmask_irq,
152 .irq_mask = pci_msi_mask_irq,
153 .irq_ack = irq_chip_ack_parent,
154 .irq_retrigger = irq_chip_retrigger_hierarchy,
155 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
156 .flags = IRQCHIP_SKIP_SET_WAKE,
157 };
158
159 static struct msi_domain_info pci_msi_ir_domain_info = {
160 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
161 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
162 .ops = &pci_msi_domain_ops,
163 .chip = &pci_msi_ir_controller,
164 .handler = handle_edge_irq,
165 .handler_name = "edge",
166 };
167
arch_create_msi_irq_domain(struct irq_domain * parent)168 struct irq_domain *arch_create_msi_irq_domain(struct irq_domain *parent)
169 {
170 return pci_msi_create_irq_domain(NULL, &pci_msi_ir_domain_info, parent);
171 }
172 #endif
173
174 #ifdef CONFIG_DMAR_TABLE
dmar_msi_write_msg(struct irq_data * data,struct msi_msg * msg)175 static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
176 {
177 dmar_msi_write(data->irq, msg);
178 }
179
180 static struct irq_chip dmar_msi_controller = {
181 .name = "DMAR-MSI",
182 .irq_unmask = dmar_msi_unmask,
183 .irq_mask = dmar_msi_mask,
184 .irq_ack = irq_chip_ack_parent,
185 .irq_set_affinity = msi_domain_set_affinity,
186 .irq_retrigger = irq_chip_retrigger_hierarchy,
187 .irq_compose_msi_msg = irq_msi_compose_msg,
188 .irq_write_msi_msg = dmar_msi_write_msg,
189 .flags = IRQCHIP_SKIP_SET_WAKE,
190 };
191
dmar_msi_get_hwirq(struct msi_domain_info * info,msi_alloc_info_t * arg)192 static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info,
193 msi_alloc_info_t *arg)
194 {
195 return arg->dmar_id;
196 }
197
dmar_msi_init(struct irq_domain * domain,struct msi_domain_info * info,unsigned int virq,irq_hw_number_t hwirq,msi_alloc_info_t * arg)198 static int dmar_msi_init(struct irq_domain *domain,
199 struct msi_domain_info *info, unsigned int virq,
200 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
201 {
202 irq_domain_set_info(domain, virq, arg->dmar_id, info->chip, NULL,
203 handle_edge_irq, arg->dmar_data, "edge");
204
205 return 0;
206 }
207
208 static struct msi_domain_ops dmar_msi_domain_ops = {
209 .get_hwirq = dmar_msi_get_hwirq,
210 .msi_init = dmar_msi_init,
211 };
212
213 static struct msi_domain_info dmar_msi_domain_info = {
214 .ops = &dmar_msi_domain_ops,
215 .chip = &dmar_msi_controller,
216 };
217
dmar_get_irq_domain(void)218 static struct irq_domain *dmar_get_irq_domain(void)
219 {
220 static struct irq_domain *dmar_domain;
221 static DEFINE_MUTEX(dmar_lock);
222
223 mutex_lock(&dmar_lock);
224 if (dmar_domain == NULL)
225 dmar_domain = msi_create_irq_domain(NULL, &dmar_msi_domain_info,
226 x86_vector_domain);
227 mutex_unlock(&dmar_lock);
228
229 return dmar_domain;
230 }
231
dmar_alloc_hwirq(int id,int node,void * arg)232 int dmar_alloc_hwirq(int id, int node, void *arg)
233 {
234 struct irq_domain *domain = dmar_get_irq_domain();
235 struct irq_alloc_info info;
236
237 if (!domain)
238 return -1;
239
240 init_irq_alloc_info(&info, NULL);
241 info.type = X86_IRQ_ALLOC_TYPE_DMAR;
242 info.dmar_id = id;
243 info.dmar_data = arg;
244
245 return irq_domain_alloc_irqs(domain, 1, node, &info);
246 }
247
dmar_free_hwirq(int irq)248 void dmar_free_hwirq(int irq)
249 {
250 irq_domain_free_irqs(irq, 1);
251 }
252 #endif
253
254 /*
255 * MSI message composition
256 */
257 #ifdef CONFIG_HPET_TIMER
hpet_dev_id(struct irq_domain * domain)258 static inline int hpet_dev_id(struct irq_domain *domain)
259 {
260 struct msi_domain_info *info = msi_get_domain_info(domain);
261
262 return (int)(long)info->data;
263 }
264
hpet_msi_write_msg(struct irq_data * data,struct msi_msg * msg)265 static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
266 {
267 hpet_msi_write(irq_data_get_irq_handler_data(data), msg);
268 }
269
270 static struct irq_chip hpet_msi_controller = {
271 .name = "HPET-MSI",
272 .irq_unmask = hpet_msi_unmask,
273 .irq_mask = hpet_msi_mask,
274 .irq_ack = irq_chip_ack_parent,
275 .irq_set_affinity = msi_domain_set_affinity,
276 .irq_retrigger = irq_chip_retrigger_hierarchy,
277 .irq_compose_msi_msg = irq_msi_compose_msg,
278 .irq_write_msi_msg = hpet_msi_write_msg,
279 .flags = IRQCHIP_SKIP_SET_WAKE,
280 };
281
hpet_msi_get_hwirq(struct msi_domain_info * info,msi_alloc_info_t * arg)282 static irq_hw_number_t hpet_msi_get_hwirq(struct msi_domain_info *info,
283 msi_alloc_info_t *arg)
284 {
285 return arg->hpet_index;
286 }
287
hpet_msi_init(struct irq_domain * domain,struct msi_domain_info * info,unsigned int virq,irq_hw_number_t hwirq,msi_alloc_info_t * arg)288 static int hpet_msi_init(struct irq_domain *domain,
289 struct msi_domain_info *info, unsigned int virq,
290 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
291 {
292 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
293 irq_domain_set_info(domain, virq, arg->hpet_index, info->chip, NULL,
294 handle_edge_irq, arg->hpet_data, "edge");
295
296 return 0;
297 }
298
hpet_msi_free(struct irq_domain * domain,struct msi_domain_info * info,unsigned int virq)299 static void hpet_msi_free(struct irq_domain *domain,
300 struct msi_domain_info *info, unsigned int virq)
301 {
302 irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
303 }
304
305 static struct msi_domain_ops hpet_msi_domain_ops = {
306 .get_hwirq = hpet_msi_get_hwirq,
307 .msi_init = hpet_msi_init,
308 .msi_free = hpet_msi_free,
309 };
310
311 static struct msi_domain_info hpet_msi_domain_info = {
312 .ops = &hpet_msi_domain_ops,
313 .chip = &hpet_msi_controller,
314 };
315
hpet_create_irq_domain(int hpet_id)316 struct irq_domain *hpet_create_irq_domain(int hpet_id)
317 {
318 struct irq_domain *parent;
319 struct irq_alloc_info info;
320 struct msi_domain_info *domain_info;
321
322 if (x86_vector_domain == NULL)
323 return NULL;
324
325 domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
326 if (!domain_info)
327 return NULL;
328
329 *domain_info = hpet_msi_domain_info;
330 domain_info->data = (void *)(long)hpet_id;
331
332 init_irq_alloc_info(&info, NULL);
333 info.type = X86_IRQ_ALLOC_TYPE_HPET;
334 info.hpet_id = hpet_id;
335 parent = irq_remapping_get_ir_irq_domain(&info);
336 if (parent == NULL)
337 parent = x86_vector_domain;
338 else
339 hpet_msi_controller.name = "IR-HPET-MSI";
340
341 return msi_create_irq_domain(NULL, domain_info, parent);
342 }
343
hpet_assign_irq(struct irq_domain * domain,struct hpet_dev * dev,int dev_num)344 int hpet_assign_irq(struct irq_domain *domain, struct hpet_dev *dev,
345 int dev_num)
346 {
347 struct irq_alloc_info info;
348
349 init_irq_alloc_info(&info, NULL);
350 info.type = X86_IRQ_ALLOC_TYPE_HPET;
351 info.hpet_data = dev;
352 info.hpet_id = hpet_dev_id(domain);
353 info.hpet_index = dev_num;
354
355 return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info);
356 }
357 #endif
358