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1 #ifndef _ASM_POWERPC_MPIC_H
2 #define _ASM_POWERPC_MPIC_H
3 #ifdef __KERNEL__
4 
5 #include <linux/irq.h>
6 #include <asm/dcr.h>
7 #include <asm/msi_bitmap.h>
8 
9 /*
10  * Global registers
11  */
12 
13 #define MPIC_GREG_BASE			0x01000
14 
15 #define MPIC_GREG_FEATURE_0		0x00000
16 #define		MPIC_GREG_FEATURE_LAST_SRC_MASK		0x07ff0000
17 #define		MPIC_GREG_FEATURE_LAST_SRC_SHIFT	16
18 #define		MPIC_GREG_FEATURE_LAST_CPU_MASK		0x00001f00
19 #define		MPIC_GREG_FEATURE_LAST_CPU_SHIFT	8
20 #define		MPIC_GREG_FEATURE_VERSION_MASK		0xff
21 #define MPIC_GREG_FEATURE_1		0x00010
22 #define MPIC_GREG_GLOBAL_CONF_0		0x00020
23 #define		MPIC_GREG_GCONF_RESET			0x80000000
24 /* On the FSL mpic implementations the Mode field is expand to be
25  * 2 bits wide:
26  *	0b00 = pass through (interrupts routed to IRQ0)
27  *	0b01 = Mixed mode
28  *	0b10 = reserved
29  *	0b11 = External proxy / coreint
30  */
31 #define		MPIC_GREG_GCONF_COREINT			0x60000000
32 #define		MPIC_GREG_GCONF_8259_PTHROU_DIS		0x20000000
33 #define		MPIC_GREG_GCONF_NO_BIAS			0x10000000
34 #define		MPIC_GREG_GCONF_BASE_MASK		0x000fffff
35 #define		MPIC_GREG_GCONF_MCK			0x08000000
36 #define MPIC_GREG_GLOBAL_CONF_1		0x00030
37 #define MPIC_GREG_VENDOR_0		0x00040
38 #define MPIC_GREG_VENDOR_1		0x00050
39 #define MPIC_GREG_VENDOR_2		0x00060
40 #define MPIC_GREG_VENDOR_3		0x00070
41 #define MPIC_GREG_VENDOR_ID		0x00080
42 #define 	MPIC_GREG_VENDOR_ID_STEPPING_MASK	0x00ff0000
43 #define 	MPIC_GREG_VENDOR_ID_STEPPING_SHIFT	16
44 #define 	MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK	0x0000ff00
45 #define 	MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT	8
46 #define 	MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK	0x000000ff
47 #define MPIC_GREG_PROCESSOR_INIT	0x00090
48 #define MPIC_GREG_IPI_VECTOR_PRI_0	0x000a0
49 #define MPIC_GREG_IPI_VECTOR_PRI_1	0x000b0
50 #define MPIC_GREG_IPI_VECTOR_PRI_2	0x000c0
51 #define MPIC_GREG_IPI_VECTOR_PRI_3	0x000d0
52 #define MPIC_GREG_IPI_STRIDE		0x10
53 #define MPIC_GREG_SPURIOUS		0x000e0
54 #define MPIC_GREG_TIMER_FREQ		0x000f0
55 
56 /*
57  *
58  * Timer registers
59  */
60 #define MPIC_TIMER_BASE			0x01100
61 #define MPIC_TIMER_STRIDE		0x40
62 #define MPIC_TIMER_GROUP_STRIDE		0x1000
63 
64 #define MPIC_TIMER_CURRENT_CNT		0x00000
65 #define MPIC_TIMER_BASE_CNT		0x00010
66 #define MPIC_TIMER_VECTOR_PRI		0x00020
67 #define MPIC_TIMER_DESTINATION		0x00030
68 
69 /*
70  * Per-Processor registers
71  */
72 
73 #define MPIC_CPU_THISBASE		0x00000
74 #define MPIC_CPU_BASE			0x20000
75 #define MPIC_CPU_STRIDE			0x01000
76 
77 #define MPIC_CPU_IPI_DISPATCH_0		0x00040
78 #define MPIC_CPU_IPI_DISPATCH_1		0x00050
79 #define MPIC_CPU_IPI_DISPATCH_2		0x00060
80 #define MPIC_CPU_IPI_DISPATCH_3		0x00070
81 #define MPIC_CPU_IPI_DISPATCH_STRIDE	0x00010
82 #define MPIC_CPU_CURRENT_TASK_PRI	0x00080
83 #define 	MPIC_CPU_TASKPRI_MASK			0x0000000f
84 #define MPIC_CPU_WHOAMI			0x00090
85 #define 	MPIC_CPU_WHOAMI_MASK			0x0000001f
86 #define MPIC_CPU_INTACK			0x000a0
87 #define MPIC_CPU_EOI			0x000b0
88 #define MPIC_CPU_MCACK			0x000c0
89 
90 /*
91  * Per-source registers
92  */
93 
94 #define MPIC_IRQ_BASE			0x10000
95 #define MPIC_IRQ_STRIDE			0x00020
96 #define MPIC_IRQ_VECTOR_PRI		0x00000
97 #define 	MPIC_VECPRI_MASK			0x80000000
98 #define 	MPIC_VECPRI_ACTIVITY			0x40000000	/* Read Only */
99 #define 	MPIC_VECPRI_PRIORITY_MASK		0x000f0000
100 #define 	MPIC_VECPRI_PRIORITY_SHIFT		16
101 #define 	MPIC_VECPRI_VECTOR_MASK			0x000007ff
102 #define 	MPIC_VECPRI_POLARITY_POSITIVE		0x00800000
103 #define 	MPIC_VECPRI_POLARITY_NEGATIVE		0x00000000
104 #define 	MPIC_VECPRI_POLARITY_MASK		0x00800000
105 #define 	MPIC_VECPRI_SENSE_LEVEL			0x00400000
106 #define 	MPIC_VECPRI_SENSE_EDGE			0x00000000
107 #define 	MPIC_VECPRI_SENSE_MASK			0x00400000
108 #define MPIC_IRQ_DESTINATION		0x00010
109 
110 #define MPIC_FSL_BRR1			0x00000
111 #define 	MPIC_FSL_BRR1_VER			0x0000ffff
112 
113 #define MPIC_MAX_IRQ_SOURCES	2048
114 #define MPIC_MAX_CPUS		32
115 #define MPIC_MAX_ISU		32
116 
117 #define MPIC_MAX_ERR      32
118 #define MPIC_FSL_ERR_INT  16
119 
120 /*
121  * Tsi108 implementation of MPIC has many differences from the original one
122  */
123 
124 /*
125  * Global registers
126  */
127 
128 #define TSI108_GREG_BASE		0x00000
129 #define TSI108_GREG_FEATURE_0		0x00000
130 #define TSI108_GREG_GLOBAL_CONF_0	0x00004
131 #define TSI108_GREG_VENDOR_ID		0x0000c
132 #define TSI108_GREG_IPI_VECTOR_PRI_0	0x00204		/* Doorbell 0 */
133 #define TSI108_GREG_IPI_STRIDE		0x0c
134 #define TSI108_GREG_SPURIOUS		0x00010
135 #define TSI108_GREG_TIMER_FREQ		0x00014
136 
137 /*
138  * Timer registers
139  */
140 #define TSI108_TIMER_BASE		0x0030
141 #define TSI108_TIMER_STRIDE		0x10
142 #define TSI108_TIMER_CURRENT_CNT	0x00000
143 #define TSI108_TIMER_BASE_CNT		0x00004
144 #define TSI108_TIMER_VECTOR_PRI		0x00008
145 #define TSI108_TIMER_DESTINATION	0x0000c
146 
147 /*
148  * Per-Processor registers
149  */
150 #define TSI108_CPU_BASE			0x00300
151 #define TSI108_CPU_STRIDE		0x00040
152 #define TSI108_CPU_IPI_DISPATCH_0	0x00200
153 #define TSI108_CPU_IPI_DISPATCH_STRIDE	0x00000
154 #define TSI108_CPU_CURRENT_TASK_PRI	0x00000
155 #define TSI108_CPU_WHOAMI		0xffffffff
156 #define TSI108_CPU_INTACK		0x00004
157 #define TSI108_CPU_EOI			0x00008
158 #define TSI108_CPU_MCACK		0x00004 /* Doesn't really exist here */
159 
160 /*
161  * Per-source registers
162  */
163 #define TSI108_IRQ_BASE			0x00100
164 #define TSI108_IRQ_STRIDE		0x00008
165 #define TSI108_IRQ_VECTOR_PRI		0x00000
166 #define TSI108_VECPRI_VECTOR_MASK	0x000000ff
167 #define TSI108_VECPRI_POLARITY_POSITIVE	0x01000000
168 #define TSI108_VECPRI_POLARITY_NEGATIVE	0x00000000
169 #define TSI108_VECPRI_SENSE_LEVEL	0x02000000
170 #define TSI108_VECPRI_SENSE_EDGE	0x00000000
171 #define TSI108_VECPRI_POLARITY_MASK	0x01000000
172 #define TSI108_VECPRI_SENSE_MASK	0x02000000
173 #define TSI108_IRQ_DESTINATION		0x00004
174 
175 /* weird mpic register indices and mask bits in the HW info array */
176 enum {
177 	MPIC_IDX_GREG_BASE = 0,
178 	MPIC_IDX_GREG_FEATURE_0,
179 	MPIC_IDX_GREG_GLOBAL_CONF_0,
180 	MPIC_IDX_GREG_VENDOR_ID,
181 	MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
182 	MPIC_IDX_GREG_IPI_STRIDE,
183 	MPIC_IDX_GREG_SPURIOUS,
184 	MPIC_IDX_GREG_TIMER_FREQ,
185 
186 	MPIC_IDX_TIMER_BASE,
187 	MPIC_IDX_TIMER_STRIDE,
188 	MPIC_IDX_TIMER_CURRENT_CNT,
189 	MPIC_IDX_TIMER_BASE_CNT,
190 	MPIC_IDX_TIMER_VECTOR_PRI,
191 	MPIC_IDX_TIMER_DESTINATION,
192 
193 	MPIC_IDX_CPU_BASE,
194 	MPIC_IDX_CPU_STRIDE,
195 	MPIC_IDX_CPU_IPI_DISPATCH_0,
196 	MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
197 	MPIC_IDX_CPU_CURRENT_TASK_PRI,
198 	MPIC_IDX_CPU_WHOAMI,
199 	MPIC_IDX_CPU_INTACK,
200 	MPIC_IDX_CPU_EOI,
201 	MPIC_IDX_CPU_MCACK,
202 
203 	MPIC_IDX_IRQ_BASE,
204 	MPIC_IDX_IRQ_STRIDE,
205 	MPIC_IDX_IRQ_VECTOR_PRI,
206 
207 	MPIC_IDX_VECPRI_VECTOR_MASK,
208 	MPIC_IDX_VECPRI_POLARITY_POSITIVE,
209 	MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
210 	MPIC_IDX_VECPRI_SENSE_LEVEL,
211 	MPIC_IDX_VECPRI_SENSE_EDGE,
212 	MPIC_IDX_VECPRI_POLARITY_MASK,
213 	MPIC_IDX_VECPRI_SENSE_MASK,
214 	MPIC_IDX_IRQ_DESTINATION,
215 	MPIC_IDX_END
216 };
217 
218 
219 #ifdef CONFIG_MPIC_U3_HT_IRQS
220 /* Fixup table entry */
221 struct mpic_irq_fixup
222 {
223 	u8 __iomem	*base;
224 	u8 __iomem	*applebase;
225 	u32		data;
226 	unsigned int	index;
227 };
228 #endif /* CONFIG_MPIC_U3_HT_IRQS */
229 
230 
231 enum mpic_reg_type {
232 	mpic_access_mmio_le,
233 	mpic_access_mmio_be,
234 #ifdef CONFIG_PPC_DCR
235 	mpic_access_dcr
236 #endif
237 };
238 
239 struct mpic_reg_bank {
240 	u32 __iomem	*base;
241 #ifdef CONFIG_PPC_DCR
242 	dcr_host_t	dhost;
243 #endif /* CONFIG_PPC_DCR */
244 };
245 
246 struct mpic_irq_save {
247 	u32		vecprio,
248 			dest;
249 #ifdef CONFIG_MPIC_U3_HT_IRQS
250 	u32		fixup_data;
251 #endif
252 };
253 
254 /* The instance data of a given MPIC */
255 struct mpic
256 {
257 	/* The OpenFirmware dt node for this MPIC */
258 	struct device_node *node;
259 
260 	/* The remapper for this MPIC */
261 	struct irq_domain	*irqhost;
262 
263 	/* The "linux" controller struct */
264 	struct irq_chip		hc_irq;
265 #ifdef CONFIG_MPIC_U3_HT_IRQS
266 	struct irq_chip		hc_ht_irq;
267 #endif
268 #ifdef CONFIG_SMP
269 	struct irq_chip		hc_ipi;
270 #endif
271 	struct irq_chip		hc_tm;
272 	struct irq_chip		hc_err;
273 	const char		*name;
274 	/* Flags */
275 	unsigned int		flags;
276 	/* How many irq sources in a given ISU */
277 	unsigned int		isu_size;
278 	unsigned int		isu_shift;
279 	unsigned int		isu_mask;
280 	/* Number of sources */
281 	unsigned int		num_sources;
282 
283 	/* vector numbers used for internal sources (ipi/timers) */
284 	unsigned int		ipi_vecs[4];
285 	unsigned int		timer_vecs[8];
286 	/* vector numbers used for FSL MPIC error interrupts */
287 	unsigned int		err_int_vecs[MPIC_MAX_ERR];
288 
289 	/* Spurious vector to program into unused sources */
290 	unsigned int		spurious_vec;
291 
292 #ifdef CONFIG_MPIC_U3_HT_IRQS
293 	/* The fixup table */
294 	struct mpic_irq_fixup	*fixups;
295 	raw_spinlock_t	fixup_lock;
296 #endif
297 
298 	/* Register access method */
299 	enum mpic_reg_type	reg_type;
300 
301 	/* The physical base address of the MPIC */
302 	phys_addr_t paddr;
303 
304 	/* The various ioremap'ed bases */
305 	struct mpic_reg_bank	thiscpuregs;
306 	struct mpic_reg_bank	gregs;
307 	struct mpic_reg_bank	tmregs;
308 	struct mpic_reg_bank	cpuregs[MPIC_MAX_CPUS];
309 	struct mpic_reg_bank	isus[MPIC_MAX_ISU];
310 
311 	/* ioremap'ed base for error interrupt registers */
312 	u32 __iomem	*err_regs;
313 
314 	/* Protected sources */
315 	unsigned long		*protected;
316 
317 #ifdef CONFIG_MPIC_WEIRD
318 	/* Pointer to HW info array */
319 	u32			*hw_set;
320 #endif
321 
322 #ifdef CONFIG_PCI_MSI
323 	struct msi_bitmap	msi_bitmap;
324 #endif
325 
326 #ifdef CONFIG_MPIC_BROKEN_REGREAD
327 	u32			isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES];
328 #endif
329 
330 	/* link */
331 	struct mpic		*next;
332 
333 #ifdef CONFIG_PM
334 	struct mpic_irq_save	*save_data;
335 #endif
336 };
337 
338 extern struct bus_type mpic_subsys;
339 
340 /*
341  * MPIC flags (passed to mpic_alloc)
342  *
343  * The top 4 bits contain an MPIC bhw id that is used to index the
344  * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
345  * Note setting any ID (leaving those bits to 0) means standard MPIC
346  */
347 
348 /*
349  * This is a secondary ("chained") controller; it only uses the CPU0
350  * registers.  Primary controllers have IPIs and affinity control.
351  */
352 #define MPIC_SECONDARY			0x00000001
353 
354 /* Set this for a big-endian MPIC */
355 #define MPIC_BIG_ENDIAN			0x00000002
356 /* Broken U3 MPIC */
357 #define MPIC_U3_HT_IRQS			0x00000004
358 /* Broken IPI registers (autodetected) */
359 #define MPIC_BROKEN_IPI			0x00000008
360 /* Spurious vector requires EOI */
361 #define MPIC_SPV_EOI			0x00000020
362 /* No passthrough disable */
363 #define MPIC_NO_PTHROU_DIS		0x00000040
364 /* DCR based MPIC */
365 #define MPIC_USES_DCR			0x00000080
366 /* MPIC has 11-bit vector fields (or larger) */
367 #define MPIC_LARGE_VECTORS		0x00000100
368 /* Enable delivery of prio 15 interrupts as MCK instead of EE */
369 #define MPIC_ENABLE_MCK			0x00000200
370 /* Disable bias among target selection, spread interrupts evenly */
371 #define MPIC_NO_BIAS			0x00000400
372 /* Destination only supports a single CPU at a time */
373 #define MPIC_SINGLE_DEST_CPU		0x00001000
374 /* Enable CoreInt delivery of interrupts */
375 #define MPIC_ENABLE_COREINT		0x00002000
376 /* Do not reset the MPIC during initialization */
377 #define MPIC_NO_RESET			0x00004000
378 /* Freescale MPIC (compatible includes "fsl,mpic") */
379 #define MPIC_FSL			0x00008000
380 /* Freescale MPIC supports EIMR (error interrupt mask register).
381  * This flag is set for MPIC version >= 4.1 (version determined
382  * from the BRR1 register).
383 */
384 #define MPIC_FSL_HAS_EIMR		0x00010000
385 
386 /* MPIC HW modification ID */
387 #define MPIC_REGSET_MASK		0xf0000000
388 #define MPIC_REGSET(val)		(((val) & 0xf ) << 28)
389 #define MPIC_GET_REGSET(flags)		(((flags) >> 28) & 0xf)
390 
391 #define	MPIC_REGSET_STANDARD		MPIC_REGSET(0)	/* Original MPIC */
392 #define	MPIC_REGSET_TSI108		MPIC_REGSET(1)	/* Tsi108/109 PIC */
393 
394 /* Get the version of primary MPIC */
395 #ifdef CONFIG_MPIC
396 extern u32 fsl_mpic_primary_get_version(void);
397 #else
fsl_mpic_primary_get_version(void)398 static inline u32 fsl_mpic_primary_get_version(void)
399 {
400 	return 0;
401 }
402 #endif
403 
404 /* Allocate the controller structure and setup the linux irq descs
405  * for the range if interrupts passed in. No HW initialization is
406  * actually performed.
407  *
408  * @phys_addr:	physial base address of the MPIC
409  * @flags:	flags, see constants above
410  * @isu_size:	number of interrupts in an ISU. Use 0 to use a
411  *              standard ISU-less setup (aka powermac)
412  * @irq_offset: first irq number to assign to this mpic
413  * @irq_count:  number of irqs to use with this mpic IRQ sources. Pass 0
414  *	        to match the number of sources
415  * @ipi_offset: first irq number to assign to this mpic IPI sources,
416  *		used only on primary mpic
417  * @senses:	array of sense values
418  * @senses_num: number of entries in the array
419  *
420  * Note about the sense array. If none is passed, all interrupts are
421  * setup to be level negative unless MPIC_U3_HT_IRQS is set in which
422  * case they are edge positive (and the array is ignored anyway).
423  * The values in the array start at the first source of the MPIC,
424  * that is senses[0] correspond to linux irq "irq_offset".
425  */
426 extern struct mpic *mpic_alloc(struct device_node *node,
427 			       phys_addr_t phys_addr,
428 			       unsigned int flags,
429 			       unsigned int isu_size,
430 			       unsigned int irq_count,
431 			       const char *name);
432 
433 /* Assign ISUs, to call before mpic_init()
434  *
435  * @mpic:	controller structure as returned by mpic_alloc()
436  * @isu_num:	ISU number
437  * @phys_addr:	physical address of the ISU
438  */
439 extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
440 			    phys_addr_t phys_addr);
441 
442 
443 /* Initialize the controller. After this has been called, none of the above
444  * should be called again for this mpic
445  */
446 extern void mpic_init(struct mpic *mpic);
447 
448 /*
449  * All of the following functions must only be used after the
450  * ISUs have been assigned and the controller fully initialized
451  * with mpic_init()
452  */
453 
454 
455 /* Change the priority of an interrupt. Default is 8 for irqs and
456  * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
457  * IPI number is then the offset'ed (linux irq number mapped to the IPI)
458  */
459 extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
460 
461 /* Setup a non-boot CPU */
462 extern void mpic_setup_this_cpu(void);
463 
464 /* Clean up for kexec (or cpu offline or ...) */
465 extern void mpic_teardown_this_cpu(int secondary);
466 
467 /* Get the current cpu priority for this cpu (0..15) */
468 extern int mpic_cpu_get_priority(void);
469 
470 /* Set the current cpu priority for this cpu */
471 extern void mpic_cpu_set_priority(int prio);
472 
473 /* Request IPIs on primary mpic */
474 extern void mpic_request_ipis(void);
475 
476 /* Send a message (IPI) to a given target (cpu number or MSG_*) */
477 void smp_mpic_message_pass(int target, int msg);
478 
479 /* Unmask a specific virq */
480 extern void mpic_unmask_irq(struct irq_data *d);
481 /* Mask a specific virq */
482 extern void mpic_mask_irq(struct irq_data *d);
483 /* EOI a specific virq */
484 extern void mpic_end_irq(struct irq_data *d);
485 
486 /* Fetch interrupt from a given mpic */
487 extern unsigned int mpic_get_one_irq(struct mpic *mpic);
488 /* This one gets from the primary mpic */
489 extern unsigned int mpic_get_irq(void);
490 /* This one gets from the primary mpic via CoreInt*/
491 extern unsigned int mpic_get_coreint_irq(void);
492 /* Fetch Machine Check interrupt from primary mpic */
493 extern unsigned int mpic_get_mcirq(void);
494 
495 #endif /* __KERNEL__ */
496 #endif	/* _ASM_POWERPC_MPIC_H */
497