1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include "i40e_prototype.h"
28
29 /**
30 * i40e_init_nvm_ops - Initialize NVM function pointers
31 * @hw: pointer to the HW structure
32 *
33 * Setup the function pointers and the NVM info structure. Should be called
34 * once per NVM initialization, e.g. inside the i40e_init_shared_code().
35 * Please notice that the NVM term is used here (& in all methods covered
36 * in this file) as an equivalent of the FLASH part mapped into the SR.
37 * We are accessing FLASH always thru the Shadow RAM.
38 **/
i40e_init_nvm(struct i40e_hw * hw)39 i40e_status i40e_init_nvm(struct i40e_hw *hw)
40 {
41 struct i40e_nvm_info *nvm = &hw->nvm;
42 i40e_status ret_code = 0;
43 u32 fla, gens;
44 u8 sr_size;
45
46 /* The SR size is stored regardless of the nvm programming mode
47 * as the blank mode may be used in the factory line.
48 */
49 gens = rd32(hw, I40E_GLNVM_GENS);
50 sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
51 I40E_GLNVM_GENS_SR_SIZE_SHIFT);
52 /* Switching to words (sr_size contains power of 2KB) */
53 nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB;
54
55 /* Check if we are in the normal or blank NVM programming mode */
56 fla = rd32(hw, I40E_GLNVM_FLA);
57 if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */
58 /* Max NVM timeout */
59 nvm->timeout = I40E_MAX_NVM_TIMEOUT;
60 nvm->blank_nvm_mode = false;
61 } else { /* Blank programming mode */
62 nvm->blank_nvm_mode = true;
63 ret_code = I40E_ERR_NVM_BLANK_MODE;
64 i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n");
65 }
66
67 return ret_code;
68 }
69
70 /**
71 * i40e_acquire_nvm - Generic request for acquiring the NVM ownership
72 * @hw: pointer to the HW structure
73 * @access: NVM access type (read or write)
74 *
75 * This function will request NVM ownership for reading
76 * via the proper Admin Command.
77 **/
i40e_acquire_nvm(struct i40e_hw * hw,enum i40e_aq_resource_access_type access)78 i40e_status i40e_acquire_nvm(struct i40e_hw *hw,
79 enum i40e_aq_resource_access_type access)
80 {
81 i40e_status ret_code = 0;
82 u64 gtime, timeout;
83 u64 time_left = 0;
84
85 if (hw->nvm.blank_nvm_mode)
86 goto i40e_i40e_acquire_nvm_exit;
87
88 ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,
89 0, &time_left, NULL);
90 /* Reading the Global Device Timer */
91 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
92
93 /* Store the timeout */
94 hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime;
95
96 if (ret_code)
97 i40e_debug(hw, I40E_DEBUG_NVM,
98 "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n",
99 access, time_left, ret_code, hw->aq.asq_last_status);
100
101 if (ret_code && time_left) {
102 /* Poll until the current NVM owner timeouts */
103 timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime;
104 while ((gtime < timeout) && time_left) {
105 usleep_range(10000, 20000);
106 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
107 ret_code = i40e_aq_request_resource(hw,
108 I40E_NVM_RESOURCE_ID,
109 access, 0, &time_left,
110 NULL);
111 if (!ret_code) {
112 hw->nvm.hw_semaphore_timeout =
113 I40E_MS_TO_GTIME(time_left) + gtime;
114 break;
115 }
116 }
117 if (ret_code) {
118 hw->nvm.hw_semaphore_timeout = 0;
119 i40e_debug(hw, I40E_DEBUG_NVM,
120 "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n",
121 time_left, ret_code, hw->aq.asq_last_status);
122 }
123 }
124
125 i40e_i40e_acquire_nvm_exit:
126 return ret_code;
127 }
128
129 /**
130 * i40e_release_nvm - Generic request for releasing the NVM ownership
131 * @hw: pointer to the HW structure
132 *
133 * This function will release NVM resource via the proper Admin Command.
134 **/
i40e_release_nvm(struct i40e_hw * hw)135 void i40e_release_nvm(struct i40e_hw *hw)
136 {
137 if (!hw->nvm.blank_nvm_mode)
138 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
139 }
140
141 /**
142 * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit
143 * @hw: pointer to the HW structure
144 *
145 * Polls the SRCTL Shadow RAM register done bit.
146 **/
i40e_poll_sr_srctl_done_bit(struct i40e_hw * hw)147 static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
148 {
149 i40e_status ret_code = I40E_ERR_TIMEOUT;
150 u32 srctl, wait_cnt;
151
152 /* Poll the I40E_GLNVM_SRCTL until the done bit is set */
153 for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {
154 srctl = rd32(hw, I40E_GLNVM_SRCTL);
155 if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {
156 ret_code = 0;
157 break;
158 }
159 udelay(5);
160 }
161 if (ret_code == I40E_ERR_TIMEOUT)
162 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set");
163 return ret_code;
164 }
165
166 /**
167 * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register
168 * @hw: pointer to the HW structure
169 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
170 * @data: word read from the Shadow RAM
171 *
172 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
173 **/
i40e_read_nvm_word_srctl(struct i40e_hw * hw,u16 offset,u16 * data)174 static i40e_status i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
175 u16 *data)
176 {
177 i40e_status ret_code = I40E_ERR_TIMEOUT;
178 u32 sr_reg;
179
180 if (offset >= hw->nvm.sr_size) {
181 i40e_debug(hw, I40E_DEBUG_NVM,
182 "NVM read error: offset %d beyond Shadow RAM limit %d\n",
183 offset, hw->nvm.sr_size);
184 ret_code = I40E_ERR_PARAM;
185 goto read_nvm_exit;
186 }
187
188 /* Poll the done bit first */
189 ret_code = i40e_poll_sr_srctl_done_bit(hw);
190 if (!ret_code) {
191 /* Write the address and start reading */
192 sr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
193 BIT(I40E_GLNVM_SRCTL_START_SHIFT);
194 wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
195
196 /* Poll I40E_GLNVM_SRCTL until the done bit is set */
197 ret_code = i40e_poll_sr_srctl_done_bit(hw);
198 if (!ret_code) {
199 sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
200 *data = (u16)((sr_reg &
201 I40E_GLNVM_SRDATA_RDDATA_MASK)
202 >> I40E_GLNVM_SRDATA_RDDATA_SHIFT);
203 }
204 }
205 if (ret_code)
206 i40e_debug(hw, I40E_DEBUG_NVM,
207 "NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
208 offset);
209
210 read_nvm_exit:
211 return ret_code;
212 }
213
214 /**
215 * i40e_read_nvm_aq - Read Shadow RAM.
216 * @hw: pointer to the HW structure.
217 * @module_pointer: module pointer location in words from the NVM beginning
218 * @offset: offset in words from module start
219 * @words: number of words to write
220 * @data: buffer with words to write to the Shadow RAM
221 * @last_command: tells the AdminQ that this is the last command
222 *
223 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
224 **/
i40e_read_nvm_aq(struct i40e_hw * hw,u8 module_pointer,u32 offset,u16 words,void * data,bool last_command)225 static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
226 u32 offset, u16 words, void *data,
227 bool last_command)
228 {
229 i40e_status ret_code = I40E_ERR_NVM;
230 struct i40e_asq_cmd_details cmd_details;
231
232 memset(&cmd_details, 0, sizeof(cmd_details));
233
234 /* Here we are checking the SR limit only for the flat memory model.
235 * We cannot do it for the module-based model, as we did not acquire
236 * the NVM resource yet (we cannot get the module pointer value).
237 * Firmware will check the module-based model.
238 */
239 if ((offset + words) > hw->nvm.sr_size)
240 i40e_debug(hw, I40E_DEBUG_NVM,
241 "NVM write error: offset %d beyond Shadow RAM limit %d\n",
242 (offset + words), hw->nvm.sr_size);
243 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
244 /* We can write only up to 4KB (one sector), in one AQ write */
245 i40e_debug(hw, I40E_DEBUG_NVM,
246 "NVM write fail error: tried to write %d words, limit is %d.\n",
247 words, I40E_SR_SECTOR_SIZE_IN_WORDS);
248 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
249 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
250 /* A single write cannot spread over two sectors */
251 i40e_debug(hw, I40E_DEBUG_NVM,
252 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
253 offset, words);
254 else
255 ret_code = i40e_aq_read_nvm(hw, module_pointer,
256 2 * offset, /*bytes*/
257 2 * words, /*bytes*/
258 data, last_command, &cmd_details);
259
260 return ret_code;
261 }
262
263 /**
264 * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ
265 * @hw: pointer to the HW structure
266 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
267 * @data: word read from the Shadow RAM
268 *
269 * Reads one 16 bit word from the Shadow RAM using the AdminQ
270 **/
i40e_read_nvm_word_aq(struct i40e_hw * hw,u16 offset,u16 * data)271 static i40e_status i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
272 u16 *data)
273 {
274 i40e_status ret_code = I40E_ERR_TIMEOUT;
275
276 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true);
277 *data = le16_to_cpu(*(__le16 *)data);
278
279 return ret_code;
280 }
281
282 /**
283 * __i40e_read_nvm_word - Reads nvm word, assumes called does the locking
284 * @hw: pointer to the HW structure
285 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
286 * @data: word read from the Shadow RAM
287 *
288 * Reads one 16 bit word from the Shadow RAM.
289 *
290 * Do not use this function except in cases where the nvm lock is already
291 * taken via i40e_acquire_nvm().
292 **/
__i40e_read_nvm_word(struct i40e_hw * hw,u16 offset,u16 * data)293 static i40e_status __i40e_read_nvm_word(struct i40e_hw *hw,
294 u16 offset, u16 *data)
295 {
296 i40e_status ret_code = 0;
297
298 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
299 ret_code = i40e_read_nvm_word_aq(hw, offset, data);
300 else
301 ret_code = i40e_read_nvm_word_srctl(hw, offset, data);
302 return ret_code;
303 }
304
305 /**
306 * i40e_read_nvm_word - Reads nvm word and acquire lock if necessary
307 * @hw: pointer to the HW structure
308 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
309 * @data: word read from the Shadow RAM
310 *
311 * Reads one 16 bit word from the Shadow RAM.
312 **/
i40e_read_nvm_word(struct i40e_hw * hw,u16 offset,u16 * data)313 i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
314 u16 *data)
315 {
316 i40e_status ret_code = 0;
317
318 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
319 if (ret_code)
320 return ret_code;
321
322 ret_code = __i40e_read_nvm_word(hw, offset, data);
323
324 i40e_release_nvm(hw);
325
326 return ret_code;
327 }
328
329 /**
330 * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
331 * @hw: pointer to the HW structure
332 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
333 * @words: (in) number of words to read; (out) number of words actually read
334 * @data: words read from the Shadow RAM
335 *
336 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
337 * method. The buffer read is preceded by the NVM ownership take
338 * and followed by the release.
339 **/
i40e_read_nvm_buffer_srctl(struct i40e_hw * hw,u16 offset,u16 * words,u16 * data)340 static i40e_status i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
341 u16 *words, u16 *data)
342 {
343 i40e_status ret_code = 0;
344 u16 index, word;
345
346 /* Loop thru the selected region */
347 for (word = 0; word < *words; word++) {
348 index = offset + word;
349 ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]);
350 if (ret_code)
351 break;
352 }
353
354 /* Update the number of words read from the Shadow RAM */
355 *words = word;
356
357 return ret_code;
358 }
359
360 /**
361 * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ
362 * @hw: pointer to the HW structure
363 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
364 * @words: (in) number of words to read; (out) number of words actually read
365 * @data: words read from the Shadow RAM
366 *
367 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq()
368 * method. The buffer read is preceded by the NVM ownership take
369 * and followed by the release.
370 **/
i40e_read_nvm_buffer_aq(struct i40e_hw * hw,u16 offset,u16 * words,u16 * data)371 static i40e_status i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
372 u16 *words, u16 *data)
373 {
374 i40e_status ret_code;
375 u16 read_size = *words;
376 bool last_cmd = false;
377 u16 words_read = 0;
378 u16 i = 0;
379
380 do {
381 /* Calculate number of bytes we should read in this step.
382 * FVL AQ do not allow to read more than one page at a time or
383 * to cross page boundaries.
384 */
385 if (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)
386 read_size = min(*words,
387 (u16)(I40E_SR_SECTOR_SIZE_IN_WORDS -
388 (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)));
389 else
390 read_size = min((*words - words_read),
391 I40E_SR_SECTOR_SIZE_IN_WORDS);
392
393 /* Check if this is last command, if so set proper flag */
394 if ((words_read + read_size) >= *words)
395 last_cmd = true;
396
397 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size,
398 data + words_read, last_cmd);
399 if (ret_code)
400 goto read_nvm_buffer_aq_exit;
401
402 /* Increment counter for words already read and move offset to
403 * new read location
404 */
405 words_read += read_size;
406 offset += read_size;
407 } while (words_read < *words);
408
409 for (i = 0; i < *words; i++)
410 data[i] = le16_to_cpu(((__le16 *)data)[i]);
411
412 read_nvm_buffer_aq_exit:
413 *words = words_read;
414 return ret_code;
415 }
416
417 /**
418 * __i40e_read_nvm_buffer - Reads nvm buffer, caller must acquire lock
419 * @hw: pointer to the HW structure
420 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
421 * @words: (in) number of words to read; (out) number of words actually read
422 * @data: words read from the Shadow RAM
423 *
424 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
425 * method.
426 **/
__i40e_read_nvm_buffer(struct i40e_hw * hw,u16 offset,u16 * words,u16 * data)427 static i40e_status __i40e_read_nvm_buffer(struct i40e_hw *hw,
428 u16 offset, u16 *words,
429 u16 *data)
430 {
431 i40e_status ret_code = 0;
432
433 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
434 ret_code = i40e_read_nvm_buffer_aq(hw, offset, words, data);
435 else
436 ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data);
437 return ret_code;
438 }
439
440 /**
441 * i40e_write_nvm_aq - Writes Shadow RAM.
442 * @hw: pointer to the HW structure.
443 * @module_pointer: module pointer location in words from the NVM beginning
444 * @offset: offset in words from module start
445 * @words: number of words to write
446 * @data: buffer with words to write to the Shadow RAM
447 * @last_command: tells the AdminQ that this is the last command
448 *
449 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
450 **/
i40e_write_nvm_aq(struct i40e_hw * hw,u8 module_pointer,u32 offset,u16 words,void * data,bool last_command)451 static i40e_status i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
452 u32 offset, u16 words, void *data,
453 bool last_command)
454 {
455 i40e_status ret_code = I40E_ERR_NVM;
456 struct i40e_asq_cmd_details cmd_details;
457
458 memset(&cmd_details, 0, sizeof(cmd_details));
459 cmd_details.wb_desc = &hw->nvm_wb_desc;
460
461 /* Here we are checking the SR limit only for the flat memory model.
462 * We cannot do it for the module-based model, as we did not acquire
463 * the NVM resource yet (we cannot get the module pointer value).
464 * Firmware will check the module-based model.
465 */
466 if ((offset + words) > hw->nvm.sr_size)
467 i40e_debug(hw, I40E_DEBUG_NVM,
468 "NVM write error: offset %d beyond Shadow RAM limit %d\n",
469 (offset + words), hw->nvm.sr_size);
470 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
471 /* We can write only up to 4KB (one sector), in one AQ write */
472 i40e_debug(hw, I40E_DEBUG_NVM,
473 "NVM write fail error: tried to write %d words, limit is %d.\n",
474 words, I40E_SR_SECTOR_SIZE_IN_WORDS);
475 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
476 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
477 /* A single write cannot spread over two sectors */
478 i40e_debug(hw, I40E_DEBUG_NVM,
479 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
480 offset, words);
481 else
482 ret_code = i40e_aq_update_nvm(hw, module_pointer,
483 2 * offset, /*bytes*/
484 2 * words, /*bytes*/
485 data, last_command, &cmd_details);
486
487 return ret_code;
488 }
489
490 /**
491 * i40e_calc_nvm_checksum - Calculates and returns the checksum
492 * @hw: pointer to hardware structure
493 * @checksum: pointer to the checksum
494 *
495 * This function calculates SW Checksum that covers the whole 64kB shadow RAM
496 * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
497 * is customer specific and unknown. Therefore, this function skips all maximum
498 * possible size of VPD (1kB).
499 **/
i40e_calc_nvm_checksum(struct i40e_hw * hw,u16 * checksum)500 static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw,
501 u16 *checksum)
502 {
503 i40e_status ret_code;
504 struct i40e_virt_mem vmem;
505 u16 pcie_alt_module = 0;
506 u16 checksum_local = 0;
507 u16 vpd_module = 0;
508 u16 *data;
509 u16 i = 0;
510
511 ret_code = i40e_allocate_virt_mem(hw, &vmem,
512 I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16));
513 if (ret_code)
514 goto i40e_calc_nvm_checksum_exit;
515 data = (u16 *)vmem.va;
516
517 /* read pointer to VPD area */
518 ret_code = __i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module);
519 if (ret_code) {
520 ret_code = I40E_ERR_NVM_CHECKSUM;
521 goto i40e_calc_nvm_checksum_exit;
522 }
523
524 /* read pointer to PCIe Alt Auto-load module */
525 ret_code = __i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
526 &pcie_alt_module);
527 if (ret_code) {
528 ret_code = I40E_ERR_NVM_CHECKSUM;
529 goto i40e_calc_nvm_checksum_exit;
530 }
531
532 /* Calculate SW checksum that covers the whole 64kB shadow RAM
533 * except the VPD and PCIe ALT Auto-load modules
534 */
535 for (i = 0; i < hw->nvm.sr_size; i++) {
536 /* Read SR page */
537 if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) {
538 u16 words = I40E_SR_SECTOR_SIZE_IN_WORDS;
539
540 ret_code = __i40e_read_nvm_buffer(hw, i, &words, data);
541 if (ret_code) {
542 ret_code = I40E_ERR_NVM_CHECKSUM;
543 goto i40e_calc_nvm_checksum_exit;
544 }
545 }
546
547 /* Skip Checksum word */
548 if (i == I40E_SR_SW_CHECKSUM_WORD)
549 continue;
550 /* Skip VPD module (convert byte size to word count) */
551 if ((i >= (u32)vpd_module) &&
552 (i < ((u32)vpd_module +
553 (I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) {
554 continue;
555 }
556 /* Skip PCIe ALT module (convert byte size to word count) */
557 if ((i >= (u32)pcie_alt_module) &&
558 (i < ((u32)pcie_alt_module +
559 (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) {
560 continue;
561 }
562
563 checksum_local += data[i % I40E_SR_SECTOR_SIZE_IN_WORDS];
564 }
565
566 *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local;
567
568 i40e_calc_nvm_checksum_exit:
569 i40e_free_virt_mem(hw, &vmem);
570 return ret_code;
571 }
572
573 /**
574 * i40e_update_nvm_checksum - Updates the NVM checksum
575 * @hw: pointer to hardware structure
576 *
577 * NVM ownership must be acquired before calling this function and released
578 * on ARQ completion event reception by caller.
579 * This function will commit SR to NVM.
580 **/
i40e_update_nvm_checksum(struct i40e_hw * hw)581 i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw)
582 {
583 i40e_status ret_code;
584 u16 checksum;
585 __le16 le_sum;
586
587 ret_code = i40e_calc_nvm_checksum(hw, &checksum);
588 if (!ret_code) {
589 le_sum = cpu_to_le16(checksum);
590 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
591 1, &le_sum, true);
592 }
593
594 return ret_code;
595 }
596
597 /**
598 * i40e_validate_nvm_checksum - Validate EEPROM checksum
599 * @hw: pointer to hardware structure
600 * @checksum: calculated checksum
601 *
602 * Performs checksum calculation and validates the NVM SW checksum. If the
603 * caller does not need checksum, the value can be NULL.
604 **/
i40e_validate_nvm_checksum(struct i40e_hw * hw,u16 * checksum)605 i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw,
606 u16 *checksum)
607 {
608 i40e_status ret_code = 0;
609 u16 checksum_sr = 0;
610 u16 checksum_local = 0;
611
612 /* We must acquire the NVM lock in order to correctly synchronize the
613 * NVM accesses across multiple PFs. Without doing so it is possible
614 * for one of the PFs to read invalid data potentially indicating that
615 * the checksum is invalid.
616 */
617 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
618 if (ret_code)
619 return ret_code;
620 ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
621 __i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);
622 i40e_release_nvm(hw);
623 if (ret_code)
624 return ret_code;
625
626 /* Verify read checksum from EEPROM is the same as
627 * calculated checksum
628 */
629 if (checksum_local != checksum_sr)
630 ret_code = I40E_ERR_NVM_CHECKSUM;
631
632 /* If the user cares, return the calculated checksum */
633 if (checksum)
634 *checksum = checksum_local;
635
636 return ret_code;
637 }
638
639 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw,
640 struct i40e_nvm_access *cmd,
641 u8 *bytes, int *perrno);
642 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw,
643 struct i40e_nvm_access *cmd,
644 u8 *bytes, int *perrno);
645 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw,
646 struct i40e_nvm_access *cmd,
647 u8 *bytes, int *errno);
648 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
649 struct i40e_nvm_access *cmd,
650 int *perrno);
651 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
652 struct i40e_nvm_access *cmd,
653 int *perrno);
654 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw,
655 struct i40e_nvm_access *cmd,
656 u8 *bytes, int *perrno);
657 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw,
658 struct i40e_nvm_access *cmd,
659 u8 *bytes, int *perrno);
660 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw,
661 struct i40e_nvm_access *cmd,
662 u8 *bytes, int *perrno);
663 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
664 struct i40e_nvm_access *cmd,
665 u8 *bytes, int *perrno);
i40e_nvmupd_get_module(u32 val)666 static inline u8 i40e_nvmupd_get_module(u32 val)
667 {
668 return (u8)(val & I40E_NVM_MOD_PNT_MASK);
669 }
i40e_nvmupd_get_transaction(u32 val)670 static inline u8 i40e_nvmupd_get_transaction(u32 val)
671 {
672 return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT);
673 }
674
675 static const char * const i40e_nvm_update_state_str[] = {
676 "I40E_NVMUPD_INVALID",
677 "I40E_NVMUPD_READ_CON",
678 "I40E_NVMUPD_READ_SNT",
679 "I40E_NVMUPD_READ_LCB",
680 "I40E_NVMUPD_READ_SA",
681 "I40E_NVMUPD_WRITE_ERA",
682 "I40E_NVMUPD_WRITE_CON",
683 "I40E_NVMUPD_WRITE_SNT",
684 "I40E_NVMUPD_WRITE_LCB",
685 "I40E_NVMUPD_WRITE_SA",
686 "I40E_NVMUPD_CSUM_CON",
687 "I40E_NVMUPD_CSUM_SA",
688 "I40E_NVMUPD_CSUM_LCB",
689 "I40E_NVMUPD_STATUS",
690 "I40E_NVMUPD_EXEC_AQ",
691 "I40E_NVMUPD_GET_AQ_RESULT",
692 };
693
694 /**
695 * i40e_nvmupd_command - Process an NVM update command
696 * @hw: pointer to hardware structure
697 * @cmd: pointer to nvm update command
698 * @bytes: pointer to the data buffer
699 * @perrno: pointer to return error code
700 *
701 * Dispatches command depending on what update state is current
702 **/
i40e_nvmupd_command(struct i40e_hw * hw,struct i40e_nvm_access * cmd,u8 * bytes,int * perrno)703 i40e_status i40e_nvmupd_command(struct i40e_hw *hw,
704 struct i40e_nvm_access *cmd,
705 u8 *bytes, int *perrno)
706 {
707 i40e_status status;
708 enum i40e_nvmupd_cmd upd_cmd;
709
710 /* assume success */
711 *perrno = 0;
712
713 /* early check for status command and debug msgs */
714 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
715
716 i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d\n",
717 i40e_nvm_update_state_str[upd_cmd],
718 hw->nvmupd_state,
719 hw->aq.nvm_release_on_done);
720
721 if (upd_cmd == I40E_NVMUPD_INVALID) {
722 *perrno = -EFAULT;
723 i40e_debug(hw, I40E_DEBUG_NVM,
724 "i40e_nvmupd_validate_command returns %d errno %d\n",
725 upd_cmd, *perrno);
726 }
727
728 /* a status request returns immediately rather than
729 * going into the state machine
730 */
731 if (upd_cmd == I40E_NVMUPD_STATUS) {
732 bytes[0] = hw->nvmupd_state;
733 return 0;
734 }
735
736 switch (hw->nvmupd_state) {
737 case I40E_NVMUPD_STATE_INIT:
738 status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno);
739 break;
740
741 case I40E_NVMUPD_STATE_READING:
742 status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno);
743 break;
744
745 case I40E_NVMUPD_STATE_WRITING:
746 status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno);
747 break;
748
749 case I40E_NVMUPD_STATE_INIT_WAIT:
750 case I40E_NVMUPD_STATE_WRITE_WAIT:
751 status = I40E_ERR_NOT_READY;
752 *perrno = -EBUSY;
753 break;
754
755 default:
756 /* invalid state, should never happen */
757 i40e_debug(hw, I40E_DEBUG_NVM,
758 "NVMUPD: no such state %d\n", hw->nvmupd_state);
759 status = I40E_NOT_SUPPORTED;
760 *perrno = -ESRCH;
761 break;
762 }
763 return status;
764 }
765
766 /**
767 * i40e_nvmupd_state_init - Handle NVM update state Init
768 * @hw: pointer to hardware structure
769 * @cmd: pointer to nvm update command buffer
770 * @bytes: pointer to the data buffer
771 * @perrno: pointer to return error code
772 *
773 * Process legitimate commands of the Init state and conditionally set next
774 * state. Reject all other commands.
775 **/
i40e_nvmupd_state_init(struct i40e_hw * hw,struct i40e_nvm_access * cmd,u8 * bytes,int * perrno)776 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw,
777 struct i40e_nvm_access *cmd,
778 u8 *bytes, int *perrno)
779 {
780 i40e_status status = 0;
781 enum i40e_nvmupd_cmd upd_cmd;
782
783 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
784
785 switch (upd_cmd) {
786 case I40E_NVMUPD_READ_SA:
787 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
788 if (status) {
789 *perrno = i40e_aq_rc_to_posix(status,
790 hw->aq.asq_last_status);
791 } else {
792 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
793 i40e_release_nvm(hw);
794 }
795 break;
796
797 case I40E_NVMUPD_READ_SNT:
798 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
799 if (status) {
800 *perrno = i40e_aq_rc_to_posix(status,
801 hw->aq.asq_last_status);
802 } else {
803 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
804 if (status)
805 i40e_release_nvm(hw);
806 else
807 hw->nvmupd_state = I40E_NVMUPD_STATE_READING;
808 }
809 break;
810
811 case I40E_NVMUPD_WRITE_ERA:
812 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
813 if (status) {
814 *perrno = i40e_aq_rc_to_posix(status,
815 hw->aq.asq_last_status);
816 } else {
817 status = i40e_nvmupd_nvm_erase(hw, cmd, perrno);
818 if (status) {
819 i40e_release_nvm(hw);
820 } else {
821 hw->aq.nvm_release_on_done = true;
822 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
823 }
824 }
825 break;
826
827 case I40E_NVMUPD_WRITE_SA:
828 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
829 if (status) {
830 *perrno = i40e_aq_rc_to_posix(status,
831 hw->aq.asq_last_status);
832 } else {
833 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
834 if (status) {
835 i40e_release_nvm(hw);
836 } else {
837 hw->aq.nvm_release_on_done = true;
838 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
839 }
840 }
841 break;
842
843 case I40E_NVMUPD_WRITE_SNT:
844 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
845 if (status) {
846 *perrno = i40e_aq_rc_to_posix(status,
847 hw->aq.asq_last_status);
848 } else {
849 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
850 if (status)
851 i40e_release_nvm(hw);
852 else
853 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
854 }
855 break;
856
857 case I40E_NVMUPD_CSUM_SA:
858 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
859 if (status) {
860 *perrno = i40e_aq_rc_to_posix(status,
861 hw->aq.asq_last_status);
862 } else {
863 status = i40e_update_nvm_checksum(hw);
864 if (status) {
865 *perrno = hw->aq.asq_last_status ?
866 i40e_aq_rc_to_posix(status,
867 hw->aq.asq_last_status) :
868 -EIO;
869 i40e_release_nvm(hw);
870 } else {
871 hw->aq.nvm_release_on_done = true;
872 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
873 }
874 }
875 break;
876
877 case I40E_NVMUPD_EXEC_AQ:
878 status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno);
879 break;
880
881 case I40E_NVMUPD_GET_AQ_RESULT:
882 status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno);
883 break;
884
885 default:
886 i40e_debug(hw, I40E_DEBUG_NVM,
887 "NVMUPD: bad cmd %s in init state\n",
888 i40e_nvm_update_state_str[upd_cmd]);
889 status = I40E_ERR_NVM;
890 *perrno = -ESRCH;
891 break;
892 }
893 return status;
894 }
895
896 /**
897 * i40e_nvmupd_state_reading - Handle NVM update state Reading
898 * @hw: pointer to hardware structure
899 * @cmd: pointer to nvm update command buffer
900 * @bytes: pointer to the data buffer
901 * @perrno: pointer to return error code
902 *
903 * NVM ownership is already held. Process legitimate commands and set any
904 * change in state; reject all other commands.
905 **/
i40e_nvmupd_state_reading(struct i40e_hw * hw,struct i40e_nvm_access * cmd,u8 * bytes,int * perrno)906 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw,
907 struct i40e_nvm_access *cmd,
908 u8 *bytes, int *perrno)
909 {
910 i40e_status status = 0;
911 enum i40e_nvmupd_cmd upd_cmd;
912
913 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
914
915 switch (upd_cmd) {
916 case I40E_NVMUPD_READ_SA:
917 case I40E_NVMUPD_READ_CON:
918 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
919 break;
920
921 case I40E_NVMUPD_READ_LCB:
922 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
923 i40e_release_nvm(hw);
924 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
925 break;
926
927 default:
928 i40e_debug(hw, I40E_DEBUG_NVM,
929 "NVMUPD: bad cmd %s in reading state.\n",
930 i40e_nvm_update_state_str[upd_cmd]);
931 status = I40E_NOT_SUPPORTED;
932 *perrno = -ESRCH;
933 break;
934 }
935 return status;
936 }
937
938 /**
939 * i40e_nvmupd_state_writing - Handle NVM update state Writing
940 * @hw: pointer to hardware structure
941 * @cmd: pointer to nvm update command buffer
942 * @bytes: pointer to the data buffer
943 * @perrno: pointer to return error code
944 *
945 * NVM ownership is already held. Process legitimate commands and set any
946 * change in state; reject all other commands
947 **/
i40e_nvmupd_state_writing(struct i40e_hw * hw,struct i40e_nvm_access * cmd,u8 * bytes,int * perrno)948 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw,
949 struct i40e_nvm_access *cmd,
950 u8 *bytes, int *perrno)
951 {
952 i40e_status status = 0;
953 enum i40e_nvmupd_cmd upd_cmd;
954 bool retry_attempt = false;
955
956 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
957
958 retry:
959 switch (upd_cmd) {
960 case I40E_NVMUPD_WRITE_CON:
961 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
962 if (!status)
963 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
964 break;
965
966 case I40E_NVMUPD_WRITE_LCB:
967 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
968 if (status) {
969 *perrno = hw->aq.asq_last_status ?
970 i40e_aq_rc_to_posix(status,
971 hw->aq.asq_last_status) :
972 -EIO;
973 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
974 } else {
975 hw->aq.nvm_release_on_done = true;
976 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
977 }
978 break;
979
980 case I40E_NVMUPD_CSUM_CON:
981 /* Assumes the caller has acquired the nvm */
982 status = i40e_update_nvm_checksum(hw);
983 if (status) {
984 *perrno = hw->aq.asq_last_status ?
985 i40e_aq_rc_to_posix(status,
986 hw->aq.asq_last_status) :
987 -EIO;
988 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
989 } else {
990 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
991 }
992 break;
993
994 case I40E_NVMUPD_CSUM_LCB:
995 /* Assumes the caller has acquired the nvm */
996 status = i40e_update_nvm_checksum(hw);
997 if (status) {
998 *perrno = hw->aq.asq_last_status ?
999 i40e_aq_rc_to_posix(status,
1000 hw->aq.asq_last_status) :
1001 -EIO;
1002 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1003 } else {
1004 hw->aq.nvm_release_on_done = true;
1005 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1006 }
1007 break;
1008
1009 default:
1010 i40e_debug(hw, I40E_DEBUG_NVM,
1011 "NVMUPD: bad cmd %s in writing state.\n",
1012 i40e_nvm_update_state_str[upd_cmd]);
1013 status = I40E_NOT_SUPPORTED;
1014 *perrno = -ESRCH;
1015 break;
1016 }
1017
1018 /* In some circumstances, a multi-write transaction takes longer
1019 * than the default 3 minute timeout on the write semaphore. If
1020 * the write failed with an EBUSY status, this is likely the problem,
1021 * so here we try to reacquire the semaphore then retry the write.
1022 * We only do one retry, then give up.
1023 */
1024 if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) &&
1025 !retry_attempt) {
1026 i40e_status old_status = status;
1027 u32 old_asq_status = hw->aq.asq_last_status;
1028 u32 gtime;
1029
1030 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
1031 if (gtime >= hw->nvm.hw_semaphore_timeout) {
1032 i40e_debug(hw, I40E_DEBUG_ALL,
1033 "NVMUPD: write semaphore expired (%d >= %lld), retrying\n",
1034 gtime, hw->nvm.hw_semaphore_timeout);
1035 i40e_release_nvm(hw);
1036 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
1037 if (status) {
1038 i40e_debug(hw, I40E_DEBUG_ALL,
1039 "NVMUPD: write semaphore reacquire failed aq_err = %d\n",
1040 hw->aq.asq_last_status);
1041 status = old_status;
1042 hw->aq.asq_last_status = old_asq_status;
1043 } else {
1044 retry_attempt = true;
1045 goto retry;
1046 }
1047 }
1048 }
1049
1050 return status;
1051 }
1052
1053 /**
1054 * i40e_nvmupd_validate_command - Validate given command
1055 * @hw: pointer to hardware structure
1056 * @cmd: pointer to nvm update command buffer
1057 * @perrno: pointer to return error code
1058 *
1059 * Return one of the valid command types or I40E_NVMUPD_INVALID
1060 **/
i40e_nvmupd_validate_command(struct i40e_hw * hw,struct i40e_nvm_access * cmd,int * perrno)1061 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
1062 struct i40e_nvm_access *cmd,
1063 int *perrno)
1064 {
1065 enum i40e_nvmupd_cmd upd_cmd;
1066 u8 module, transaction;
1067
1068 /* anything that doesn't match a recognized case is an error */
1069 upd_cmd = I40E_NVMUPD_INVALID;
1070
1071 transaction = i40e_nvmupd_get_transaction(cmd->config);
1072 module = i40e_nvmupd_get_module(cmd->config);
1073
1074 /* limits on data size */
1075 if ((cmd->data_size < 1) ||
1076 (cmd->data_size > I40E_NVMUPD_MAX_DATA)) {
1077 i40e_debug(hw, I40E_DEBUG_NVM,
1078 "i40e_nvmupd_validate_command data_size %d\n",
1079 cmd->data_size);
1080 *perrno = -EFAULT;
1081 return I40E_NVMUPD_INVALID;
1082 }
1083
1084 switch (cmd->command) {
1085 case I40E_NVM_READ:
1086 switch (transaction) {
1087 case I40E_NVM_CON:
1088 upd_cmd = I40E_NVMUPD_READ_CON;
1089 break;
1090 case I40E_NVM_SNT:
1091 upd_cmd = I40E_NVMUPD_READ_SNT;
1092 break;
1093 case I40E_NVM_LCB:
1094 upd_cmd = I40E_NVMUPD_READ_LCB;
1095 break;
1096 case I40E_NVM_SA:
1097 upd_cmd = I40E_NVMUPD_READ_SA;
1098 break;
1099 case I40E_NVM_EXEC:
1100 if (module == 0xf)
1101 upd_cmd = I40E_NVMUPD_STATUS;
1102 else if (module == 0)
1103 upd_cmd = I40E_NVMUPD_GET_AQ_RESULT;
1104 break;
1105 }
1106 break;
1107
1108 case I40E_NVM_WRITE:
1109 switch (transaction) {
1110 case I40E_NVM_CON:
1111 upd_cmd = I40E_NVMUPD_WRITE_CON;
1112 break;
1113 case I40E_NVM_SNT:
1114 upd_cmd = I40E_NVMUPD_WRITE_SNT;
1115 break;
1116 case I40E_NVM_LCB:
1117 upd_cmd = I40E_NVMUPD_WRITE_LCB;
1118 break;
1119 case I40E_NVM_SA:
1120 upd_cmd = I40E_NVMUPD_WRITE_SA;
1121 break;
1122 case I40E_NVM_ERA:
1123 upd_cmd = I40E_NVMUPD_WRITE_ERA;
1124 break;
1125 case I40E_NVM_CSUM:
1126 upd_cmd = I40E_NVMUPD_CSUM_CON;
1127 break;
1128 case (I40E_NVM_CSUM|I40E_NVM_SA):
1129 upd_cmd = I40E_NVMUPD_CSUM_SA;
1130 break;
1131 case (I40E_NVM_CSUM|I40E_NVM_LCB):
1132 upd_cmd = I40E_NVMUPD_CSUM_LCB;
1133 break;
1134 case I40E_NVM_EXEC:
1135 if (module == 0)
1136 upd_cmd = I40E_NVMUPD_EXEC_AQ;
1137 break;
1138 }
1139 break;
1140 }
1141
1142 return upd_cmd;
1143 }
1144
1145 /**
1146 * i40e_nvmupd_exec_aq - Run an AQ command
1147 * @hw: pointer to hardware structure
1148 * @cmd: pointer to nvm update command buffer
1149 * @bytes: pointer to the data buffer
1150 * @perrno: pointer to return error code
1151 *
1152 * cmd structure contains identifiers and data buffer
1153 **/
i40e_nvmupd_exec_aq(struct i40e_hw * hw,struct i40e_nvm_access * cmd,u8 * bytes,int * perrno)1154 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw,
1155 struct i40e_nvm_access *cmd,
1156 u8 *bytes, int *perrno)
1157 {
1158 struct i40e_asq_cmd_details cmd_details;
1159 i40e_status status;
1160 struct i40e_aq_desc *aq_desc;
1161 u32 buff_size = 0;
1162 u8 *buff = NULL;
1163 u32 aq_desc_len;
1164 u32 aq_data_len;
1165
1166 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1167 memset(&cmd_details, 0, sizeof(cmd_details));
1168 cmd_details.wb_desc = &hw->nvm_wb_desc;
1169
1170 aq_desc_len = sizeof(struct i40e_aq_desc);
1171 memset(&hw->nvm_wb_desc, 0, aq_desc_len);
1172
1173 /* get the aq descriptor */
1174 if (cmd->data_size < aq_desc_len) {
1175 i40e_debug(hw, I40E_DEBUG_NVM,
1176 "NVMUPD: not enough aq desc bytes for exec, size %d < %d\n",
1177 cmd->data_size, aq_desc_len);
1178 *perrno = -EINVAL;
1179 return I40E_ERR_PARAM;
1180 }
1181 aq_desc = (struct i40e_aq_desc *)bytes;
1182
1183 /* if data buffer needed, make sure it's ready */
1184 aq_data_len = cmd->data_size - aq_desc_len;
1185 buff_size = max_t(u32, aq_data_len, le16_to_cpu(aq_desc->datalen));
1186 if (buff_size) {
1187 if (!hw->nvm_buff.va) {
1188 status = i40e_allocate_virt_mem(hw, &hw->nvm_buff,
1189 hw->aq.asq_buf_size);
1190 if (status)
1191 i40e_debug(hw, I40E_DEBUG_NVM,
1192 "NVMUPD: i40e_allocate_virt_mem for exec buff failed, %d\n",
1193 status);
1194 }
1195
1196 if (hw->nvm_buff.va) {
1197 buff = hw->nvm_buff.va;
1198 memcpy(buff, &bytes[aq_desc_len], aq_data_len);
1199 }
1200 }
1201
1202 /* and away we go! */
1203 status = i40e_asq_send_command(hw, aq_desc, buff,
1204 buff_size, &cmd_details);
1205 if (status) {
1206 i40e_debug(hw, I40E_DEBUG_NVM,
1207 "i40e_nvmupd_exec_aq err %s aq_err %s\n",
1208 i40e_stat_str(hw, status),
1209 i40e_aq_str(hw, hw->aq.asq_last_status));
1210 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1211 }
1212
1213 return status;
1214 }
1215
1216 /**
1217 * i40e_nvmupd_get_aq_result - Get the results from the previous exec_aq
1218 * @hw: pointer to hardware structure
1219 * @cmd: pointer to nvm update command buffer
1220 * @bytes: pointer to the data buffer
1221 * @perrno: pointer to return error code
1222 *
1223 * cmd structure contains identifiers and data buffer
1224 **/
i40e_nvmupd_get_aq_result(struct i40e_hw * hw,struct i40e_nvm_access * cmd,u8 * bytes,int * perrno)1225 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
1226 struct i40e_nvm_access *cmd,
1227 u8 *bytes, int *perrno)
1228 {
1229 u32 aq_total_len;
1230 u32 aq_desc_len;
1231 int remainder;
1232 u8 *buff;
1233
1234 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1235
1236 aq_desc_len = sizeof(struct i40e_aq_desc);
1237 aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_wb_desc.datalen);
1238
1239 /* check offset range */
1240 if (cmd->offset > aq_total_len) {
1241 i40e_debug(hw, I40E_DEBUG_NVM, "%s: offset too big %d > %d\n",
1242 __func__, cmd->offset, aq_total_len);
1243 *perrno = -EINVAL;
1244 return I40E_ERR_PARAM;
1245 }
1246
1247 /* check copylength range */
1248 if (cmd->data_size > (aq_total_len - cmd->offset)) {
1249 int new_len = aq_total_len - cmd->offset;
1250
1251 i40e_debug(hw, I40E_DEBUG_NVM, "%s: copy length %d too big, trimming to %d\n",
1252 __func__, cmd->data_size, new_len);
1253 cmd->data_size = new_len;
1254 }
1255
1256 remainder = cmd->data_size;
1257 if (cmd->offset < aq_desc_len) {
1258 u32 len = aq_desc_len - cmd->offset;
1259
1260 len = min(len, cmd->data_size);
1261 i40e_debug(hw, I40E_DEBUG_NVM, "%s: aq_desc bytes %d to %d\n",
1262 __func__, cmd->offset, cmd->offset + len);
1263
1264 buff = ((u8 *)&hw->nvm_wb_desc) + cmd->offset;
1265 memcpy(bytes, buff, len);
1266
1267 bytes += len;
1268 remainder -= len;
1269 buff = hw->nvm_buff.va;
1270 } else {
1271 buff = hw->nvm_buff.va + (cmd->offset - aq_desc_len);
1272 }
1273
1274 if (remainder > 0) {
1275 int start_byte = buff - (u8 *)hw->nvm_buff.va;
1276
1277 i40e_debug(hw, I40E_DEBUG_NVM, "%s: databuf bytes %d to %d\n",
1278 __func__, start_byte, start_byte + remainder);
1279 memcpy(bytes, buff, remainder);
1280 }
1281
1282 return 0;
1283 }
1284
1285 /**
1286 * i40e_nvmupd_nvm_read - Read NVM
1287 * @hw: pointer to hardware structure
1288 * @cmd: pointer to nvm update command buffer
1289 * @bytes: pointer to the data buffer
1290 * @perrno: pointer to return error code
1291 *
1292 * cmd structure contains identifiers and data buffer
1293 **/
i40e_nvmupd_nvm_read(struct i40e_hw * hw,struct i40e_nvm_access * cmd,u8 * bytes,int * perrno)1294 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw,
1295 struct i40e_nvm_access *cmd,
1296 u8 *bytes, int *perrno)
1297 {
1298 struct i40e_asq_cmd_details cmd_details;
1299 i40e_status status;
1300 u8 module, transaction;
1301 bool last;
1302
1303 transaction = i40e_nvmupd_get_transaction(cmd->config);
1304 module = i40e_nvmupd_get_module(cmd->config);
1305 last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA);
1306
1307 memset(&cmd_details, 0, sizeof(cmd_details));
1308 cmd_details.wb_desc = &hw->nvm_wb_desc;
1309
1310 status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1311 bytes, last, &cmd_details);
1312 if (status) {
1313 i40e_debug(hw, I40E_DEBUG_NVM,
1314 "i40e_nvmupd_nvm_read mod 0x%x off 0x%x len 0x%x\n",
1315 module, cmd->offset, cmd->data_size);
1316 i40e_debug(hw, I40E_DEBUG_NVM,
1317 "i40e_nvmupd_nvm_read status %d aq %d\n",
1318 status, hw->aq.asq_last_status);
1319 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1320 }
1321
1322 return status;
1323 }
1324
1325 /**
1326 * i40e_nvmupd_nvm_erase - Erase an NVM module
1327 * @hw: pointer to hardware structure
1328 * @cmd: pointer to nvm update command buffer
1329 * @perrno: pointer to return error code
1330 *
1331 * module, offset, data_size and data are in cmd structure
1332 **/
i40e_nvmupd_nvm_erase(struct i40e_hw * hw,struct i40e_nvm_access * cmd,int * perrno)1333 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
1334 struct i40e_nvm_access *cmd,
1335 int *perrno)
1336 {
1337 i40e_status status = 0;
1338 struct i40e_asq_cmd_details cmd_details;
1339 u8 module, transaction;
1340 bool last;
1341
1342 transaction = i40e_nvmupd_get_transaction(cmd->config);
1343 module = i40e_nvmupd_get_module(cmd->config);
1344 last = (transaction & I40E_NVM_LCB);
1345
1346 memset(&cmd_details, 0, sizeof(cmd_details));
1347 cmd_details.wb_desc = &hw->nvm_wb_desc;
1348
1349 status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1350 last, &cmd_details);
1351 if (status) {
1352 i40e_debug(hw, I40E_DEBUG_NVM,
1353 "i40e_nvmupd_nvm_erase mod 0x%x off 0x%x len 0x%x\n",
1354 module, cmd->offset, cmd->data_size);
1355 i40e_debug(hw, I40E_DEBUG_NVM,
1356 "i40e_nvmupd_nvm_erase status %d aq %d\n",
1357 status, hw->aq.asq_last_status);
1358 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1359 }
1360
1361 return status;
1362 }
1363
1364 /**
1365 * i40e_nvmupd_nvm_write - Write NVM
1366 * @hw: pointer to hardware structure
1367 * @cmd: pointer to nvm update command buffer
1368 * @bytes: pointer to the data buffer
1369 * @perrno: pointer to return error code
1370 *
1371 * module, offset, data_size and data are in cmd structure
1372 **/
i40e_nvmupd_nvm_write(struct i40e_hw * hw,struct i40e_nvm_access * cmd,u8 * bytes,int * perrno)1373 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw,
1374 struct i40e_nvm_access *cmd,
1375 u8 *bytes, int *perrno)
1376 {
1377 i40e_status status = 0;
1378 struct i40e_asq_cmd_details cmd_details;
1379 u8 module, transaction;
1380 bool last;
1381
1382 transaction = i40e_nvmupd_get_transaction(cmd->config);
1383 module = i40e_nvmupd_get_module(cmd->config);
1384 last = (transaction & I40E_NVM_LCB);
1385
1386 memset(&cmd_details, 0, sizeof(cmd_details));
1387 cmd_details.wb_desc = &hw->nvm_wb_desc;
1388
1389 status = i40e_aq_update_nvm(hw, module, cmd->offset,
1390 (u16)cmd->data_size, bytes, last,
1391 &cmd_details);
1392 if (status) {
1393 i40e_debug(hw, I40E_DEBUG_NVM,
1394 "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n",
1395 module, cmd->offset, cmd->data_size);
1396 i40e_debug(hw, I40E_DEBUG_NVM,
1397 "i40e_nvmupd_nvm_write status %d aq %d\n",
1398 status, hw->aq.asq_last_status);
1399 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1400 }
1401
1402 return status;
1403 }
1404