1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/async.h>
32 #include <drm/drmP.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_fb_helper.h>
35 #include <drm/drm_legacy.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_vgpu.h"
40 #include "i915_trace.h"
41 #include <linux/pci.h>
42 #include <linux/console.h>
43 #include <linux/vt.h>
44 #include <linux/vgaarb.h>
45 #include <linux/acpi.h>
46 #include <linux/pnp.h>
47 #include <linux/vga_switcheroo.h>
48 #include <linux/slab.h>
49 #include <acpi/video.h>
50 #include <linux/pm.h>
51 #include <linux/pm_runtime.h>
52 #include <linux/oom.h>
53
54
i915_getparam(struct drm_device * dev,void * data,struct drm_file * file_priv)55 static int i915_getparam(struct drm_device *dev, void *data,
56 struct drm_file *file_priv)
57 {
58 struct drm_i915_private *dev_priv = dev->dev_private;
59 drm_i915_getparam_t *param = data;
60 int value;
61
62 switch (param->param) {
63 case I915_PARAM_IRQ_ACTIVE:
64 case I915_PARAM_ALLOW_BATCHBUFFER:
65 case I915_PARAM_LAST_DISPATCH:
66 /* Reject all old ums/dri params. */
67 return -ENODEV;
68 case I915_PARAM_CHIPSET_ID:
69 value = dev->pdev->device;
70 break;
71 case I915_PARAM_REVISION:
72 value = dev->pdev->revision;
73 break;
74 case I915_PARAM_HAS_GEM:
75 value = 1;
76 break;
77 case I915_PARAM_NUM_FENCES_AVAIL:
78 value = dev_priv->num_fence_regs;
79 break;
80 case I915_PARAM_HAS_OVERLAY:
81 value = dev_priv->overlay ? 1 : 0;
82 break;
83 case I915_PARAM_HAS_PAGEFLIPPING:
84 value = 1;
85 break;
86 case I915_PARAM_HAS_EXECBUF2:
87 /* depends on GEM */
88 value = 1;
89 break;
90 case I915_PARAM_HAS_BSD:
91 value = intel_ring_initialized(&dev_priv->ring[VCS]);
92 break;
93 case I915_PARAM_HAS_BLT:
94 value = intel_ring_initialized(&dev_priv->ring[BCS]);
95 break;
96 case I915_PARAM_HAS_VEBOX:
97 value = intel_ring_initialized(&dev_priv->ring[VECS]);
98 break;
99 case I915_PARAM_HAS_BSD2:
100 value = intel_ring_initialized(&dev_priv->ring[VCS2]);
101 break;
102 case I915_PARAM_HAS_RELAXED_FENCING:
103 value = 1;
104 break;
105 case I915_PARAM_HAS_COHERENT_RINGS:
106 value = 1;
107 break;
108 case I915_PARAM_HAS_EXEC_CONSTANTS:
109 value = INTEL_INFO(dev)->gen >= 4;
110 break;
111 case I915_PARAM_HAS_RELAXED_DELTA:
112 value = 1;
113 break;
114 case I915_PARAM_HAS_GEN7_SOL_RESET:
115 value = 1;
116 break;
117 case I915_PARAM_HAS_LLC:
118 value = HAS_LLC(dev);
119 break;
120 case I915_PARAM_HAS_WT:
121 value = HAS_WT(dev);
122 break;
123 case I915_PARAM_HAS_ALIASING_PPGTT:
124 value = USES_PPGTT(dev);
125 break;
126 case I915_PARAM_HAS_WAIT_TIMEOUT:
127 value = 1;
128 break;
129 case I915_PARAM_HAS_SEMAPHORES:
130 value = i915_semaphore_is_enabled(dev);
131 break;
132 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
133 value = 1;
134 break;
135 case I915_PARAM_HAS_SECURE_BATCHES:
136 value = HAS_SECURE_BATCHES(dev_priv) && capable(CAP_SYS_ADMIN);
137 break;
138 case I915_PARAM_HAS_PINNED_BATCHES:
139 value = 1;
140 break;
141 case I915_PARAM_HAS_EXEC_NO_RELOC:
142 value = 1;
143 break;
144 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
145 value = 1;
146 break;
147 case I915_PARAM_CMD_PARSER_VERSION:
148 value = i915_cmd_parser_get_version(dev_priv);
149 break;
150 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
151 value = 1;
152 break;
153 case I915_PARAM_MMAP_VERSION:
154 value = 1;
155 break;
156 case I915_PARAM_SUBSLICE_TOTAL:
157 value = INTEL_INFO(dev)->subslice_total;
158 if (!value)
159 return -ENODEV;
160 break;
161 case I915_PARAM_EU_TOTAL:
162 value = INTEL_INFO(dev)->eu_total;
163 if (!value)
164 return -ENODEV;
165 break;
166 case I915_PARAM_HAS_GPU_RESET:
167 value = i915.enable_hangcheck &&
168 intel_has_gpu_reset(dev);
169 break;
170 case I915_PARAM_HAS_RESOURCE_STREAMER:
171 value = HAS_RESOURCE_STREAMER(dev);
172 break;
173 default:
174 DRM_DEBUG("Unknown parameter %d\n", param->param);
175 return -EINVAL;
176 }
177
178 if (copy_to_user(param->value, &value, sizeof(int))) {
179 DRM_ERROR("copy_to_user failed\n");
180 return -EFAULT;
181 }
182
183 return 0;
184 }
185
i915_get_bridge_dev(struct drm_device * dev)186 static int i915_get_bridge_dev(struct drm_device *dev)
187 {
188 struct drm_i915_private *dev_priv = dev->dev_private;
189
190 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
191 if (!dev_priv->bridge_dev) {
192 DRM_ERROR("bridge device not found\n");
193 return -1;
194 }
195 return 0;
196 }
197
198 #define MCHBAR_I915 0x44
199 #define MCHBAR_I965 0x48
200 #define MCHBAR_SIZE (4*4096)
201
202 #define DEVEN_REG 0x54
203 #define DEVEN_MCHBAR_EN (1 << 28)
204
205 /* Allocate space for the MCH regs if needed, return nonzero on error */
206 static int
intel_alloc_mchbar_resource(struct drm_device * dev)207 intel_alloc_mchbar_resource(struct drm_device *dev)
208 {
209 struct drm_i915_private *dev_priv = dev->dev_private;
210 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
211 u32 temp_lo, temp_hi = 0;
212 u64 mchbar_addr;
213 int ret;
214
215 if (INTEL_INFO(dev)->gen >= 4)
216 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
217 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
218 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
219
220 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
221 #ifdef CONFIG_PNP
222 if (mchbar_addr &&
223 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
224 return 0;
225 #endif
226
227 /* Get some space for it */
228 dev_priv->mch_res.name = "i915 MCHBAR";
229 dev_priv->mch_res.flags = IORESOURCE_MEM;
230 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
231 &dev_priv->mch_res,
232 MCHBAR_SIZE, MCHBAR_SIZE,
233 PCIBIOS_MIN_MEM,
234 0, pcibios_align_resource,
235 dev_priv->bridge_dev);
236 if (ret) {
237 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
238 dev_priv->mch_res.start = 0;
239 return ret;
240 }
241
242 if (INTEL_INFO(dev)->gen >= 4)
243 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
244 upper_32_bits(dev_priv->mch_res.start));
245
246 pci_write_config_dword(dev_priv->bridge_dev, reg,
247 lower_32_bits(dev_priv->mch_res.start));
248 return 0;
249 }
250
251 /* Setup MCHBAR if possible, return true if we should disable it again */
252 static void
intel_setup_mchbar(struct drm_device * dev)253 intel_setup_mchbar(struct drm_device *dev)
254 {
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
257 u32 temp;
258 bool enabled;
259
260 if (IS_VALLEYVIEW(dev))
261 return;
262
263 dev_priv->mchbar_need_disable = false;
264
265 if (IS_I915G(dev) || IS_I915GM(dev)) {
266 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
267 enabled = !!(temp & DEVEN_MCHBAR_EN);
268 } else {
269 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
270 enabled = temp & 1;
271 }
272
273 /* If it's already enabled, don't have to do anything */
274 if (enabled)
275 return;
276
277 if (intel_alloc_mchbar_resource(dev))
278 return;
279
280 dev_priv->mchbar_need_disable = true;
281
282 /* Space is allocated or reserved, so enable it. */
283 if (IS_I915G(dev) || IS_I915GM(dev)) {
284 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
285 temp | DEVEN_MCHBAR_EN);
286 } else {
287 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
288 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
289 }
290 }
291
292 static void
intel_teardown_mchbar(struct drm_device * dev)293 intel_teardown_mchbar(struct drm_device *dev)
294 {
295 struct drm_i915_private *dev_priv = dev->dev_private;
296 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
297 u32 temp;
298
299 if (dev_priv->mchbar_need_disable) {
300 if (IS_I915G(dev) || IS_I915GM(dev)) {
301 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
302 temp &= ~DEVEN_MCHBAR_EN;
303 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
304 } else {
305 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
306 temp &= ~1;
307 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
308 }
309 }
310
311 if (dev_priv->mch_res.start)
312 release_resource(&dev_priv->mch_res);
313 }
314
315 /* true = enable decode, false = disable decoder */
i915_vga_set_decode(void * cookie,bool state)316 static unsigned int i915_vga_set_decode(void *cookie, bool state)
317 {
318 struct drm_device *dev = cookie;
319
320 intel_modeset_vga_set_state(dev, state);
321 if (state)
322 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
323 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
324 else
325 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
326 }
327
i915_switcheroo_set_state(struct pci_dev * pdev,enum vga_switcheroo_state state)328 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
329 {
330 struct drm_device *dev = pci_get_drvdata(pdev);
331 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
332
333 if (state == VGA_SWITCHEROO_ON) {
334 pr_info("switched on\n");
335 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
336 /* i915 resume handler doesn't set to D0 */
337 pci_set_power_state(dev->pdev, PCI_D0);
338 i915_resume_switcheroo(dev);
339 dev->switch_power_state = DRM_SWITCH_POWER_ON;
340 } else {
341 pr_err("switched off\n");
342 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
343 i915_suspend_switcheroo(dev, pmm);
344 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
345 }
346 }
347
i915_switcheroo_can_switch(struct pci_dev * pdev)348 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
349 {
350 struct drm_device *dev = pci_get_drvdata(pdev);
351
352 /*
353 * FIXME: open_count is protected by drm_global_mutex but that would lead to
354 * locking inversion with the driver load path. And the access here is
355 * completely racy anyway. So don't bother with locking for now.
356 */
357 return dev->open_count == 0;
358 }
359
360 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
361 .set_gpu_state = i915_switcheroo_set_state,
362 .reprobe = NULL,
363 .can_switch = i915_switcheroo_can_switch,
364 };
365
i915_load_modeset_init(struct drm_device * dev)366 static int i915_load_modeset_init(struct drm_device *dev)
367 {
368 struct drm_i915_private *dev_priv = dev->dev_private;
369 int ret;
370
371 ret = intel_parse_bios(dev);
372 if (ret)
373 DRM_INFO("failed to find VBIOS tables\n");
374
375 /* If we have > 1 VGA cards, then we need to arbitrate access
376 * to the common VGA resources.
377 *
378 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
379 * then we do not take part in VGA arbitration and the
380 * vga_client_register() fails with -ENODEV.
381 */
382 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
383 if (ret && ret != -ENODEV)
384 goto out;
385
386 intel_register_dsm_handler();
387
388 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
389 if (ret)
390 goto cleanup_vga_client;
391
392 /* Initialise stolen first so that we may reserve preallocated
393 * objects for the BIOS to KMS transition.
394 */
395 ret = i915_gem_init_stolen(dev);
396 if (ret)
397 goto cleanup_vga_switcheroo;
398
399 intel_power_domains_init_hw(dev_priv);
400
401 ret = intel_irq_install(dev_priv);
402 if (ret)
403 goto cleanup_gem_stolen;
404
405 intel_setup_gmbus(dev);
406
407 /* Important: The output setup functions called by modeset_init need
408 * working irqs for e.g. gmbus and dp aux transfers. */
409 intel_modeset_init(dev);
410
411 intel_guc_ucode_init(dev);
412
413 ret = i915_gem_init(dev);
414 if (ret)
415 goto cleanup_irq;
416
417 intel_modeset_gem_init(dev);
418
419 /* Always safe in the mode setting case. */
420 /* FIXME: do pre/post-mode set stuff in core KMS code */
421 dev->vblank_disable_allowed = true;
422 if (INTEL_INFO(dev)->num_pipes == 0)
423 return 0;
424
425 ret = intel_fbdev_init(dev);
426 if (ret)
427 goto cleanup_gem;
428
429 /* Only enable hotplug handling once the fbdev is fully set up. */
430 intel_hpd_init(dev_priv);
431
432 /*
433 * Some ports require correctly set-up hpd registers for detection to
434 * work properly (leading to ghost connected connector status), e.g. VGA
435 * on gm45. Hence we can only set up the initial fbdev config after hpd
436 * irqs are fully enabled. Now we should scan for the initial config
437 * only once hotplug handling is enabled, but due to screwed-up locking
438 * around kms/fbdev init we can't protect the fdbev initial config
439 * scanning against hotplug events. Hence do this first and ignore the
440 * tiny window where we will loose hotplug notifactions.
441 */
442 async_schedule(intel_fbdev_initial_config, dev_priv);
443
444 drm_kms_helper_poll_init(dev);
445
446 return 0;
447
448 cleanup_gem:
449 mutex_lock(&dev->struct_mutex);
450 i915_gem_cleanup_ringbuffer(dev);
451 i915_gem_context_fini(dev);
452 mutex_unlock(&dev->struct_mutex);
453 cleanup_irq:
454 intel_guc_ucode_fini(dev);
455 drm_irq_uninstall(dev);
456 intel_teardown_gmbus(dev);
457 cleanup_gem_stolen:
458 i915_gem_cleanup_stolen(dev);
459 cleanup_vga_switcheroo:
460 vga_switcheroo_unregister_client(dev->pdev);
461 cleanup_vga_client:
462 vga_client_register(dev->pdev, NULL, NULL, NULL);
463 out:
464 return ret;
465 }
466
467 #if IS_ENABLED(CONFIG_FB)
i915_kick_out_firmware_fb(struct drm_i915_private * dev_priv)468 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
469 {
470 struct apertures_struct *ap;
471 struct pci_dev *pdev = dev_priv->dev->pdev;
472 bool primary;
473 int ret;
474
475 ap = alloc_apertures(1);
476 if (!ap)
477 return -ENOMEM;
478
479 ap->ranges[0].base = dev_priv->gtt.mappable_base;
480 ap->ranges[0].size = dev_priv->gtt.mappable_end;
481
482 primary =
483 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
484
485 ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
486
487 kfree(ap);
488
489 return ret;
490 }
491 #else
i915_kick_out_firmware_fb(struct drm_i915_private * dev_priv)492 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
493 {
494 return 0;
495 }
496 #endif
497
498 #if !defined(CONFIG_VGA_CONSOLE)
i915_kick_out_vgacon(struct drm_i915_private * dev_priv)499 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
500 {
501 return 0;
502 }
503 #elif !defined(CONFIG_DUMMY_CONSOLE)
i915_kick_out_vgacon(struct drm_i915_private * dev_priv)504 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
505 {
506 return -ENODEV;
507 }
508 #else
i915_kick_out_vgacon(struct drm_i915_private * dev_priv)509 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
510 {
511 int ret = 0;
512
513 DRM_INFO("Replacing VGA console driver\n");
514
515 console_lock();
516 if (con_is_bound(&vga_con))
517 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
518 if (ret == 0) {
519 ret = do_unregister_con_driver(&vga_con);
520
521 /* Ignore "already unregistered". */
522 if (ret == -ENODEV)
523 ret = 0;
524 }
525 console_unlock();
526
527 return ret;
528 }
529 #endif
530
i915_dump_device_info(struct drm_i915_private * dev_priv)531 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
532 {
533 const struct intel_device_info *info = &dev_priv->info;
534
535 #define PRINT_S(name) "%s"
536 #define SEP_EMPTY
537 #define PRINT_FLAG(name) info->name ? #name "," : ""
538 #define SEP_COMMA ,
539 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
540 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
541 info->gen,
542 dev_priv->dev->pdev->device,
543 dev_priv->dev->pdev->revision,
544 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
545 #undef PRINT_S
546 #undef SEP_EMPTY
547 #undef PRINT_FLAG
548 #undef SEP_COMMA
549 }
550
cherryview_sseu_info_init(struct drm_device * dev)551 static void cherryview_sseu_info_init(struct drm_device *dev)
552 {
553 struct drm_i915_private *dev_priv = dev->dev_private;
554 struct intel_device_info *info;
555 u32 fuse, eu_dis;
556
557 info = (struct intel_device_info *)&dev_priv->info;
558 fuse = I915_READ(CHV_FUSE_GT);
559
560 info->slice_total = 1;
561
562 if (!(fuse & CHV_FGT_DISABLE_SS0)) {
563 info->subslice_per_slice++;
564 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
565 CHV_FGT_EU_DIS_SS0_R1_MASK);
566 info->eu_total += 8 - hweight32(eu_dis);
567 }
568
569 if (!(fuse & CHV_FGT_DISABLE_SS1)) {
570 info->subslice_per_slice++;
571 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
572 CHV_FGT_EU_DIS_SS1_R1_MASK);
573 info->eu_total += 8 - hweight32(eu_dis);
574 }
575
576 info->subslice_total = info->subslice_per_slice;
577 /*
578 * CHV expected to always have a uniform distribution of EU
579 * across subslices.
580 */
581 info->eu_per_subslice = info->subslice_total ?
582 info->eu_total / info->subslice_total :
583 0;
584 /*
585 * CHV supports subslice power gating on devices with more than
586 * one subslice, and supports EU power gating on devices with
587 * more than one EU pair per subslice.
588 */
589 info->has_slice_pg = 0;
590 info->has_subslice_pg = (info->subslice_total > 1);
591 info->has_eu_pg = (info->eu_per_subslice > 2);
592 }
593
gen9_sseu_info_init(struct drm_device * dev)594 static void gen9_sseu_info_init(struct drm_device *dev)
595 {
596 struct drm_i915_private *dev_priv = dev->dev_private;
597 struct intel_device_info *info;
598 int s_max = 3, ss_max = 4, eu_max = 8;
599 int s, ss;
600 u32 fuse2, s_enable, ss_disable, eu_disable;
601 u8 eu_mask = 0xff;
602
603 info = (struct intel_device_info *)&dev_priv->info;
604 fuse2 = I915_READ(GEN8_FUSE2);
605 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
606 GEN8_F2_S_ENA_SHIFT;
607 ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
608 GEN9_F2_SS_DIS_SHIFT;
609
610 info->slice_total = hweight32(s_enable);
611 /*
612 * The subslice disable field is global, i.e. it applies
613 * to each of the enabled slices.
614 */
615 info->subslice_per_slice = ss_max - hweight32(ss_disable);
616 info->subslice_total = info->slice_total *
617 info->subslice_per_slice;
618
619 /*
620 * Iterate through enabled slices and subslices to
621 * count the total enabled EU.
622 */
623 for (s = 0; s < s_max; s++) {
624 if (!(s_enable & (0x1 << s)))
625 /* skip disabled slice */
626 continue;
627
628 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
629 for (ss = 0; ss < ss_max; ss++) {
630 int eu_per_ss;
631
632 if (ss_disable & (0x1 << ss))
633 /* skip disabled subslice */
634 continue;
635
636 eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
637 eu_mask);
638
639 /*
640 * Record which subslice(s) has(have) 7 EUs. we
641 * can tune the hash used to spread work among
642 * subslices if they are unbalanced.
643 */
644 if (eu_per_ss == 7)
645 info->subslice_7eu[s] |= 1 << ss;
646
647 info->eu_total += eu_per_ss;
648 }
649 }
650
651 /*
652 * SKL is expected to always have a uniform distribution
653 * of EU across subslices with the exception that any one
654 * EU in any one subslice may be fused off for die
655 * recovery. BXT is expected to be perfectly uniform in EU
656 * distribution.
657 */
658 info->eu_per_subslice = info->subslice_total ?
659 DIV_ROUND_UP(info->eu_total,
660 info->subslice_total) : 0;
661 /*
662 * SKL supports slice power gating on devices with more than
663 * one slice, and supports EU power gating on devices with
664 * more than one EU pair per subslice. BXT supports subslice
665 * power gating on devices with more than one subslice, and
666 * supports EU power gating on devices with more than one EU
667 * pair per subslice.
668 */
669 info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1));
670 info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
671 info->has_eu_pg = (info->eu_per_subslice > 2);
672 }
673
broadwell_sseu_info_init(struct drm_device * dev)674 static void broadwell_sseu_info_init(struct drm_device *dev)
675 {
676 struct drm_i915_private *dev_priv = dev->dev_private;
677 struct intel_device_info *info;
678 const int s_max = 3, ss_max = 3, eu_max = 8;
679 int s, ss;
680 u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
681
682 fuse2 = I915_READ(GEN8_FUSE2);
683 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
684 ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
685
686 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
687 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
688 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
689 (32 - GEN8_EU_DIS0_S1_SHIFT));
690 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
691 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
692 (32 - GEN8_EU_DIS1_S2_SHIFT));
693
694
695 info = (struct intel_device_info *)&dev_priv->info;
696 info->slice_total = hweight32(s_enable);
697
698 /*
699 * The subslice disable field is global, i.e. it applies
700 * to each of the enabled slices.
701 */
702 info->subslice_per_slice = ss_max - hweight32(ss_disable);
703 info->subslice_total = info->slice_total * info->subslice_per_slice;
704
705 /*
706 * Iterate through enabled slices and subslices to
707 * count the total enabled EU.
708 */
709 for (s = 0; s < s_max; s++) {
710 if (!(s_enable & (0x1 << s)))
711 /* skip disabled slice */
712 continue;
713
714 for (ss = 0; ss < ss_max; ss++) {
715 u32 n_disabled;
716
717 if (ss_disable & (0x1 << ss))
718 /* skip disabled subslice */
719 continue;
720
721 n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
722
723 /*
724 * Record which subslices have 7 EUs.
725 */
726 if (eu_max - n_disabled == 7)
727 info->subslice_7eu[s] |= 1 << ss;
728
729 info->eu_total += eu_max - n_disabled;
730 }
731 }
732
733 /*
734 * BDW is expected to always have a uniform distribution of EU across
735 * subslices with the exception that any one EU in any one subslice may
736 * be fused off for die recovery.
737 */
738 info->eu_per_subslice = info->subslice_total ?
739 DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
740
741 /*
742 * BDW supports slice power gating on devices with more than
743 * one slice.
744 */
745 info->has_slice_pg = (info->slice_total > 1);
746 info->has_subslice_pg = 0;
747 info->has_eu_pg = 0;
748 }
749
750 /*
751 * Determine various intel_device_info fields at runtime.
752 *
753 * Use it when either:
754 * - it's judged too laborious to fill n static structures with the limit
755 * when a simple if statement does the job,
756 * - run-time checks (eg read fuse/strap registers) are needed.
757 *
758 * This function needs to be called:
759 * - after the MMIO has been setup as we are reading registers,
760 * - after the PCH has been detected,
761 * - before the first usage of the fields it can tweak.
762 */
intel_device_info_runtime_init(struct drm_device * dev)763 static void intel_device_info_runtime_init(struct drm_device *dev)
764 {
765 struct drm_i915_private *dev_priv = dev->dev_private;
766 struct intel_device_info *info;
767 enum pipe pipe;
768
769 info = (struct intel_device_info *)&dev_priv->info;
770
771 /*
772 * Skylake and Broxton currently don't expose the topmost plane as its
773 * use is exclusive with the legacy cursor and we only want to expose
774 * one of those, not both. Until we can safely expose the topmost plane
775 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
776 * we don't expose the topmost plane at all to prevent ABI breakage
777 * down the line.
778 */
779 if (IS_BROXTON(dev)) {
780 info->num_sprites[PIPE_A] = 2;
781 info->num_sprites[PIPE_B] = 2;
782 info->num_sprites[PIPE_C] = 1;
783 } else if (IS_VALLEYVIEW(dev))
784 for_each_pipe(dev_priv, pipe)
785 info->num_sprites[pipe] = 2;
786 else
787 for_each_pipe(dev_priv, pipe)
788 info->num_sprites[pipe] = 1;
789
790 if (i915.disable_display) {
791 DRM_INFO("Display disabled (module parameter)\n");
792 info->num_pipes = 0;
793 } else if (info->num_pipes > 0 &&
794 (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
795 !IS_VALLEYVIEW(dev)) {
796 u32 fuse_strap = I915_READ(FUSE_STRAP);
797 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
798
799 /*
800 * SFUSE_STRAP is supposed to have a bit signalling the display
801 * is fused off. Unfortunately it seems that, at least in
802 * certain cases, fused off display means that PCH display
803 * reads don't land anywhere. In that case, we read 0s.
804 *
805 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
806 * should be set when taking over after the firmware.
807 */
808 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
809 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
810 (dev_priv->pch_type == PCH_CPT &&
811 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
812 DRM_INFO("Display fused off, disabling\n");
813 info->num_pipes = 0;
814 }
815 }
816
817 /* Initialize slice/subslice/EU info */
818 if (IS_CHERRYVIEW(dev))
819 cherryview_sseu_info_init(dev);
820 else if (IS_BROADWELL(dev))
821 broadwell_sseu_info_init(dev);
822 else if (INTEL_INFO(dev)->gen >= 9)
823 gen9_sseu_info_init(dev);
824
825 DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
826 DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
827 DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
828 DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
829 DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
830 DRM_DEBUG_DRIVER("has slice power gating: %s\n",
831 info->has_slice_pg ? "y" : "n");
832 DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
833 info->has_subslice_pg ? "y" : "n");
834 DRM_DEBUG_DRIVER("has EU power gating: %s\n",
835 info->has_eu_pg ? "y" : "n");
836 }
837
intel_init_dpio(struct drm_i915_private * dev_priv)838 static void intel_init_dpio(struct drm_i915_private *dev_priv)
839 {
840 if (!IS_VALLEYVIEW(dev_priv))
841 return;
842
843 /*
844 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
845 * CHV x1 PHY (DP/HDMI D)
846 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
847 */
848 if (IS_CHERRYVIEW(dev_priv)) {
849 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
850 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
851 } else {
852 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
853 }
854 }
855
856 /**
857 * i915_driver_load - setup chip and create an initial config
858 * @dev: DRM device
859 * @flags: startup flags
860 *
861 * The driver load routine has to do several things:
862 * - drive output discovery via intel_modeset_init()
863 * - initialize the memory manager
864 * - allocate initial config memory
865 * - setup the DRM framebuffer with the allocated memory
866 */
i915_driver_load(struct drm_device * dev,unsigned long flags)867 int i915_driver_load(struct drm_device *dev, unsigned long flags)
868 {
869 struct drm_i915_private *dev_priv;
870 struct intel_device_info *info, *device_info;
871 int ret = 0, mmio_bar, mmio_size;
872 uint32_t aperture_size;
873
874 info = (struct intel_device_info *) flags;
875
876 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
877 if (dev_priv == NULL)
878 return -ENOMEM;
879
880 dev->dev_private = dev_priv;
881 dev_priv->dev = dev;
882
883 /* Setup the write-once "constant" device info */
884 device_info = (struct intel_device_info *)&dev_priv->info;
885 memcpy(device_info, info, sizeof(dev_priv->info));
886 device_info->device_id = dev->pdev->device;
887
888 spin_lock_init(&dev_priv->irq_lock);
889 spin_lock_init(&dev_priv->gpu_error.lock);
890 mutex_init(&dev_priv->backlight_lock);
891 spin_lock_init(&dev_priv->uncore.lock);
892 spin_lock_init(&dev_priv->mm.object_stat_lock);
893 spin_lock_init(&dev_priv->mmio_flip_lock);
894 mutex_init(&dev_priv->sb_lock);
895 mutex_init(&dev_priv->modeset_restore_lock);
896 mutex_init(&dev_priv->csr_lock);
897 mutex_init(&dev_priv->av_mutex);
898
899 intel_pm_setup(dev);
900
901 intel_display_crc_init(dev);
902
903 i915_dump_device_info(dev_priv);
904
905 /* Not all pre-production machines fall into this category, only the
906 * very first ones. Almost everything should work, except for maybe
907 * suspend/resume. And we don't implement workarounds that affect only
908 * pre-production machines. */
909 if (IS_HSW_EARLY_SDV(dev))
910 DRM_INFO("This is an early pre-production Haswell machine. "
911 "It may not be fully functional.\n");
912
913 if (i915_get_bridge_dev(dev)) {
914 ret = -EIO;
915 goto free_priv;
916 }
917
918 mmio_bar = IS_GEN2(dev) ? 1 : 0;
919 /* Before gen4, the registers and the GTT are behind different BARs.
920 * However, from gen4 onwards, the registers and the GTT are shared
921 * in the same BAR, so we want to restrict this ioremap from
922 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
923 * the register BAR remains the same size for all the earlier
924 * generations up to Ironlake.
925 */
926 if (info->gen < 5)
927 mmio_size = 512*1024;
928 else
929 mmio_size = 2*1024*1024;
930
931 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
932 if (!dev_priv->regs) {
933 DRM_ERROR("failed to map registers\n");
934 ret = -EIO;
935 goto put_bridge;
936 }
937
938 /* This must be called before any calls to HAS_PCH_* */
939 intel_detect_pch(dev);
940
941 intel_uncore_init(dev);
942
943 /* Load CSR Firmware for SKL */
944 intel_csr_ucode_init(dev);
945
946 ret = i915_gem_gtt_init(dev);
947 if (ret)
948 goto out_freecsr;
949
950 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
951 * otherwise the vga fbdev driver falls over. */
952 ret = i915_kick_out_firmware_fb(dev_priv);
953 if (ret) {
954 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
955 goto out_gtt;
956 }
957
958 ret = i915_kick_out_vgacon(dev_priv);
959 if (ret) {
960 DRM_ERROR("failed to remove conflicting VGA console\n");
961 goto out_gtt;
962 }
963
964 pci_set_master(dev->pdev);
965
966 /* overlay on gen2 is broken and can't address above 1G */
967 if (IS_GEN2(dev))
968 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
969
970 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
971 * using 32bit addressing, overwriting memory if HWS is located
972 * above 4GB.
973 *
974 * The documentation also mentions an issue with undefined
975 * behaviour if any general state is accessed within a page above 4GB,
976 * which also needs to be handled carefully.
977 */
978 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
979 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
980
981 aperture_size = dev_priv->gtt.mappable_end;
982
983 dev_priv->gtt.mappable =
984 io_mapping_create_wc(dev_priv->gtt.mappable_base,
985 aperture_size);
986 if (dev_priv->gtt.mappable == NULL) {
987 ret = -EIO;
988 goto out_gtt;
989 }
990
991 dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
992 aperture_size);
993
994 /* The i915 workqueue is primarily used for batched retirement of
995 * requests (and thus managing bo) once the task has been completed
996 * by the GPU. i915_gem_retire_requests() is called directly when we
997 * need high-priority retirement, such as waiting for an explicit
998 * bo.
999 *
1000 * It is also used for periodic low-priority events, such as
1001 * idle-timers and recording error state.
1002 *
1003 * All tasks on the workqueue are expected to acquire the dev mutex
1004 * so there is no point in running more than one instance of the
1005 * workqueue at any time. Use an ordered one.
1006 */
1007 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1008 if (dev_priv->wq == NULL) {
1009 DRM_ERROR("Failed to create our workqueue.\n");
1010 ret = -ENOMEM;
1011 goto out_mtrrfree;
1012 }
1013
1014 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1015 if (dev_priv->hotplug.dp_wq == NULL) {
1016 DRM_ERROR("Failed to create our dp workqueue.\n");
1017 ret = -ENOMEM;
1018 goto out_freewq;
1019 }
1020
1021 dev_priv->gpu_error.hangcheck_wq =
1022 alloc_ordered_workqueue("i915-hangcheck", 0);
1023 if (dev_priv->gpu_error.hangcheck_wq == NULL) {
1024 DRM_ERROR("Failed to create our hangcheck workqueue.\n");
1025 ret = -ENOMEM;
1026 goto out_freedpwq;
1027 }
1028
1029 intel_irq_init(dev_priv);
1030 intel_uncore_sanitize(dev);
1031
1032 /* Try to make sure MCHBAR is enabled before poking at it */
1033 intel_setup_mchbar(dev);
1034 intel_opregion_setup(dev);
1035
1036 i915_gem_load(dev);
1037
1038 /* On the 945G/GM, the chipset reports the MSI capability on the
1039 * integrated graphics even though the support isn't actually there
1040 * according to the published specs. It doesn't appear to function
1041 * correctly in testing on 945G.
1042 * This may be a side effect of MSI having been made available for PEG
1043 * and the registers being closely associated.
1044 *
1045 * According to chipset errata, on the 965GM, MSI interrupts may
1046 * be lost or delayed, but we use them anyways to avoid
1047 * stuck interrupts on some machines.
1048 */
1049 if (!IS_I945G(dev) && !IS_I945GM(dev))
1050 pci_enable_msi(dev->pdev);
1051
1052 intel_device_info_runtime_init(dev);
1053
1054 intel_init_dpio(dev_priv);
1055
1056 if (INTEL_INFO(dev)->num_pipes) {
1057 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1058 if (ret)
1059 goto out_gem_unload;
1060 }
1061
1062 intel_power_domains_init(dev_priv);
1063
1064 ret = i915_load_modeset_init(dev);
1065 if (ret < 0) {
1066 DRM_ERROR("failed to init modeset\n");
1067 goto out_power_well;
1068 }
1069
1070 /*
1071 * Notify a valid surface after modesetting,
1072 * when running inside a VM.
1073 */
1074 if (intel_vgpu_active(dev))
1075 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1076
1077 i915_setup_sysfs(dev);
1078
1079 if (INTEL_INFO(dev)->num_pipes) {
1080 /* Must be done after probing outputs */
1081 intel_opregion_init(dev);
1082 acpi_video_register();
1083 }
1084
1085 if (IS_GEN5(dev))
1086 intel_gpu_ips_init(dev_priv);
1087
1088 intel_runtime_pm_enable(dev_priv);
1089
1090 i915_audio_component_init(dev_priv);
1091
1092 return 0;
1093
1094 out_power_well:
1095 intel_power_domains_fini(dev_priv);
1096 drm_vblank_cleanup(dev);
1097 out_gem_unload:
1098 WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1099 unregister_shrinker(&dev_priv->mm.shrinker);
1100
1101 if (dev->pdev->msi_enabled)
1102 pci_disable_msi(dev->pdev);
1103
1104 intel_teardown_mchbar(dev);
1105 pm_qos_remove_request(&dev_priv->pm_qos);
1106 destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1107 out_freedpwq:
1108 destroy_workqueue(dev_priv->hotplug.dp_wq);
1109 out_freewq:
1110 destroy_workqueue(dev_priv->wq);
1111 out_mtrrfree:
1112 arch_phys_wc_del(dev_priv->gtt.mtrr);
1113 io_mapping_free(dev_priv->gtt.mappable);
1114 out_gtt:
1115 i915_global_gtt_cleanup(dev);
1116 out_freecsr:
1117 intel_csr_ucode_fini(dev);
1118 intel_uncore_fini(dev);
1119 pci_iounmap(dev->pdev, dev_priv->regs);
1120 put_bridge:
1121 pci_dev_put(dev_priv->bridge_dev);
1122 free_priv:
1123 kmem_cache_destroy(dev_priv->requests);
1124 kmem_cache_destroy(dev_priv->vmas);
1125 kmem_cache_destroy(dev_priv->objects);
1126 kfree(dev_priv);
1127 return ret;
1128 }
1129
i915_driver_unload(struct drm_device * dev)1130 int i915_driver_unload(struct drm_device *dev)
1131 {
1132 struct drm_i915_private *dev_priv = dev->dev_private;
1133 int ret;
1134
1135 i915_audio_component_cleanup(dev_priv);
1136
1137 ret = i915_gem_suspend(dev);
1138 if (ret) {
1139 DRM_ERROR("failed to idle hardware: %d\n", ret);
1140 return ret;
1141 }
1142
1143 intel_power_domains_fini(dev_priv);
1144
1145 intel_gpu_ips_teardown();
1146
1147 i915_teardown_sysfs(dev);
1148
1149 WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1150 unregister_shrinker(&dev_priv->mm.shrinker);
1151
1152 io_mapping_free(dev_priv->gtt.mappable);
1153 arch_phys_wc_del(dev_priv->gtt.mtrr);
1154
1155 acpi_video_unregister();
1156
1157 intel_fbdev_fini(dev);
1158
1159 drm_vblank_cleanup(dev);
1160
1161 intel_modeset_cleanup(dev);
1162
1163 /*
1164 * free the memory space allocated for the child device
1165 * config parsed from VBT
1166 */
1167 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1168 kfree(dev_priv->vbt.child_dev);
1169 dev_priv->vbt.child_dev = NULL;
1170 dev_priv->vbt.child_dev_num = 0;
1171 }
1172 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1173 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1174 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1175 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1176
1177 vga_switcheroo_unregister_client(dev->pdev);
1178 vga_client_register(dev->pdev, NULL, NULL, NULL);
1179
1180 /* Free error state after interrupts are fully disabled. */
1181 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1182 i915_destroy_error_state(dev);
1183
1184 if (dev->pdev->msi_enabled)
1185 pci_disable_msi(dev->pdev);
1186
1187 intel_opregion_fini(dev);
1188
1189 /* Flush any outstanding unpin_work. */
1190 flush_workqueue(dev_priv->wq);
1191
1192 intel_guc_ucode_fini(dev);
1193 mutex_lock(&dev->struct_mutex);
1194 i915_gem_cleanup_ringbuffer(dev);
1195 i915_gem_context_fini(dev);
1196 mutex_unlock(&dev->struct_mutex);
1197 intel_fbc_cleanup_cfb(dev_priv);
1198 i915_gem_cleanup_stolen(dev);
1199
1200 intel_csr_ucode_fini(dev);
1201
1202 intel_teardown_mchbar(dev);
1203
1204 destroy_workqueue(dev_priv->hotplug.dp_wq);
1205 destroy_workqueue(dev_priv->wq);
1206 destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1207 pm_qos_remove_request(&dev_priv->pm_qos);
1208
1209 i915_global_gtt_cleanup(dev);
1210
1211 intel_uncore_fini(dev);
1212 if (dev_priv->regs != NULL)
1213 pci_iounmap(dev->pdev, dev_priv->regs);
1214
1215 kmem_cache_destroy(dev_priv->requests);
1216 kmem_cache_destroy(dev_priv->vmas);
1217 kmem_cache_destroy(dev_priv->objects);
1218 pci_dev_put(dev_priv->bridge_dev);
1219 kfree(dev_priv);
1220
1221 return 0;
1222 }
1223
i915_driver_open(struct drm_device * dev,struct drm_file * file)1224 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1225 {
1226 int ret;
1227
1228 ret = i915_gem_open(dev, file);
1229 if (ret)
1230 return ret;
1231
1232 return 0;
1233 }
1234
1235 /**
1236 * i915_driver_lastclose - clean up after all DRM clients have exited
1237 * @dev: DRM device
1238 *
1239 * Take care of cleaning up after all DRM clients have exited. In the
1240 * mode setting case, we want to restore the kernel's initial mode (just
1241 * in case the last client left us in a bad state).
1242 *
1243 * Additionally, in the non-mode setting case, we'll tear down the GTT
1244 * and DMA structures, since the kernel won't be using them, and clea
1245 * up any GEM state.
1246 */
i915_driver_lastclose(struct drm_device * dev)1247 void i915_driver_lastclose(struct drm_device *dev)
1248 {
1249 intel_fbdev_restore_mode(dev);
1250 vga_switcheroo_process_delayed_switch();
1251 }
1252
i915_driver_preclose(struct drm_device * dev,struct drm_file * file)1253 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1254 {
1255 mutex_lock(&dev->struct_mutex);
1256 i915_gem_context_close(dev, file);
1257 i915_gem_release(dev, file);
1258 mutex_unlock(&dev->struct_mutex);
1259
1260 intel_modeset_preclose(dev, file);
1261 }
1262
i915_driver_postclose(struct drm_device * dev,struct drm_file * file)1263 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1264 {
1265 struct drm_i915_file_private *file_priv = file->driver_priv;
1266
1267 if (file_priv && file_priv->bsd_ring)
1268 file_priv->bsd_ring = NULL;
1269 kfree(file_priv);
1270 }
1271
1272 static int
i915_gem_reject_pin_ioctl(struct drm_device * dev,void * data,struct drm_file * file)1273 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1274 struct drm_file *file)
1275 {
1276 return -ENODEV;
1277 }
1278
1279 const struct drm_ioctl_desc i915_ioctls[] = {
1280 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1281 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1282 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1283 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1284 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1285 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1286 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1287 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1288 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1289 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1290 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1291 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1292 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1293 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1294 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1295 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1296 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1297 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1298 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1299 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
1300 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1301 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1302 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1303 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1304 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1305 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1306 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1307 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1308 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1309 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1310 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1311 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1312 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
1313 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1314 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1315 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
1316 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
1317 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1318 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1319 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1320 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW),
1321 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW),
1322 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
1323 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
1324 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1325 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1326 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1327 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1328 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_RENDER_ALLOW),
1329 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1330 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1331 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1332 };
1333
1334 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
1335