1 #ifndef _ASM_X86_INSN_H
2 #define _ASM_X86_INSN_H
3 /*
4 * x86 instruction analysis
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 * Copyright (C) IBM Corporation, 2009
21 */
22
23 /* insn_attr_t is defined in inat.h */
24 #include <asm/inat.h>
25
26 struct insn_field {
27 union {
28 insn_value_t value;
29 insn_byte_t bytes[4];
30 };
31 /* !0 if we've run insn_get_xxx() for this field */
32 unsigned char got;
33 unsigned char nbytes;
34 };
35
36 struct insn {
37 struct insn_field prefixes; /*
38 * Prefixes
39 * prefixes.bytes[3]: last prefix
40 */
41 struct insn_field rex_prefix; /* REX prefix */
42 struct insn_field vex_prefix; /* VEX prefix */
43 struct insn_field opcode; /*
44 * opcode.bytes[0]: opcode1
45 * opcode.bytes[1]: opcode2
46 * opcode.bytes[2]: opcode3
47 */
48 struct insn_field modrm;
49 struct insn_field sib;
50 struct insn_field displacement;
51 union {
52 struct insn_field immediate;
53 struct insn_field moffset1; /* for 64bit MOV */
54 struct insn_field immediate1; /* for 64bit imm or off16/32 */
55 };
56 union {
57 struct insn_field moffset2; /* for 64bit MOV */
58 struct insn_field immediate2; /* for 64bit imm or seg16 */
59 };
60
61 insn_attr_t attr;
62 unsigned char opnd_bytes;
63 unsigned char addr_bytes;
64 unsigned char length;
65 unsigned char x86_64;
66
67 const insn_byte_t *kaddr; /* kernel address of insn to analyze */
68 const insn_byte_t *end_kaddr; /* kernel address of last insn in buffer */
69 const insn_byte_t *next_byte;
70 };
71
72 #define MAX_INSN_SIZE 15
73
74 #define X86_MODRM_MOD(modrm) (((modrm) & 0xc0) >> 6)
75 #define X86_MODRM_REG(modrm) (((modrm) & 0x38) >> 3)
76 #define X86_MODRM_RM(modrm) ((modrm) & 0x07)
77
78 #define X86_SIB_SCALE(sib) (((sib) & 0xc0) >> 6)
79 #define X86_SIB_INDEX(sib) (((sib) & 0x38) >> 3)
80 #define X86_SIB_BASE(sib) ((sib) & 0x07)
81
82 #define X86_REX_W(rex) ((rex) & 8)
83 #define X86_REX_R(rex) ((rex) & 4)
84 #define X86_REX_X(rex) ((rex) & 2)
85 #define X86_REX_B(rex) ((rex) & 1)
86
87 /* VEX bit flags */
88 #define X86_VEX_W(vex) ((vex) & 0x80) /* VEX3 Byte2 */
89 #define X86_VEX_R(vex) ((vex) & 0x80) /* VEX2/3 Byte1 */
90 #define X86_VEX_X(vex) ((vex) & 0x40) /* VEX3 Byte1 */
91 #define X86_VEX_B(vex) ((vex) & 0x20) /* VEX3 Byte1 */
92 #define X86_VEX_L(vex) ((vex) & 0x04) /* VEX3 Byte2, VEX2 Byte1 */
93 /* VEX bit fields */
94 #define X86_VEX3_M(vex) ((vex) & 0x1f) /* VEX3 Byte1 */
95 #define X86_VEX2_M 1 /* VEX2.M always 1 */
96 #define X86_VEX_V(vex) (((vex) & 0x78) >> 3) /* VEX3 Byte2, VEX2 Byte1 */
97 #define X86_VEX_P(vex) ((vex) & 0x03) /* VEX3 Byte2, VEX2 Byte1 */
98 #define X86_VEX_M_MAX 0x1f /* VEX3.M Maximum value */
99
100 extern void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64);
101 extern void insn_get_prefixes(struct insn *insn);
102 extern void insn_get_opcode(struct insn *insn);
103 extern void insn_get_modrm(struct insn *insn);
104 extern void insn_get_sib(struct insn *insn);
105 extern void insn_get_displacement(struct insn *insn);
106 extern void insn_get_immediate(struct insn *insn);
107 extern void insn_get_length(struct insn *insn);
108
109 /* Attribute will be determined after getting ModRM (for opcode groups) */
insn_get_attribute(struct insn * insn)110 static inline void insn_get_attribute(struct insn *insn)
111 {
112 insn_get_modrm(insn);
113 }
114
115 /* Instruction uses RIP-relative addressing */
116 extern int insn_rip_relative(struct insn *insn);
117
118 /* Init insn for kernel text */
kernel_insn_init(struct insn * insn,const void * kaddr,int buf_len)119 static inline void kernel_insn_init(struct insn *insn,
120 const void *kaddr, int buf_len)
121 {
122 #ifdef CONFIG_X86_64
123 insn_init(insn, kaddr, buf_len, 1);
124 #else /* CONFIG_X86_32 */
125 insn_init(insn, kaddr, buf_len, 0);
126 #endif
127 }
128
insn_is_avx(struct insn * insn)129 static inline int insn_is_avx(struct insn *insn)
130 {
131 if (!insn->prefixes.got)
132 insn_get_prefixes(insn);
133 return (insn->vex_prefix.value != 0);
134 }
135
136 /* Ensure this instruction is decoded completely */
insn_complete(struct insn * insn)137 static inline int insn_complete(struct insn *insn)
138 {
139 return insn->opcode.got && insn->modrm.got && insn->sib.got &&
140 insn->displacement.got && insn->immediate.got;
141 }
142
insn_vex_m_bits(struct insn * insn)143 static inline insn_byte_t insn_vex_m_bits(struct insn *insn)
144 {
145 if (insn->vex_prefix.nbytes == 2) /* 2 bytes VEX */
146 return X86_VEX2_M;
147 else
148 return X86_VEX3_M(insn->vex_prefix.bytes[1]);
149 }
150
insn_vex_p_bits(struct insn * insn)151 static inline insn_byte_t insn_vex_p_bits(struct insn *insn)
152 {
153 if (insn->vex_prefix.nbytes == 2) /* 2 bytes VEX */
154 return X86_VEX_P(insn->vex_prefix.bytes[1]);
155 else
156 return X86_VEX_P(insn->vex_prefix.bytes[2]);
157 }
158
159 /* Get the last prefix id from last prefix or VEX prefix */
insn_last_prefix_id(struct insn * insn)160 static inline int insn_last_prefix_id(struct insn *insn)
161 {
162 if (insn_is_avx(insn))
163 return insn_vex_p_bits(insn); /* VEX_p is a SIMD prefix id */
164
165 if (insn->prefixes.bytes[3])
166 return inat_get_last_prefix_id(insn->prefixes.bytes[3]);
167
168 return 0;
169 }
170
171 /* Offset of each field from kaddr */
insn_offset_rex_prefix(struct insn * insn)172 static inline int insn_offset_rex_prefix(struct insn *insn)
173 {
174 return insn->prefixes.nbytes;
175 }
insn_offset_vex_prefix(struct insn * insn)176 static inline int insn_offset_vex_prefix(struct insn *insn)
177 {
178 return insn_offset_rex_prefix(insn) + insn->rex_prefix.nbytes;
179 }
insn_offset_opcode(struct insn * insn)180 static inline int insn_offset_opcode(struct insn *insn)
181 {
182 return insn_offset_vex_prefix(insn) + insn->vex_prefix.nbytes;
183 }
insn_offset_modrm(struct insn * insn)184 static inline int insn_offset_modrm(struct insn *insn)
185 {
186 return insn_offset_opcode(insn) + insn->opcode.nbytes;
187 }
insn_offset_sib(struct insn * insn)188 static inline int insn_offset_sib(struct insn *insn)
189 {
190 return insn_offset_modrm(insn) + insn->modrm.nbytes;
191 }
insn_offset_displacement(struct insn * insn)192 static inline int insn_offset_displacement(struct insn *insn)
193 {
194 return insn_offset_sib(insn) + insn->sib.nbytes;
195 }
insn_offset_immediate(struct insn * insn)196 static inline int insn_offset_immediate(struct insn *insn)
197 {
198 return insn_offset_displacement(insn) + insn->displacement.nbytes;
199 }
200
201 /**
202 * for_each_insn_prefix() -- Iterate prefixes in the instruction
203 * @insn: Pointer to struct insn.
204 * @idx: Index storage.
205 * @prefix: Prefix byte.
206 *
207 * Iterate prefix bytes of given @insn. Each prefix byte is stored in @prefix
208 * and the index is stored in @idx (note that this @idx is just for a cursor,
209 * do not change it.)
210 * Since prefixes.nbytes can be bigger than 4 if some prefixes
211 * are repeated, it cannot be used for looping over the prefixes.
212 */
213 #define for_each_insn_prefix(insn, idx, prefix) \
214 for (idx = 0; idx < ARRAY_SIZE(insn->prefixes.bytes) && (prefix = insn->prefixes.bytes[idx]) != 0; idx++)
215
216 #define POP_SS_OPCODE 0x1f
217 #define MOV_SREG_OPCODE 0x8e
218
219 /*
220 * Intel SDM Vol.3A 6.8.3 states;
221 * "Any single-step trap that would be delivered following the MOV to SS
222 * instruction or POP to SS instruction (because EFLAGS.TF is 1) is
223 * suppressed."
224 * This function returns true if @insn is MOV SS or POP SS. On these
225 * instructions, single stepping is suppressed.
226 */
insn_masking_exception(struct insn * insn)227 static inline int insn_masking_exception(struct insn *insn)
228 {
229 return insn->opcode.bytes[0] == POP_SS_OPCODE ||
230 (insn->opcode.bytes[0] == MOV_SREG_OPCODE &&
231 X86_MODRM_REG(insn->modrm.bytes[0]) == 2);
232 }
233
234 #endif /* _ASM_X86_INSN_H */
235