1 /*
2 * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/regmap.h>
18 #include "common.h"
19 #include "hardware.h"
20
21 #define REG_SET 0x4
22 #define REG_CLR 0x8
23
24 #define ANADIG_REG_2P5 0x130
25 #define ANADIG_REG_CORE 0x140
26 #define ANADIG_ANA_MISC0 0x150
27 #define ANADIG_USB1_CHRG_DETECT 0x1b0
28 #define ANADIG_USB2_CHRG_DETECT 0x210
29 #define ANADIG_DIGPROG 0x260
30 #define ANADIG_DIGPROG_IMX6SL 0x280
31 #define ANADIG_DIGPROG_IMX7D 0x800
32
33 #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
34 #define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8
35 #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
36 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
37 /* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
38 #define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000
39 #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000
40 #define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000
41
42 static struct regmap *anatop;
43
imx_anatop_enable_weak2p5(bool enable)44 static void imx_anatop_enable_weak2p5(bool enable)
45 {
46 u32 reg, val;
47
48 regmap_read(anatop, ANADIG_ANA_MISC0, &val);
49
50 /* can only be enabled when stop_mode_config is clear. */
51 reg = ANADIG_REG_2P5;
52 reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ?
53 REG_SET : REG_CLR;
54 regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG);
55 }
56
imx_anatop_enable_fet_odrive(bool enable)57 static void imx_anatop_enable_fet_odrive(bool enable)
58 {
59 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR),
60 BM_ANADIG_REG_CORE_FET_ODRIVE);
61 }
62
imx_anatop_enable_2p5_pulldown(bool enable)63 static inline void imx_anatop_enable_2p5_pulldown(bool enable)
64 {
65 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR),
66 BM_ANADIG_REG_2P5_ENABLE_PULLDOWN);
67 }
68
imx_anatop_disconnect_high_snvs(bool enable)69 static inline void imx_anatop_disconnect_high_snvs(bool enable)
70 {
71 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR),
72 BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS);
73 }
74
imx_anatop_pre_suspend(void)75 void imx_anatop_pre_suspend(void)
76 {
77 if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
78 imx_anatop_enable_2p5_pulldown(true);
79 else
80 imx_anatop_enable_weak2p5(true);
81
82 imx_anatop_enable_fet_odrive(true);
83
84 if (cpu_is_imx6sl())
85 imx_anatop_disconnect_high_snvs(true);
86 }
87
imx_anatop_post_resume(void)88 void imx_anatop_post_resume(void)
89 {
90 if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
91 imx_anatop_enable_2p5_pulldown(false);
92 else
93 imx_anatop_enable_weak2p5(false);
94
95 imx_anatop_enable_fet_odrive(false);
96
97 if (cpu_is_imx6sl())
98 imx_anatop_disconnect_high_snvs(false);
99
100 }
101
imx_anatop_usb_chrg_detect_disable(void)102 static void imx_anatop_usb_chrg_detect_disable(void)
103 {
104 regmap_write(anatop, ANADIG_USB1_CHRG_DETECT,
105 BM_ANADIG_USB_CHRG_DETECT_EN_B
106 | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
107 regmap_write(anatop, ANADIG_USB2_CHRG_DETECT,
108 BM_ANADIG_USB_CHRG_DETECT_EN_B |
109 BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
110 }
111
imx_init_revision_from_anatop(void)112 void __init imx_init_revision_from_anatop(void)
113 {
114 struct device_node *np;
115 void __iomem *anatop_base;
116 unsigned int revision;
117 u32 digprog;
118 u16 offset = ANADIG_DIGPROG;
119
120 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
121 anatop_base = of_iomap(np, 0);
122 WARN_ON(!anatop_base);
123 if (of_device_is_compatible(np, "fsl,imx6sl-anatop"))
124 offset = ANADIG_DIGPROG_IMX6SL;
125 if (of_device_is_compatible(np, "fsl,imx7d-anatop"))
126 offset = ANADIG_DIGPROG_IMX7D;
127 digprog = readl_relaxed(anatop_base + offset);
128 iounmap(anatop_base);
129
130 switch (digprog & 0xff) {
131 case 0:
132 revision = IMX_CHIP_REVISION_1_0;
133 break;
134 case 1:
135 revision = IMX_CHIP_REVISION_1_1;
136 break;
137 case 2:
138 revision = IMX_CHIP_REVISION_1_2;
139 break;
140 case 3:
141 revision = IMX_CHIP_REVISION_1_3;
142 break;
143 case 4:
144 revision = IMX_CHIP_REVISION_1_4;
145 break;
146 case 5:
147 /*
148 * i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked
149 * as 'D' in Part Number last character.
150 */
151 revision = IMX_CHIP_REVISION_1_5;
152 break;
153 default:
154 revision = IMX_CHIP_REVISION_UNKNOWN;
155 }
156
157 mxc_set_cpu_type(digprog >> 16 & 0xff);
158 imx_set_soc_revision(revision);
159 }
160
imx_anatop_init(void)161 void __init imx_anatop_init(void)
162 {
163 anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
164 if (IS_ERR(anatop)) {
165 pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__);
166 return;
167 }
168
169 imx_anatop_usb_chrg_detect_disable();
170 }
171