1 #ifndef __POWERNV_PCI_H 2 #define __POWERNV_PCI_H 3 4 struct pci_dn; 5 6 enum pnv_phb_type { 7 PNV_PHB_P5IOC2 = 0, 8 PNV_PHB_IODA1 = 1, 9 PNV_PHB_IODA2 = 2, 10 }; 11 12 /* Precise PHB model for error management */ 13 enum pnv_phb_model { 14 PNV_PHB_MODEL_UNKNOWN, 15 PNV_PHB_MODEL_P5IOC2, 16 PNV_PHB_MODEL_P7IOC, 17 PNV_PHB_MODEL_PHB3, 18 }; 19 20 #define PNV_PCI_DIAG_BUF_SIZE 8192 21 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ 22 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ 23 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 24 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 25 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 26 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */ 27 28 /* Data associated with a PE, including IOMMU tracking etc.. */ 29 struct pnv_phb; 30 struct pnv_ioda_pe { 31 unsigned long flags; 32 struct pnv_phb *phb; 33 34 /* A PE can be associated with a single device or an 35 * entire bus (& children). In the former case, pdev 36 * is populated, in the later case, pbus is. 37 */ 38 #ifdef CONFIG_PCI_IOV 39 struct pci_dev *parent_dev; 40 #endif 41 struct pci_dev *pdev; 42 struct pci_bus *pbus; 43 44 /* Effective RID (device RID for a device PE and base bus 45 * RID with devfn 0 for a bus PE) 46 */ 47 unsigned int rid; 48 49 /* PE number */ 50 unsigned int pe_number; 51 52 /* "Weight" assigned to the PE for the sake of DMA resource 53 * allocations 54 */ 55 unsigned int dma_weight; 56 57 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 58 int tce32_seg; 59 int tce32_segcount; 60 struct iommu_table_group table_group; 61 62 /* 64-bit TCE bypass region */ 63 bool tce_bypass_enabled; 64 uint64_t tce_bypass_base; 65 66 /* MSIs. MVE index is identical for for 32 and 64 bit MSI 67 * and -1 if not supported. (It's actually identical to the 68 * PE number) 69 */ 70 int mve_number; 71 72 /* PEs in compound case */ 73 struct pnv_ioda_pe *master; 74 struct list_head slaves; 75 76 /* Link in list of PE#s */ 77 struct list_head dma_link; 78 struct list_head list; 79 }; 80 81 #define PNV_PHB_FLAG_EEH (1 << 0) 82 83 struct pnv_phb { 84 struct pci_controller *hose; 85 enum pnv_phb_type type; 86 enum pnv_phb_model model; 87 u64 hub_id; 88 u64 opal_id; 89 int flags; 90 void __iomem *regs; 91 int initialized; 92 spinlock_t lock; 93 94 #ifdef CONFIG_DEBUG_FS 95 int has_dbgfs; 96 struct dentry *dbgfs; 97 #endif 98 99 #ifdef CONFIG_PCI_MSI 100 unsigned int msi_base; 101 unsigned int msi32_support; 102 struct msi_bitmap msi_bmp; 103 #endif 104 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, 105 unsigned int hwirq, unsigned int virq, 106 unsigned int is_64, struct msi_msg *msg); 107 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); 108 void (*fixup_phb)(struct pci_controller *hose); 109 u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn); 110 int (*init_m64)(struct pnv_phb *phb); 111 void (*reserve_m64_pe)(struct pci_bus *bus, 112 unsigned long *pe_bitmap, bool all); 113 int (*pick_m64_pe)(struct pci_bus *bus, bool all); 114 int (*get_pe_state)(struct pnv_phb *phb, int pe_no); 115 void (*freeze_pe)(struct pnv_phb *phb, int pe_no); 116 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt); 117 118 union { 119 struct { 120 struct iommu_table iommu_table; 121 struct iommu_table_group table_group; 122 } p5ioc2; 123 124 struct { 125 /* Global bridge info */ 126 unsigned int total_pe; 127 unsigned int reserved_pe; 128 129 /* 32-bit MMIO window */ 130 unsigned int m32_size; 131 unsigned int m32_segsize; 132 unsigned int m32_pci_base; 133 134 /* 64-bit MMIO window */ 135 unsigned int m64_bar_idx; 136 unsigned long m64_size; 137 unsigned long m64_segsize; 138 unsigned long m64_base; 139 unsigned long m64_bar_alloc; 140 141 /* IO ports */ 142 unsigned int io_size; 143 unsigned int io_segsize; 144 unsigned int io_pci_base; 145 146 /* PE allocation bitmap */ 147 unsigned long *pe_alloc; 148 /* PE allocation mutex */ 149 struct mutex pe_alloc_mutex; 150 151 /* M32 & IO segment maps */ 152 unsigned int *m32_segmap; 153 unsigned int *io_segmap; 154 struct pnv_ioda_pe *pe_array; 155 156 /* IRQ chip */ 157 int irq_chip_init; 158 struct irq_chip irq_chip; 159 160 /* Sorted list of used PE's based 161 * on the sequence of creation 162 */ 163 struct list_head pe_list; 164 struct mutex pe_list_mutex; 165 166 /* Reverse map of PEs, will have to extend if 167 * we are to support more than 256 PEs, indexed 168 * bus { bus, devfn } 169 */ 170 unsigned char pe_rmap[0x10000]; 171 172 /* 32-bit TCE tables allocation */ 173 unsigned long tce32_count; 174 175 /* Total "weight" for the sake of DMA resources 176 * allocation 177 */ 178 unsigned int dma_weight; 179 unsigned int dma_pe_count; 180 181 /* Sorted list of used PE's, sorted at 182 * boot for resource allocation purposes 183 */ 184 struct list_head pe_dma_list; 185 186 /* TCE cache invalidate registers (physical and 187 * remapped) 188 */ 189 phys_addr_t tce_inval_reg_phys; 190 __be64 __iomem *tce_inval_reg; 191 } ioda; 192 }; 193 194 /* PHB and hub status structure */ 195 union { 196 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE]; 197 struct OpalIoP7IOCPhbErrorData p7ioc; 198 struct OpalIoPhb3ErrorData phb3; 199 struct OpalIoP7IOCErrorData hub_diag; 200 } diag; 201 202 }; 203 204 extern struct pci_ops pnv_pci_ops; 205 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 206 unsigned long uaddr, enum dma_data_direction direction, 207 struct dma_attrs *attrs); 208 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages); 209 extern int pnv_tce_xchg(struct iommu_table *tbl, long index, 210 unsigned long *hpa, enum dma_data_direction *direction); 211 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index); 212 213 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 214 unsigned char *log_buff); 215 int pnv_pci_cfg_read(struct pci_dn *pdn, 216 int where, int size, u32 *val); 217 int pnv_pci_cfg_write(struct pci_dn *pdn, 218 int where, int size, u32 val); 219 extern struct iommu_table *pnv_pci_table_alloc(int nid); 220 221 extern long pnv_pci_link_table_and_group(int node, int num, 222 struct iommu_table *tbl, 223 struct iommu_table_group *table_group); 224 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, 225 struct iommu_table_group *table_group); 226 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 227 void *tce_mem, u64 tce_size, 228 u64 dma_offset, unsigned page_shift); 229 extern void pnv_pci_init_p5ioc2_hub(struct device_node *np); 230 extern void pnv_pci_init_ioda_hub(struct device_node *np); 231 extern void pnv_pci_init_ioda2_phb(struct device_node *np); 232 extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 233 __be64 *startp, __be64 *endp, bool rm); 234 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 235 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option); 236 237 extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev); 238 extern void pnv_pci_dma_bus_setup(struct pci_bus *bus); 239 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type); 240 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev); 241 242 #endif /* __POWERNV_PCI_H */ 243