1 /* 2 * arch/arm/mach-pxa/include/mach/idp.h 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc. 9 * 10 * 2001-09-13: Cliff Brake <cbrake@accelent.com> 11 * Initial code 12 * 13 * 2005-02-15: Cliff Brake <cliff.brake@gmail.com> 14 * <http://www.vibren.com> <http://bec-systems.com> 15 * Changes for 2.6 kernel. 16 */ 17 18 19 /* 20 * Note: this file must be safe to include in assembly files 21 * 22 * Support for the Vibren PXA255 IDP requires rev04 or later 23 * IDP hardware. 24 */ 25 26 #include "irqs.h" /* PXA_GPIO_TO_IRQ */ 27 28 #define IDP_FLASH_PHYS (PXA_CS0_PHYS) 29 #define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS) 30 #define IDP_MEDIAQ_PHYS (PXA_CS3_PHYS) 31 #define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000) 32 #define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000) 33 #define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000) 34 #define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000) 35 36 37 /* 38 * virtual memory map 39 */ 40 41 #define IDP_COREVOLT_VIRT (0xf0000000) 42 #define IDP_COREVOLT_SIZE (1*1024*1024) 43 44 #define IDP_CPLD_VIRT (IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE) 45 #define IDP_CPLD_SIZE (1*1024*1024) 46 47 #if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000 48 #error Your custom IO space is getting a bit large !! 49 #endif 50 51 #define CPLD_P2V(x) ((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT) 52 #define CPLD_V2P(x) ((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS) 53 54 #ifndef __ASSEMBLY__ 55 # define __CPLD_REG(x) (*((volatile unsigned long *)CPLD_P2V(x))) 56 #else 57 # define __CPLD_REG(x) CPLD_P2V(x) 58 #endif 59 60 /* board level registers in the CPLD: (offsets from CPLD_VIRT) */ 61 62 #define _IDP_CPLD_REV (IDP_CPLD_PHYS + 0x00) 63 #define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04) 64 #define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x08) 65 #define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C) 66 #define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10) 67 #define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14) 68 #define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18) 69 #define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C) 70 #define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20) 71 #define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24) 72 #define _IDP_CPLD_PCCARD_PWR (IDP_CPLD_PHYS + 0x28) 73 #define _IDP_CPLD_MISC_CTRL (IDP_CPLD_PHYS + 0x2C) 74 #define _IDP_CPLD_LCD (IDP_CPLD_PHYS + 0x30) 75 #define _IDP_CPLD_FLASH_WE (IDP_CPLD_PHYS + 0x34) 76 77 #define _IDP_CPLD_KB_ROW (IDP_CPLD_PHYS + 0x50) 78 #define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x54) 79 #define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x58) 80 #define _IDP_CPLD_MISC_STATUS (IDP_CPLD_PHYS + 0x5C) 81 82 /* FPGA register virtual addresses */ 83 84 #define IDP_CPLD_REV __CPLD_REG(_IDP_CPLD_REV) 85 #define IDP_CPLD_PERIPH_PWR __CPLD_REG(_IDP_CPLD_PERIPH_PWR) 86 #define IDP_CPLD_LED_CONTROL __CPLD_REG(_IDP_CPLD_LED_CONTROL) 87 #define IDP_CPLD_KB_COL_HIGH __CPLD_REG(_IDP_CPLD_KB_COL_HIGH) 88 #define IDP_CPLD_KB_COL_LOW __CPLD_REG(_IDP_CPLD_KB_COL_LOW) 89 #define IDP_CPLD_PCCARD_EN __CPLD_REG(_IDP_CPLD_PCCARD_EN) 90 #define IDP_CPLD_GPIOH_DIR __CPLD_REG(_IDP_CPLD_GPIOH_DIR) 91 #define IDP_CPLD_GPIOH_VALUE __CPLD_REG(_IDP_CPLD_GPIOH_VALUE) 92 #define IDP_CPLD_GPIOL_DIR __CPLD_REG(_IDP_CPLD_GPIOL_DIR) 93 #define IDP_CPLD_GPIOL_VALUE __CPLD_REG(_IDP_CPLD_GPIOL_VALUE) 94 #define IDP_CPLD_PCCARD_PWR __CPLD_REG(_IDP_CPLD_PCCARD_PWR) 95 #define IDP_CPLD_MISC_CTRL __CPLD_REG(_IDP_CPLD_MISC_CTRL) 96 #define IDP_CPLD_LCD __CPLD_REG(_IDP_CPLD_LCD) 97 #define IDP_CPLD_FLASH_WE __CPLD_REG(_IDP_CPLD_FLASH_WE) 98 99 #define IDP_CPLD_KB_ROW __CPLD_REG(_IDP_CPLD_KB_ROW) 100 #define IDP_CPLD_PCCARD0_STATUS __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS) 101 #define IDP_CPLD_PCCARD1_STATUS __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS) 102 #define IDP_CPLD_MISC_STATUS __CPLD_REG(_IDP_CPLD_MISC_STATUS) 103 104 105 /* 106 * Bit masks for various registers 107 */ 108 109 // IDP_CPLD_PCCARD_PWR 110 #define PCC0_PWR0 (1 << 0) 111 #define PCC0_PWR1 (1 << 1) 112 #define PCC0_PWR2 (1 << 2) 113 #define PCC0_PWR3 (1 << 3) 114 #define PCC1_PWR0 (1 << 4) 115 #define PCC1_PWR1 (1 << 5) 116 #define PCC1_PWR2 (1 << 6) 117 #define PCC1_PWR3 (1 << 7) 118 119 // IDP_CPLD_PCCARD_EN 120 #define PCC0_RESET (1 << 6) 121 #define PCC1_RESET (1 << 7) 122 #define PCC0_ENABLE (1 << 0) 123 #define PCC1_ENABLE (1 << 1) 124 125 // IDP_CPLD_PCCARDx_STATUS 126 #define _PCC_WRPROT (1 << 7) // 7-4 read as low true 127 #define _PCC_RESET (1 << 6) 128 #define _PCC_IRQ (1 << 5) 129 #define _PCC_INPACK (1 << 4) 130 #define PCC_BVD2 (1 << 3) 131 #define PCC_BVD1 (1 << 2) 132 #define PCC_VS2 (1 << 1) 133 #define PCC_VS1 (1 << 0) 134 135 /* A listing of interrupts used by external hardware devices */ 136 137 #define TOUCH_PANEL_IRQ PXA_GPIO_TO_IRQ(5) 138 #define IDE_IRQ PXA_GPIO_TO_IRQ(21) 139 140 #define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING 141 142 #define ETHERNET_IRQ PXA_GPIO_TO_IRQ(4) 143 #define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING 144 145 #define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING 146 147 #define PCMCIA_S0_CD_VALID PXA_GPIO_TO_IRQ(7) 148 #define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH 149 150 #define PCMCIA_S1_CD_VALID PXA_GPIO_TO_IRQ(8) 151 #define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH 152 153 #define PCMCIA_S0_RDYINT PXA_GPIO_TO_IRQ(19) 154 #define PCMCIA_S1_RDYINT PXA_GPIO_TO_IRQ(22) 155 156 157 /* 158 * Macros for LED Driver 159 */ 160 161 /* leds 0 = ON */ 162 #define IDP_HB_LED (1<<5) 163 #define IDP_BUSY_LED (1<<6) 164 165 #define IDP_LEDS_MASK (IDP_HB_LED | IDP_BUSY_LED) 166 167 /* 168 * macros for MTD driver 169 */ 170 171 #define FLASH_WRITE_PROTECT_DISABLE() ((IDP_CPLD_FLASH_WE) &= ~(0x1)) 172 #define FLASH_WRITE_PROTECT_ENABLE() ((IDP_CPLD_FLASH_WE) |= (0x1)) 173 174 /* 175 * macros for matrix keyboard driver 176 */ 177 178 #define KEYBD_MATRIX_NUMBER_INPUTS 7 179 #define KEYBD_MATRIX_NUMBER_OUTPUTS 14 180 181 #define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC FALSE 182 #define KEYBD_MATRIX_INVERT_INPUT_LOGIC FALSE 183 184 #define KEYBD_MATRIX_SETTLING_TIME_US 100 185 #define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT 2 186 187 #define KEYBD_MATRIX_SET_OUTPUTS(outputs) \ 188 {\ 189 IDP_CPLD_KB_COL_LOW = outputs;\ 190 IDP_CPLD_KB_COL_HIGH = outputs >> 7;\ 191 } 192 193 #define KEYBD_MATRIX_GET_INPUTS(inputs) \ 194 {\ 195 inputs = (IDP_CPLD_KB_ROW & 0x7f);\ 196 } 197 198 199