1 /*
2 * Intel I/OAT DMA Linux driver
3 * Copyright(c) 2004 - 2015 Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in
15 * the file called "COPYING".
16 *
17 */
18
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/slab.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 #include <linux/dmaengine.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/workqueue.h>
28 #include <linux/prefetch.h>
29 #include <linux/dca.h>
30 #include <linux/aer.h>
31 #include "dma.h"
32 #include "registers.h"
33 #include "hw.h"
34
35 #include "../dmaengine.h"
36
37 MODULE_VERSION(IOAT_DMA_VERSION);
38 MODULE_LICENSE("Dual BSD/GPL");
39 MODULE_AUTHOR("Intel Corporation");
40
41 static struct pci_device_id ioat_pci_tbl[] = {
42 /* I/OAT v3 platforms */
43 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) },
44 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) },
45 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) },
46 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) },
47 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) },
48 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) },
49 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) },
50 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) },
51
52 /* I/OAT v3.2 platforms */
53 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) },
54 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) },
55 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) },
56 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) },
57 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) },
58 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) },
59 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) },
60 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) },
61 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) },
62 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) },
63
64 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) },
65 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) },
66 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) },
67 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) },
68 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) },
69 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) },
70 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) },
71 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) },
72 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) },
73 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) },
74
75 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) },
76 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) },
77 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) },
78 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) },
79 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) },
80 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) },
81 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) },
82 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) },
83 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) },
84 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) },
85
86 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0) },
87 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW1) },
88 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2) },
89 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3) },
90 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4) },
91 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5) },
92 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6) },
93 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7) },
94 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8) },
95 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9) },
96
97 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX0) },
98 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX1) },
99 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX2) },
100 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX3) },
101 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX4) },
102 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX5) },
103 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX6) },
104 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX7) },
105 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX8) },
106 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX9) },
107
108 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SKX) },
109
110 /* I/OAT v3.3 platforms */
111 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0) },
112 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1) },
113 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2) },
114 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3) },
115
116 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0) },
117 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1) },
118 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2) },
119 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3) },
120
121 { 0, }
122 };
123 MODULE_DEVICE_TABLE(pci, ioat_pci_tbl);
124
125 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
126 static void ioat_remove(struct pci_dev *pdev);
127 static void
128 ioat_init_channel(struct ioatdma_device *ioat_dma,
129 struct ioatdma_chan *ioat_chan, int idx);
130 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma);
131 static void ioat_enumerate_channels(struct ioatdma_device *ioat_dma);
132 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma);
133
134 static int ioat_dca_enabled = 1;
135 module_param(ioat_dca_enabled, int, 0644);
136 MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)");
137 int ioat_pending_level = 4;
138 module_param(ioat_pending_level, int, 0644);
139 MODULE_PARM_DESC(ioat_pending_level,
140 "high-water mark for pushing ioat descriptors (default: 4)");
141 int ioat_ring_alloc_order = 8;
142 module_param(ioat_ring_alloc_order, int, 0644);
143 MODULE_PARM_DESC(ioat_ring_alloc_order,
144 "ioat+: allocate 2^n descriptors per channel (default: 8 max: 16)");
145 int ioat_ring_max_alloc_order = IOAT_MAX_ORDER;
146 module_param(ioat_ring_max_alloc_order, int, 0644);
147 MODULE_PARM_DESC(ioat_ring_max_alloc_order,
148 "ioat+: upper limit for ring size (default: 16)");
149 static char ioat_interrupt_style[32] = "msix";
150 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
151 sizeof(ioat_interrupt_style), 0644);
152 MODULE_PARM_DESC(ioat_interrupt_style,
153 "set ioat interrupt style: msix (default), msi, intx");
154
155 struct kmem_cache *ioat_cache;
156 struct kmem_cache *ioat_sed_cache;
157
is_jf_ioat(struct pci_dev * pdev)158 static bool is_jf_ioat(struct pci_dev *pdev)
159 {
160 switch (pdev->device) {
161 case PCI_DEVICE_ID_INTEL_IOAT_JSF0:
162 case PCI_DEVICE_ID_INTEL_IOAT_JSF1:
163 case PCI_DEVICE_ID_INTEL_IOAT_JSF2:
164 case PCI_DEVICE_ID_INTEL_IOAT_JSF3:
165 case PCI_DEVICE_ID_INTEL_IOAT_JSF4:
166 case PCI_DEVICE_ID_INTEL_IOAT_JSF5:
167 case PCI_DEVICE_ID_INTEL_IOAT_JSF6:
168 case PCI_DEVICE_ID_INTEL_IOAT_JSF7:
169 case PCI_DEVICE_ID_INTEL_IOAT_JSF8:
170 case PCI_DEVICE_ID_INTEL_IOAT_JSF9:
171 return true;
172 default:
173 return false;
174 }
175 }
176
is_snb_ioat(struct pci_dev * pdev)177 static bool is_snb_ioat(struct pci_dev *pdev)
178 {
179 switch (pdev->device) {
180 case PCI_DEVICE_ID_INTEL_IOAT_SNB0:
181 case PCI_DEVICE_ID_INTEL_IOAT_SNB1:
182 case PCI_DEVICE_ID_INTEL_IOAT_SNB2:
183 case PCI_DEVICE_ID_INTEL_IOAT_SNB3:
184 case PCI_DEVICE_ID_INTEL_IOAT_SNB4:
185 case PCI_DEVICE_ID_INTEL_IOAT_SNB5:
186 case PCI_DEVICE_ID_INTEL_IOAT_SNB6:
187 case PCI_DEVICE_ID_INTEL_IOAT_SNB7:
188 case PCI_DEVICE_ID_INTEL_IOAT_SNB8:
189 case PCI_DEVICE_ID_INTEL_IOAT_SNB9:
190 return true;
191 default:
192 return false;
193 }
194 }
195
is_ivb_ioat(struct pci_dev * pdev)196 static bool is_ivb_ioat(struct pci_dev *pdev)
197 {
198 switch (pdev->device) {
199 case PCI_DEVICE_ID_INTEL_IOAT_IVB0:
200 case PCI_DEVICE_ID_INTEL_IOAT_IVB1:
201 case PCI_DEVICE_ID_INTEL_IOAT_IVB2:
202 case PCI_DEVICE_ID_INTEL_IOAT_IVB3:
203 case PCI_DEVICE_ID_INTEL_IOAT_IVB4:
204 case PCI_DEVICE_ID_INTEL_IOAT_IVB5:
205 case PCI_DEVICE_ID_INTEL_IOAT_IVB6:
206 case PCI_DEVICE_ID_INTEL_IOAT_IVB7:
207 case PCI_DEVICE_ID_INTEL_IOAT_IVB8:
208 case PCI_DEVICE_ID_INTEL_IOAT_IVB9:
209 return true;
210 default:
211 return false;
212 }
213
214 }
215
is_hsw_ioat(struct pci_dev * pdev)216 static bool is_hsw_ioat(struct pci_dev *pdev)
217 {
218 switch (pdev->device) {
219 case PCI_DEVICE_ID_INTEL_IOAT_HSW0:
220 case PCI_DEVICE_ID_INTEL_IOAT_HSW1:
221 case PCI_DEVICE_ID_INTEL_IOAT_HSW2:
222 case PCI_DEVICE_ID_INTEL_IOAT_HSW3:
223 case PCI_DEVICE_ID_INTEL_IOAT_HSW4:
224 case PCI_DEVICE_ID_INTEL_IOAT_HSW5:
225 case PCI_DEVICE_ID_INTEL_IOAT_HSW6:
226 case PCI_DEVICE_ID_INTEL_IOAT_HSW7:
227 case PCI_DEVICE_ID_INTEL_IOAT_HSW8:
228 case PCI_DEVICE_ID_INTEL_IOAT_HSW9:
229 return true;
230 default:
231 return false;
232 }
233
234 }
235
is_bdx_ioat(struct pci_dev * pdev)236 static bool is_bdx_ioat(struct pci_dev *pdev)
237 {
238 switch (pdev->device) {
239 case PCI_DEVICE_ID_INTEL_IOAT_BDX0:
240 case PCI_DEVICE_ID_INTEL_IOAT_BDX1:
241 case PCI_DEVICE_ID_INTEL_IOAT_BDX2:
242 case PCI_DEVICE_ID_INTEL_IOAT_BDX3:
243 case PCI_DEVICE_ID_INTEL_IOAT_BDX4:
244 case PCI_DEVICE_ID_INTEL_IOAT_BDX5:
245 case PCI_DEVICE_ID_INTEL_IOAT_BDX6:
246 case PCI_DEVICE_ID_INTEL_IOAT_BDX7:
247 case PCI_DEVICE_ID_INTEL_IOAT_BDX8:
248 case PCI_DEVICE_ID_INTEL_IOAT_BDX9:
249 return true;
250 default:
251 return false;
252 }
253 }
254
is_skx_ioat(struct pci_dev * pdev)255 static inline bool is_skx_ioat(struct pci_dev *pdev)
256 {
257 return (pdev->device == PCI_DEVICE_ID_INTEL_IOAT_SKX) ? true : false;
258 }
259
is_xeon_cb32(struct pci_dev * pdev)260 static bool is_xeon_cb32(struct pci_dev *pdev)
261 {
262 return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) ||
263 is_hsw_ioat(pdev) || is_bdx_ioat(pdev) || is_skx_ioat(pdev);
264 }
265
is_bwd_ioat(struct pci_dev * pdev)266 bool is_bwd_ioat(struct pci_dev *pdev)
267 {
268 switch (pdev->device) {
269 case PCI_DEVICE_ID_INTEL_IOAT_BWD0:
270 case PCI_DEVICE_ID_INTEL_IOAT_BWD1:
271 case PCI_DEVICE_ID_INTEL_IOAT_BWD2:
272 case PCI_DEVICE_ID_INTEL_IOAT_BWD3:
273 /* even though not Atom, BDX-DE has same DMA silicon */
274 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0:
275 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1:
276 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2:
277 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3:
278 return true;
279 default:
280 return false;
281 }
282 }
283
is_bwd_noraid(struct pci_dev * pdev)284 static bool is_bwd_noraid(struct pci_dev *pdev)
285 {
286 switch (pdev->device) {
287 case PCI_DEVICE_ID_INTEL_IOAT_BWD2:
288 case PCI_DEVICE_ID_INTEL_IOAT_BWD3:
289 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0:
290 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1:
291 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2:
292 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3:
293 return true;
294 default:
295 return false;
296 }
297
298 }
299
300 /*
301 * Perform a IOAT transaction to verify the HW works.
302 */
303 #define IOAT_TEST_SIZE 2000
304
ioat_dma_test_callback(void * dma_async_param)305 static void ioat_dma_test_callback(void *dma_async_param)
306 {
307 struct completion *cmp = dma_async_param;
308
309 complete(cmp);
310 }
311
312 /**
313 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
314 * @ioat_dma: dma device to be tested
315 */
ioat_dma_self_test(struct ioatdma_device * ioat_dma)316 static int ioat_dma_self_test(struct ioatdma_device *ioat_dma)
317 {
318 int i;
319 u8 *src;
320 u8 *dest;
321 struct dma_device *dma = &ioat_dma->dma_dev;
322 struct device *dev = &ioat_dma->pdev->dev;
323 struct dma_chan *dma_chan;
324 struct dma_async_tx_descriptor *tx;
325 dma_addr_t dma_dest, dma_src;
326 dma_cookie_t cookie;
327 int err = 0;
328 struct completion cmp;
329 unsigned long tmo;
330 unsigned long flags;
331
332 src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
333 if (!src)
334 return -ENOMEM;
335 dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
336 if (!dest) {
337 kfree(src);
338 return -ENOMEM;
339 }
340
341 /* Fill in src buffer */
342 for (i = 0; i < IOAT_TEST_SIZE; i++)
343 src[i] = (u8)i;
344
345 /* Start copy, using first DMA channel */
346 dma_chan = container_of(dma->channels.next, struct dma_chan,
347 device_node);
348 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
349 dev_err(dev, "selftest cannot allocate chan resource\n");
350 err = -ENODEV;
351 goto out;
352 }
353
354 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
355 if (dma_mapping_error(dev, dma_src)) {
356 dev_err(dev, "mapping src buffer failed\n");
357 goto free_resources;
358 }
359 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
360 if (dma_mapping_error(dev, dma_dest)) {
361 dev_err(dev, "mapping dest buffer failed\n");
362 goto unmap_src;
363 }
364 flags = DMA_PREP_INTERRUPT;
365 tx = ioat_dma->dma_dev.device_prep_dma_memcpy(dma_chan, dma_dest,
366 dma_src, IOAT_TEST_SIZE,
367 flags);
368 if (!tx) {
369 dev_err(dev, "Self-test prep failed, disabling\n");
370 err = -ENODEV;
371 goto unmap_dma;
372 }
373
374 async_tx_ack(tx);
375 init_completion(&cmp);
376 tx->callback = ioat_dma_test_callback;
377 tx->callback_param = &cmp;
378 cookie = tx->tx_submit(tx);
379 if (cookie < 0) {
380 dev_err(dev, "Self-test setup failed, disabling\n");
381 err = -ENODEV;
382 goto unmap_dma;
383 }
384 dma->device_issue_pending(dma_chan);
385
386 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
387
388 if (tmo == 0 ||
389 dma->device_tx_status(dma_chan, cookie, NULL)
390 != DMA_COMPLETE) {
391 dev_err(dev, "Self-test copy timed out, disabling\n");
392 err = -ENODEV;
393 goto unmap_dma;
394 }
395 if (memcmp(src, dest, IOAT_TEST_SIZE)) {
396 dev_err(dev, "Self-test copy failed compare, disabling\n");
397 err = -ENODEV;
398 goto unmap_dma;
399 }
400
401 unmap_dma:
402 dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
403 unmap_src:
404 dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
405 free_resources:
406 dma->device_free_chan_resources(dma_chan);
407 out:
408 kfree(src);
409 kfree(dest);
410 return err;
411 }
412
413 /**
414 * ioat_dma_setup_interrupts - setup interrupt handler
415 * @ioat_dma: ioat dma device
416 */
ioat_dma_setup_interrupts(struct ioatdma_device * ioat_dma)417 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma)
418 {
419 struct ioatdma_chan *ioat_chan;
420 struct pci_dev *pdev = ioat_dma->pdev;
421 struct device *dev = &pdev->dev;
422 struct msix_entry *msix;
423 int i, j, msixcnt;
424 int err = -EINVAL;
425 u8 intrctrl = 0;
426
427 if (!strcmp(ioat_interrupt_style, "msix"))
428 goto msix;
429 if (!strcmp(ioat_interrupt_style, "msi"))
430 goto msi;
431 if (!strcmp(ioat_interrupt_style, "intx"))
432 goto intx;
433 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
434 goto err_no_irq;
435
436 msix:
437 /* The number of MSI-X vectors should equal the number of channels */
438 msixcnt = ioat_dma->dma_dev.chancnt;
439 for (i = 0; i < msixcnt; i++)
440 ioat_dma->msix_entries[i].entry = i;
441
442 err = pci_enable_msix_exact(pdev, ioat_dma->msix_entries, msixcnt);
443 if (err)
444 goto msi;
445
446 for (i = 0; i < msixcnt; i++) {
447 msix = &ioat_dma->msix_entries[i];
448 ioat_chan = ioat_chan_by_index(ioat_dma, i);
449 err = devm_request_irq(dev, msix->vector,
450 ioat_dma_do_interrupt_msix, 0,
451 "ioat-msix", ioat_chan);
452 if (err) {
453 for (j = 0; j < i; j++) {
454 msix = &ioat_dma->msix_entries[j];
455 ioat_chan = ioat_chan_by_index(ioat_dma, j);
456 devm_free_irq(dev, msix->vector, ioat_chan);
457 }
458 goto msi;
459 }
460 }
461 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
462 ioat_dma->irq_mode = IOAT_MSIX;
463 goto done;
464
465 msi:
466 err = pci_enable_msi(pdev);
467 if (err)
468 goto intx;
469
470 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
471 "ioat-msi", ioat_dma);
472 if (err) {
473 pci_disable_msi(pdev);
474 goto intx;
475 }
476 ioat_dma->irq_mode = IOAT_MSI;
477 goto done;
478
479 intx:
480 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
481 IRQF_SHARED, "ioat-intx", ioat_dma);
482 if (err)
483 goto err_no_irq;
484
485 ioat_dma->irq_mode = IOAT_INTX;
486 done:
487 if (is_bwd_ioat(pdev))
488 ioat_intr_quirk(ioat_dma);
489 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
490 writeb(intrctrl, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
491 return 0;
492
493 err_no_irq:
494 /* Disable all interrupt generation */
495 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
496 ioat_dma->irq_mode = IOAT_NOIRQ;
497 dev_err(dev, "no usable interrupts\n");
498 return err;
499 }
500
ioat_disable_interrupts(struct ioatdma_device * ioat_dma)501 static void ioat_disable_interrupts(struct ioatdma_device *ioat_dma)
502 {
503 /* Disable all interrupt generation */
504 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
505 }
506
ioat_probe(struct ioatdma_device * ioat_dma)507 static int ioat_probe(struct ioatdma_device *ioat_dma)
508 {
509 int err = -ENODEV;
510 struct dma_device *dma = &ioat_dma->dma_dev;
511 struct pci_dev *pdev = ioat_dma->pdev;
512 struct device *dev = &pdev->dev;
513
514 /* DMA coherent memory pool for DMA descriptor allocations */
515 ioat_dma->dma_pool = pci_pool_create("dma_desc_pool", pdev,
516 sizeof(struct ioat_dma_descriptor),
517 64, 0);
518 if (!ioat_dma->dma_pool) {
519 err = -ENOMEM;
520 goto err_dma_pool;
521 }
522
523 ioat_dma->completion_pool = pci_pool_create("completion_pool", pdev,
524 sizeof(u64),
525 SMP_CACHE_BYTES,
526 SMP_CACHE_BYTES);
527
528 if (!ioat_dma->completion_pool) {
529 err = -ENOMEM;
530 goto err_completion_pool;
531 }
532
533 ioat_enumerate_channels(ioat_dma);
534
535 dma_cap_set(DMA_MEMCPY, dma->cap_mask);
536 dma->dev = &pdev->dev;
537
538 if (!dma->chancnt) {
539 dev_err(dev, "channel enumeration error\n");
540 goto err_setup_interrupts;
541 }
542
543 err = ioat_dma_setup_interrupts(ioat_dma);
544 if (err)
545 goto err_setup_interrupts;
546
547 err = ioat3_dma_self_test(ioat_dma);
548 if (err)
549 goto err_self_test;
550
551 return 0;
552
553 err_self_test:
554 ioat_disable_interrupts(ioat_dma);
555 err_setup_interrupts:
556 pci_pool_destroy(ioat_dma->completion_pool);
557 err_completion_pool:
558 pci_pool_destroy(ioat_dma->dma_pool);
559 err_dma_pool:
560 return err;
561 }
562
ioat_register(struct ioatdma_device * ioat_dma)563 static int ioat_register(struct ioatdma_device *ioat_dma)
564 {
565 int err = dma_async_device_register(&ioat_dma->dma_dev);
566
567 if (err) {
568 ioat_disable_interrupts(ioat_dma);
569 pci_pool_destroy(ioat_dma->completion_pool);
570 pci_pool_destroy(ioat_dma->dma_pool);
571 }
572
573 return err;
574 }
575
ioat_dma_remove(struct ioatdma_device * ioat_dma)576 static void ioat_dma_remove(struct ioatdma_device *ioat_dma)
577 {
578 struct dma_device *dma = &ioat_dma->dma_dev;
579
580 ioat_disable_interrupts(ioat_dma);
581
582 ioat_kobject_del(ioat_dma);
583
584 dma_async_device_unregister(dma);
585
586 pci_pool_destroy(ioat_dma->dma_pool);
587 pci_pool_destroy(ioat_dma->completion_pool);
588
589 INIT_LIST_HEAD(&dma->channels);
590 }
591
592 /**
593 * ioat_enumerate_channels - find and initialize the device's channels
594 * @ioat_dma: the ioat dma device to be enumerated
595 */
ioat_enumerate_channels(struct ioatdma_device * ioat_dma)596 static void ioat_enumerate_channels(struct ioatdma_device *ioat_dma)
597 {
598 struct ioatdma_chan *ioat_chan;
599 struct device *dev = &ioat_dma->pdev->dev;
600 struct dma_device *dma = &ioat_dma->dma_dev;
601 u8 xfercap_log;
602 int i;
603
604 INIT_LIST_HEAD(&dma->channels);
605 dma->chancnt = readb(ioat_dma->reg_base + IOAT_CHANCNT_OFFSET);
606 dma->chancnt &= 0x1f; /* bits [4:0] valid */
607 if (dma->chancnt > ARRAY_SIZE(ioat_dma->idx)) {
608 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
609 dma->chancnt, ARRAY_SIZE(ioat_dma->idx));
610 dma->chancnt = ARRAY_SIZE(ioat_dma->idx);
611 }
612 xfercap_log = readb(ioat_dma->reg_base + IOAT_XFERCAP_OFFSET);
613 xfercap_log &= 0x1f; /* bits [4:0] valid */
614 if (xfercap_log == 0)
615 return;
616 dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log);
617
618 for (i = 0; i < dma->chancnt; i++) {
619 ioat_chan = devm_kzalloc(dev, sizeof(*ioat_chan), GFP_KERNEL);
620 if (!ioat_chan)
621 break;
622
623 ioat_init_channel(ioat_dma, ioat_chan, i);
624 ioat_chan->xfercap_log = xfercap_log;
625 spin_lock_init(&ioat_chan->prep_lock);
626 if (ioat_reset_hw(ioat_chan)) {
627 i = 0;
628 break;
629 }
630 }
631 dma->chancnt = i;
632 }
633
634 /**
635 * ioat_free_chan_resources - release all the descriptors
636 * @chan: the channel to be cleaned
637 */
ioat_free_chan_resources(struct dma_chan * c)638 static void ioat_free_chan_resources(struct dma_chan *c)
639 {
640 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
641 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;
642 struct ioat_ring_ent *desc;
643 const int total_descs = 1 << ioat_chan->alloc_order;
644 int descs;
645 int i;
646
647 /* Before freeing channel resources first check
648 * if they have been previously allocated for this channel.
649 */
650 if (!ioat_chan->ring)
651 return;
652
653 ioat_stop(ioat_chan);
654 ioat_reset_hw(ioat_chan);
655
656 spin_lock_bh(&ioat_chan->cleanup_lock);
657 spin_lock_bh(&ioat_chan->prep_lock);
658 descs = ioat_ring_space(ioat_chan);
659 dev_dbg(to_dev(ioat_chan), "freeing %d idle descriptors\n", descs);
660 for (i = 0; i < descs; i++) {
661 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head + i);
662 ioat_free_ring_ent(desc, c);
663 }
664
665 if (descs < total_descs)
666 dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n",
667 total_descs - descs);
668
669 for (i = 0; i < total_descs - descs; i++) {
670 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail + i);
671 dump_desc_dbg(ioat_chan, desc);
672 ioat_free_ring_ent(desc, c);
673 }
674
675 kfree(ioat_chan->ring);
676 ioat_chan->ring = NULL;
677 ioat_chan->alloc_order = 0;
678 pci_pool_free(ioat_dma->completion_pool, ioat_chan->completion,
679 ioat_chan->completion_dma);
680 spin_unlock_bh(&ioat_chan->prep_lock);
681 spin_unlock_bh(&ioat_chan->cleanup_lock);
682
683 ioat_chan->last_completion = 0;
684 ioat_chan->completion_dma = 0;
685 ioat_chan->dmacount = 0;
686 }
687
688 /* ioat_alloc_chan_resources - allocate/initialize ioat descriptor ring
689 * @chan: channel to be initialized
690 */
ioat_alloc_chan_resources(struct dma_chan * c)691 static int ioat_alloc_chan_resources(struct dma_chan *c)
692 {
693 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
694 struct ioat_ring_ent **ring;
695 u64 status;
696 int order;
697 int i = 0;
698 u32 chanerr;
699
700 /* have we already been set up? */
701 if (ioat_chan->ring)
702 return 1 << ioat_chan->alloc_order;
703
704 /* Setup register to interrupt and write completion status on error */
705 writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
706
707 /* allocate a completion writeback area */
708 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
709 ioat_chan->completion =
710 pci_pool_alloc(ioat_chan->ioat_dma->completion_pool,
711 GFP_KERNEL, &ioat_chan->completion_dma);
712 if (!ioat_chan->completion)
713 return -ENOMEM;
714
715 memset(ioat_chan->completion, 0, sizeof(*ioat_chan->completion));
716 writel(((u64)ioat_chan->completion_dma) & 0x00000000FFFFFFFF,
717 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
718 writel(((u64)ioat_chan->completion_dma) >> 32,
719 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
720
721 order = ioat_get_alloc_order();
722 ring = ioat_alloc_ring(c, order, GFP_KERNEL);
723 if (!ring)
724 return -ENOMEM;
725
726 spin_lock_bh(&ioat_chan->cleanup_lock);
727 spin_lock_bh(&ioat_chan->prep_lock);
728 ioat_chan->ring = ring;
729 ioat_chan->head = 0;
730 ioat_chan->issued = 0;
731 ioat_chan->tail = 0;
732 ioat_chan->alloc_order = order;
733 set_bit(IOAT_RUN, &ioat_chan->state);
734 spin_unlock_bh(&ioat_chan->prep_lock);
735 spin_unlock_bh(&ioat_chan->cleanup_lock);
736
737 ioat_start_null_desc(ioat_chan);
738
739 /* check that we got off the ground */
740 do {
741 udelay(1);
742 status = ioat_chansts(ioat_chan);
743 } while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status));
744
745 if (is_ioat_active(status) || is_ioat_idle(status))
746 return 1 << ioat_chan->alloc_order;
747
748 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
749
750 dev_WARN(to_dev(ioat_chan),
751 "failed to start channel chanerr: %#x\n", chanerr);
752 ioat_free_chan_resources(c);
753 return -EFAULT;
754 }
755
756 /* common channel initialization */
757 static void
ioat_init_channel(struct ioatdma_device * ioat_dma,struct ioatdma_chan * ioat_chan,int idx)758 ioat_init_channel(struct ioatdma_device *ioat_dma,
759 struct ioatdma_chan *ioat_chan, int idx)
760 {
761 struct dma_device *dma = &ioat_dma->dma_dev;
762 struct dma_chan *c = &ioat_chan->dma_chan;
763 unsigned long data = (unsigned long) c;
764
765 ioat_chan->ioat_dma = ioat_dma;
766 ioat_chan->reg_base = ioat_dma->reg_base + (0x80 * (idx + 1));
767 spin_lock_init(&ioat_chan->cleanup_lock);
768 ioat_chan->dma_chan.device = dma;
769 dma_cookie_init(&ioat_chan->dma_chan);
770 list_add_tail(&ioat_chan->dma_chan.device_node, &dma->channels);
771 ioat_dma->idx[idx] = ioat_chan;
772 init_timer(&ioat_chan->timer);
773 ioat_chan->timer.function = ioat_timer_event;
774 ioat_chan->timer.data = data;
775 tasklet_init(&ioat_chan->cleanup_task, ioat_cleanup_event, data);
776 }
777
778 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */
ioat_xor_val_self_test(struct ioatdma_device * ioat_dma)779 static int ioat_xor_val_self_test(struct ioatdma_device *ioat_dma)
780 {
781 int i, src_idx;
782 struct page *dest;
783 struct page *xor_srcs[IOAT_NUM_SRC_TEST];
784 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1];
785 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1];
786 dma_addr_t dest_dma;
787 struct dma_async_tx_descriptor *tx;
788 struct dma_chan *dma_chan;
789 dma_cookie_t cookie;
790 u8 cmp_byte = 0;
791 u32 cmp_word;
792 u32 xor_val_result;
793 int err = 0;
794 struct completion cmp;
795 unsigned long tmo;
796 struct device *dev = &ioat_dma->pdev->dev;
797 struct dma_device *dma = &ioat_dma->dma_dev;
798 u8 op = 0;
799
800 dev_dbg(dev, "%s\n", __func__);
801
802 if (!dma_has_cap(DMA_XOR, dma->cap_mask))
803 return 0;
804
805 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
806 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
807 if (!xor_srcs[src_idx]) {
808 while (src_idx--)
809 __free_page(xor_srcs[src_idx]);
810 return -ENOMEM;
811 }
812 }
813
814 dest = alloc_page(GFP_KERNEL);
815 if (!dest) {
816 while (src_idx--)
817 __free_page(xor_srcs[src_idx]);
818 return -ENOMEM;
819 }
820
821 /* Fill in src buffers */
822 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
823 u8 *ptr = page_address(xor_srcs[src_idx]);
824
825 for (i = 0; i < PAGE_SIZE; i++)
826 ptr[i] = (1 << src_idx);
827 }
828
829 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++)
830 cmp_byte ^= (u8) (1 << src_idx);
831
832 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
833 (cmp_byte << 8) | cmp_byte;
834
835 memset(page_address(dest), 0, PAGE_SIZE);
836
837 dma_chan = container_of(dma->channels.next, struct dma_chan,
838 device_node);
839 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
840 err = -ENODEV;
841 goto out;
842 }
843
844 /* test xor */
845 op = IOAT_OP_XOR;
846
847 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE);
848 if (dma_mapping_error(dev, dest_dma))
849 goto dma_unmap;
850
851 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
852 dma_srcs[i] = DMA_ERROR_CODE;
853 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) {
854 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE,
855 DMA_TO_DEVICE);
856 if (dma_mapping_error(dev, dma_srcs[i]))
857 goto dma_unmap;
858 }
859 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
860 IOAT_NUM_SRC_TEST, PAGE_SIZE,
861 DMA_PREP_INTERRUPT);
862
863 if (!tx) {
864 dev_err(dev, "Self-test xor prep failed\n");
865 err = -ENODEV;
866 goto dma_unmap;
867 }
868
869 async_tx_ack(tx);
870 init_completion(&cmp);
871 tx->callback = ioat_dma_test_callback;
872 tx->callback_param = &cmp;
873 cookie = tx->tx_submit(tx);
874 if (cookie < 0) {
875 dev_err(dev, "Self-test xor setup failed\n");
876 err = -ENODEV;
877 goto dma_unmap;
878 }
879 dma->device_issue_pending(dma_chan);
880
881 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
882
883 if (tmo == 0 ||
884 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
885 dev_err(dev, "Self-test xor timed out\n");
886 err = -ENODEV;
887 goto dma_unmap;
888 }
889
890 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
891 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
892
893 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
894 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
895 u32 *ptr = page_address(dest);
896
897 if (ptr[i] != cmp_word) {
898 dev_err(dev, "Self-test xor failed compare\n");
899 err = -ENODEV;
900 goto free_resources;
901 }
902 }
903 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
904
905 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
906
907 /* skip validate if the capability is not present */
908 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
909 goto free_resources;
910
911 op = IOAT_OP_XOR_VAL;
912
913 /* validate the sources with the destintation page */
914 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
915 xor_val_srcs[i] = xor_srcs[i];
916 xor_val_srcs[i] = dest;
917
918 xor_val_result = 1;
919
920 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
921 dma_srcs[i] = DMA_ERROR_CODE;
922 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) {
923 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
924 DMA_TO_DEVICE);
925 if (dma_mapping_error(dev, dma_srcs[i]))
926 goto dma_unmap;
927 }
928 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
929 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
930 &xor_val_result, DMA_PREP_INTERRUPT);
931 if (!tx) {
932 dev_err(dev, "Self-test zero prep failed\n");
933 err = -ENODEV;
934 goto dma_unmap;
935 }
936
937 async_tx_ack(tx);
938 init_completion(&cmp);
939 tx->callback = ioat_dma_test_callback;
940 tx->callback_param = &cmp;
941 cookie = tx->tx_submit(tx);
942 if (cookie < 0) {
943 dev_err(dev, "Self-test zero setup failed\n");
944 err = -ENODEV;
945 goto dma_unmap;
946 }
947 dma->device_issue_pending(dma_chan);
948
949 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
950
951 if (tmo == 0 ||
952 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
953 dev_err(dev, "Self-test validate timed out\n");
954 err = -ENODEV;
955 goto dma_unmap;
956 }
957
958 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
959 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
960
961 if (xor_val_result != 0) {
962 dev_err(dev, "Self-test validate failed compare\n");
963 err = -ENODEV;
964 goto free_resources;
965 }
966
967 memset(page_address(dest), 0, PAGE_SIZE);
968
969 /* test for non-zero parity sum */
970 op = IOAT_OP_XOR_VAL;
971
972 xor_val_result = 0;
973 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
974 dma_srcs[i] = DMA_ERROR_CODE;
975 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) {
976 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
977 DMA_TO_DEVICE);
978 if (dma_mapping_error(dev, dma_srcs[i]))
979 goto dma_unmap;
980 }
981 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
982 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
983 &xor_val_result, DMA_PREP_INTERRUPT);
984 if (!tx) {
985 dev_err(dev, "Self-test 2nd zero prep failed\n");
986 err = -ENODEV;
987 goto dma_unmap;
988 }
989
990 async_tx_ack(tx);
991 init_completion(&cmp);
992 tx->callback = ioat_dma_test_callback;
993 tx->callback_param = &cmp;
994 cookie = tx->tx_submit(tx);
995 if (cookie < 0) {
996 dev_err(dev, "Self-test 2nd zero setup failed\n");
997 err = -ENODEV;
998 goto dma_unmap;
999 }
1000 dma->device_issue_pending(dma_chan);
1001
1002 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
1003
1004 if (tmo == 0 ||
1005 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
1006 dev_err(dev, "Self-test 2nd validate timed out\n");
1007 err = -ENODEV;
1008 goto dma_unmap;
1009 }
1010
1011 if (xor_val_result != SUM_CHECK_P_RESULT) {
1012 dev_err(dev, "Self-test validate failed compare\n");
1013 err = -ENODEV;
1014 goto dma_unmap;
1015 }
1016
1017 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1018 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
1019
1020 goto free_resources;
1021 dma_unmap:
1022 if (op == IOAT_OP_XOR) {
1023 if (dest_dma != DMA_ERROR_CODE)
1024 dma_unmap_page(dev, dest_dma, PAGE_SIZE,
1025 DMA_FROM_DEVICE);
1026 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
1027 if (dma_srcs[i] != DMA_ERROR_CODE)
1028 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1029 DMA_TO_DEVICE);
1030 } else if (op == IOAT_OP_XOR_VAL) {
1031 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1032 if (dma_srcs[i] != DMA_ERROR_CODE)
1033 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1034 DMA_TO_DEVICE);
1035 }
1036 free_resources:
1037 dma->device_free_chan_resources(dma_chan);
1038 out:
1039 src_idx = IOAT_NUM_SRC_TEST;
1040 while (src_idx--)
1041 __free_page(xor_srcs[src_idx]);
1042 __free_page(dest);
1043 return err;
1044 }
1045
ioat3_dma_self_test(struct ioatdma_device * ioat_dma)1046 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma)
1047 {
1048 int rc;
1049
1050 rc = ioat_dma_self_test(ioat_dma);
1051 if (rc)
1052 return rc;
1053
1054 rc = ioat_xor_val_self_test(ioat_dma);
1055
1056 return rc;
1057 }
1058
ioat_intr_quirk(struct ioatdma_device * ioat_dma)1059 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma)
1060 {
1061 struct dma_device *dma;
1062 struct dma_chan *c;
1063 struct ioatdma_chan *ioat_chan;
1064 u32 errmask;
1065
1066 dma = &ioat_dma->dma_dev;
1067
1068 /*
1069 * if we have descriptor write back error status, we mask the
1070 * error interrupts
1071 */
1072 if (ioat_dma->cap & IOAT_CAP_DWBES) {
1073 list_for_each_entry(c, &dma->channels, device_node) {
1074 ioat_chan = to_ioat_chan(c);
1075 errmask = readl(ioat_chan->reg_base +
1076 IOAT_CHANERR_MASK_OFFSET);
1077 errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR |
1078 IOAT_CHANERR_XOR_Q_ERR;
1079 writel(errmask, ioat_chan->reg_base +
1080 IOAT_CHANERR_MASK_OFFSET);
1081 }
1082 }
1083 }
1084
ioat3_dma_probe(struct ioatdma_device * ioat_dma,int dca)1085 static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca)
1086 {
1087 struct pci_dev *pdev = ioat_dma->pdev;
1088 int dca_en = system_has_dca_enabled(pdev);
1089 struct dma_device *dma;
1090 struct dma_chan *c;
1091 struct ioatdma_chan *ioat_chan;
1092 bool is_raid_device = false;
1093 int err;
1094
1095 dma = &ioat_dma->dma_dev;
1096 dma->device_prep_dma_memcpy = ioat_dma_prep_memcpy_lock;
1097 dma->device_issue_pending = ioat_issue_pending;
1098 dma->device_alloc_chan_resources = ioat_alloc_chan_resources;
1099 dma->device_free_chan_resources = ioat_free_chan_resources;
1100
1101 dma_cap_set(DMA_INTERRUPT, dma->cap_mask);
1102 dma->device_prep_dma_interrupt = ioat_prep_interrupt_lock;
1103
1104 ioat_dma->cap = readl(ioat_dma->reg_base + IOAT_DMA_CAP_OFFSET);
1105
1106 if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev))
1107 ioat_dma->cap &=
1108 ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS);
1109
1110 /* dca is incompatible with raid operations */
1111 if (dca_en && (ioat_dma->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ)))
1112 ioat_dma->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ);
1113
1114 if (ioat_dma->cap & IOAT_CAP_XOR) {
1115 is_raid_device = true;
1116 dma->max_xor = 8;
1117
1118 dma_cap_set(DMA_XOR, dma->cap_mask);
1119 dma->device_prep_dma_xor = ioat_prep_xor;
1120
1121 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1122 dma->device_prep_dma_xor_val = ioat_prep_xor_val;
1123 }
1124
1125 if (ioat_dma->cap & IOAT_CAP_PQ) {
1126 is_raid_device = true;
1127
1128 dma->device_prep_dma_pq = ioat_prep_pq;
1129 dma->device_prep_dma_pq_val = ioat_prep_pq_val;
1130 dma_cap_set(DMA_PQ, dma->cap_mask);
1131 dma_cap_set(DMA_PQ_VAL, dma->cap_mask);
1132
1133 if (ioat_dma->cap & IOAT_CAP_RAID16SS)
1134 dma_set_maxpq(dma, 16, 0);
1135 else
1136 dma_set_maxpq(dma, 8, 0);
1137
1138 if (!(ioat_dma->cap & IOAT_CAP_XOR)) {
1139 dma->device_prep_dma_xor = ioat_prep_pqxor;
1140 dma->device_prep_dma_xor_val = ioat_prep_pqxor_val;
1141 dma_cap_set(DMA_XOR, dma->cap_mask);
1142 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1143
1144 if (ioat_dma->cap & IOAT_CAP_RAID16SS)
1145 dma->max_xor = 16;
1146 else
1147 dma->max_xor = 8;
1148 }
1149 }
1150
1151 dma->device_tx_status = ioat_tx_status;
1152
1153 /* starting with CB3.3 super extended descriptors are supported */
1154 if (ioat_dma->cap & IOAT_CAP_RAID16SS) {
1155 char pool_name[14];
1156 int i;
1157
1158 for (i = 0; i < MAX_SED_POOLS; i++) {
1159 snprintf(pool_name, 14, "ioat_hw%d_sed", i);
1160
1161 /* allocate SED DMA pool */
1162 ioat_dma->sed_hw_pool[i] = dmam_pool_create(pool_name,
1163 &pdev->dev,
1164 SED_SIZE * (i + 1), 64, 0);
1165 if (!ioat_dma->sed_hw_pool[i])
1166 return -ENOMEM;
1167
1168 }
1169 }
1170
1171 if (!(ioat_dma->cap & (IOAT_CAP_XOR | IOAT_CAP_PQ)))
1172 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
1173
1174 err = ioat_probe(ioat_dma);
1175 if (err)
1176 return err;
1177
1178 list_for_each_entry(c, &dma->channels, device_node) {
1179 ioat_chan = to_ioat_chan(c);
1180 writel(IOAT_DMA_DCA_ANY_CPU,
1181 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);
1182 }
1183
1184 err = ioat_register(ioat_dma);
1185 if (err)
1186 return err;
1187
1188 ioat_kobject_add(ioat_dma, &ioat_ktype);
1189
1190 if (dca)
1191 ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base);
1192
1193 return 0;
1194 }
1195
ioat_shutdown(struct pci_dev * pdev)1196 static void ioat_shutdown(struct pci_dev *pdev)
1197 {
1198 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev);
1199 struct ioatdma_chan *ioat_chan;
1200 int i;
1201
1202 if (!ioat_dma)
1203 return;
1204
1205 for (i = 0; i < IOAT_MAX_CHANS; i++) {
1206 ioat_chan = ioat_dma->idx[i];
1207 if (!ioat_chan)
1208 continue;
1209
1210 spin_lock_bh(&ioat_chan->prep_lock);
1211 set_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
1212 spin_unlock_bh(&ioat_chan->prep_lock);
1213 /*
1214 * Synchronization rule for del_timer_sync():
1215 * - The caller must not hold locks which would prevent
1216 * completion of the timer's handler.
1217 * So prep_lock cannot be held before calling it.
1218 */
1219 del_timer_sync(&ioat_chan->timer);
1220
1221 /* this should quiesce then reset */
1222 ioat_reset_hw(ioat_chan);
1223 }
1224
1225 ioat_disable_interrupts(ioat_dma);
1226 }
1227
ioat_resume(struct ioatdma_device * ioat_dma)1228 void ioat_resume(struct ioatdma_device *ioat_dma)
1229 {
1230 struct ioatdma_chan *ioat_chan;
1231 u32 chanerr;
1232 int i;
1233
1234 for (i = 0; i < IOAT_MAX_CHANS; i++) {
1235 ioat_chan = ioat_dma->idx[i];
1236 if (!ioat_chan)
1237 continue;
1238
1239 spin_lock_bh(&ioat_chan->prep_lock);
1240 clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
1241 spin_unlock_bh(&ioat_chan->prep_lock);
1242
1243 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
1244 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
1245
1246 /* no need to reset as shutdown already did that */
1247 }
1248 }
1249
1250 #define DRV_NAME "ioatdma"
1251
ioat_pcie_error_detected(struct pci_dev * pdev,enum pci_channel_state error)1252 static pci_ers_result_t ioat_pcie_error_detected(struct pci_dev *pdev,
1253 enum pci_channel_state error)
1254 {
1255 dev_dbg(&pdev->dev, "%s: PCIe AER error %d\n", DRV_NAME, error);
1256
1257 /* quiesce and block I/O */
1258 ioat_shutdown(pdev);
1259
1260 return PCI_ERS_RESULT_NEED_RESET;
1261 }
1262
ioat_pcie_error_slot_reset(struct pci_dev * pdev)1263 static pci_ers_result_t ioat_pcie_error_slot_reset(struct pci_dev *pdev)
1264 {
1265 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
1266 int err;
1267
1268 dev_dbg(&pdev->dev, "%s post reset handling\n", DRV_NAME);
1269
1270 if (pci_enable_device_mem(pdev) < 0) {
1271 dev_err(&pdev->dev,
1272 "Failed to enable PCIe device after reset.\n");
1273 result = PCI_ERS_RESULT_DISCONNECT;
1274 } else {
1275 pci_set_master(pdev);
1276 pci_restore_state(pdev);
1277 pci_save_state(pdev);
1278 pci_wake_from_d3(pdev, false);
1279 }
1280
1281 err = pci_cleanup_aer_uncorrect_error_status(pdev);
1282 if (err) {
1283 dev_err(&pdev->dev,
1284 "AER uncorrect error status clear failed: %#x\n", err);
1285 }
1286
1287 return result;
1288 }
1289
ioat_pcie_error_resume(struct pci_dev * pdev)1290 static void ioat_pcie_error_resume(struct pci_dev *pdev)
1291 {
1292 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev);
1293
1294 dev_dbg(&pdev->dev, "%s: AER handling resuming\n", DRV_NAME);
1295
1296 /* initialize and bring everything back */
1297 ioat_resume(ioat_dma);
1298 }
1299
1300 static const struct pci_error_handlers ioat_err_handler = {
1301 .error_detected = ioat_pcie_error_detected,
1302 .slot_reset = ioat_pcie_error_slot_reset,
1303 .resume = ioat_pcie_error_resume,
1304 };
1305
1306 static struct pci_driver ioat_pci_driver = {
1307 .name = DRV_NAME,
1308 .id_table = ioat_pci_tbl,
1309 .probe = ioat_pci_probe,
1310 .remove = ioat_remove,
1311 .shutdown = ioat_shutdown,
1312 .err_handler = &ioat_err_handler,
1313 };
1314
1315 static struct ioatdma_device *
alloc_ioatdma(struct pci_dev * pdev,void __iomem * iobase)1316 alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase)
1317 {
1318 struct device *dev = &pdev->dev;
1319 struct ioatdma_device *d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
1320
1321 if (!d)
1322 return NULL;
1323 d->pdev = pdev;
1324 d->reg_base = iobase;
1325 return d;
1326 }
1327
ioat_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)1328 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1329 {
1330 void __iomem * const *iomap;
1331 struct device *dev = &pdev->dev;
1332 struct ioatdma_device *device;
1333 int err;
1334
1335 err = pcim_enable_device(pdev);
1336 if (err)
1337 return err;
1338
1339 err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME);
1340 if (err)
1341 return err;
1342 iomap = pcim_iomap_table(pdev);
1343 if (!iomap)
1344 return -ENOMEM;
1345
1346 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1347 if (err)
1348 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1349 if (err)
1350 return err;
1351
1352 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1353 if (err)
1354 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1355 if (err)
1356 return err;
1357
1358 device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]);
1359 if (!device)
1360 return -ENOMEM;
1361 pci_set_master(pdev);
1362 pci_set_drvdata(pdev, device);
1363
1364 device->version = readb(device->reg_base + IOAT_VER_OFFSET);
1365 if (device->version >= IOAT_VER_3_0) {
1366 if (is_skx_ioat(pdev))
1367 device->version = IOAT_VER_3_2;
1368 err = ioat3_dma_probe(device, ioat_dca_enabled);
1369
1370 if (device->version >= IOAT_VER_3_3)
1371 pci_enable_pcie_error_reporting(pdev);
1372 } else
1373 return -ENODEV;
1374
1375 if (err) {
1376 dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n");
1377 pci_disable_pcie_error_reporting(pdev);
1378 return -ENODEV;
1379 }
1380
1381 return 0;
1382 }
1383
ioat_remove(struct pci_dev * pdev)1384 static void ioat_remove(struct pci_dev *pdev)
1385 {
1386 struct ioatdma_device *device = pci_get_drvdata(pdev);
1387
1388 if (!device)
1389 return;
1390
1391 dev_err(&pdev->dev, "Removing dma and dca services\n");
1392 if (device->dca) {
1393 unregister_dca_provider(device->dca, &pdev->dev);
1394 free_dca_provider(device->dca);
1395 device->dca = NULL;
1396 }
1397
1398 pci_disable_pcie_error_reporting(pdev);
1399 ioat_dma_remove(device);
1400 }
1401
ioat_init_module(void)1402 static int __init ioat_init_module(void)
1403 {
1404 int err = -ENOMEM;
1405
1406 pr_info("%s: Intel(R) QuickData Technology Driver %s\n",
1407 DRV_NAME, IOAT_DMA_VERSION);
1408
1409 ioat_cache = kmem_cache_create("ioat", sizeof(struct ioat_ring_ent),
1410 0, SLAB_HWCACHE_ALIGN, NULL);
1411 if (!ioat_cache)
1412 return -ENOMEM;
1413
1414 ioat_sed_cache = KMEM_CACHE(ioat_sed_ent, 0);
1415 if (!ioat_sed_cache)
1416 goto err_ioat_cache;
1417
1418 err = pci_register_driver(&ioat_pci_driver);
1419 if (err)
1420 goto err_ioat3_cache;
1421
1422 return 0;
1423
1424 err_ioat3_cache:
1425 kmem_cache_destroy(ioat_sed_cache);
1426
1427 err_ioat_cache:
1428 kmem_cache_destroy(ioat_cache);
1429
1430 return err;
1431 }
1432 module_init(ioat_init_module);
1433
ioat_exit_module(void)1434 static void __exit ioat_exit_module(void)
1435 {
1436 pci_unregister_driver(&ioat_pci_driver);
1437 kmem_cache_destroy(ioat_cache);
1438 }
1439 module_exit(ioat_exit_module);
1440