1 /*
2 * Intel I/OAT DMA Linux driver
3 * Copyright(c) 2004 - 2015 Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in
15 * the file called "COPYING".
16 *
17 */
18
19 /*
20 * This driver supports an Intel I/OAT DMA engine, which does asynchronous
21 * copy operations.
22 */
23
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/slab.h>
27 #include <linux/pci.h>
28 #include <linux/interrupt.h>
29 #include <linux/dmaengine.h>
30 #include <linux/delay.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/workqueue.h>
33 #include <linux/prefetch.h>
34 #include "dma.h"
35 #include "registers.h"
36 #include "hw.h"
37
38 #include "../dmaengine.h"
39
40 static void ioat_eh(struct ioatdma_chan *ioat_chan);
41
42 /**
43 * ioat_dma_do_interrupt - handler used for single vector interrupt mode
44 * @irq: interrupt id
45 * @data: interrupt data
46 */
ioat_dma_do_interrupt(int irq,void * data)47 irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
48 {
49 struct ioatdma_device *instance = data;
50 struct ioatdma_chan *ioat_chan;
51 unsigned long attnstatus;
52 int bit;
53 u8 intrctrl;
54
55 intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
56
57 if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
58 return IRQ_NONE;
59
60 if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
61 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
62 return IRQ_NONE;
63 }
64
65 attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
66 for_each_set_bit(bit, &attnstatus, BITS_PER_LONG) {
67 ioat_chan = ioat_chan_by_index(instance, bit);
68 if (test_bit(IOAT_RUN, &ioat_chan->state))
69 tasklet_schedule(&ioat_chan->cleanup_task);
70 }
71
72 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
73 return IRQ_HANDLED;
74 }
75
76 /**
77 * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
78 * @irq: interrupt id
79 * @data: interrupt data
80 */
ioat_dma_do_interrupt_msix(int irq,void * data)81 irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
82 {
83 struct ioatdma_chan *ioat_chan = data;
84
85 if (test_bit(IOAT_RUN, &ioat_chan->state))
86 tasklet_schedule(&ioat_chan->cleanup_task);
87
88 return IRQ_HANDLED;
89 }
90
ioat_stop(struct ioatdma_chan * ioat_chan)91 void ioat_stop(struct ioatdma_chan *ioat_chan)
92 {
93 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;
94 struct pci_dev *pdev = ioat_dma->pdev;
95 int chan_id = chan_num(ioat_chan);
96 struct msix_entry *msix;
97
98 /* 1/ stop irq from firing tasklets
99 * 2/ stop the tasklet from re-arming irqs
100 */
101 clear_bit(IOAT_RUN, &ioat_chan->state);
102
103 /* flush inflight interrupts */
104 switch (ioat_dma->irq_mode) {
105 case IOAT_MSIX:
106 msix = &ioat_dma->msix_entries[chan_id];
107 synchronize_irq(msix->vector);
108 break;
109 case IOAT_MSI:
110 case IOAT_INTX:
111 synchronize_irq(pdev->irq);
112 break;
113 default:
114 break;
115 }
116
117 /* flush inflight timers */
118 del_timer_sync(&ioat_chan->timer);
119
120 /* flush inflight tasklet runs */
121 tasklet_kill(&ioat_chan->cleanup_task);
122
123 /* final cleanup now that everything is quiesced and can't re-arm */
124 ioat_cleanup_event((unsigned long)&ioat_chan->dma_chan);
125 }
126
__ioat_issue_pending(struct ioatdma_chan * ioat_chan)127 static void __ioat_issue_pending(struct ioatdma_chan *ioat_chan)
128 {
129 ioat_chan->dmacount += ioat_ring_pending(ioat_chan);
130 ioat_chan->issued = ioat_chan->head;
131 writew(ioat_chan->dmacount,
132 ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
133 dev_dbg(to_dev(ioat_chan),
134 "%s: head: %#x tail: %#x issued: %#x count: %#x\n",
135 __func__, ioat_chan->head, ioat_chan->tail,
136 ioat_chan->issued, ioat_chan->dmacount);
137 }
138
ioat_issue_pending(struct dma_chan * c)139 void ioat_issue_pending(struct dma_chan *c)
140 {
141 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
142
143 if (ioat_ring_pending(ioat_chan)) {
144 spin_lock_bh(&ioat_chan->prep_lock);
145 __ioat_issue_pending(ioat_chan);
146 spin_unlock_bh(&ioat_chan->prep_lock);
147 }
148 }
149
150 /**
151 * ioat_update_pending - log pending descriptors
152 * @ioat: ioat+ channel
153 *
154 * Check if the number of unsubmitted descriptors has exceeded the
155 * watermark. Called with prep_lock held
156 */
ioat_update_pending(struct ioatdma_chan * ioat_chan)157 static void ioat_update_pending(struct ioatdma_chan *ioat_chan)
158 {
159 if (ioat_ring_pending(ioat_chan) > ioat_pending_level)
160 __ioat_issue_pending(ioat_chan);
161 }
162
__ioat_start_null_desc(struct ioatdma_chan * ioat_chan)163 static void __ioat_start_null_desc(struct ioatdma_chan *ioat_chan)
164 {
165 struct ioat_ring_ent *desc;
166 struct ioat_dma_descriptor *hw;
167
168 if (ioat_ring_space(ioat_chan) < 1) {
169 dev_err(to_dev(ioat_chan),
170 "Unable to start null desc - ring full\n");
171 return;
172 }
173
174 dev_dbg(to_dev(ioat_chan),
175 "%s: head: %#x tail: %#x issued: %#x\n",
176 __func__, ioat_chan->head, ioat_chan->tail, ioat_chan->issued);
177 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head);
178
179 hw = desc->hw;
180 hw->ctl = 0;
181 hw->ctl_f.null = 1;
182 hw->ctl_f.int_en = 1;
183 hw->ctl_f.compl_write = 1;
184 /* set size to non-zero value (channel returns error when size is 0) */
185 hw->size = NULL_DESC_BUFFER_SIZE;
186 hw->src_addr = 0;
187 hw->dst_addr = 0;
188 async_tx_ack(&desc->txd);
189 ioat_set_chainaddr(ioat_chan, desc->txd.phys);
190 dump_desc_dbg(ioat_chan, desc);
191 /* make sure descriptors are written before we submit */
192 wmb();
193 ioat_chan->head += 1;
194 __ioat_issue_pending(ioat_chan);
195 }
196
ioat_start_null_desc(struct ioatdma_chan * ioat_chan)197 void ioat_start_null_desc(struct ioatdma_chan *ioat_chan)
198 {
199 spin_lock_bh(&ioat_chan->prep_lock);
200 if (!test_bit(IOAT_CHAN_DOWN, &ioat_chan->state))
201 __ioat_start_null_desc(ioat_chan);
202 spin_unlock_bh(&ioat_chan->prep_lock);
203 }
204
__ioat_restart_chan(struct ioatdma_chan * ioat_chan)205 static void __ioat_restart_chan(struct ioatdma_chan *ioat_chan)
206 {
207 /* set the tail to be re-issued */
208 ioat_chan->issued = ioat_chan->tail;
209 ioat_chan->dmacount = 0;
210 mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT);
211
212 dev_dbg(to_dev(ioat_chan),
213 "%s: head: %#x tail: %#x issued: %#x count: %#x\n",
214 __func__, ioat_chan->head, ioat_chan->tail,
215 ioat_chan->issued, ioat_chan->dmacount);
216
217 if (ioat_ring_pending(ioat_chan)) {
218 struct ioat_ring_ent *desc;
219
220 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail);
221 ioat_set_chainaddr(ioat_chan, desc->txd.phys);
222 __ioat_issue_pending(ioat_chan);
223 } else
224 __ioat_start_null_desc(ioat_chan);
225 }
226
ioat_quiesce(struct ioatdma_chan * ioat_chan,unsigned long tmo)227 static int ioat_quiesce(struct ioatdma_chan *ioat_chan, unsigned long tmo)
228 {
229 unsigned long end = jiffies + tmo;
230 int err = 0;
231 u32 status;
232
233 status = ioat_chansts(ioat_chan);
234 if (is_ioat_active(status) || is_ioat_idle(status))
235 ioat_suspend(ioat_chan);
236 while (is_ioat_active(status) || is_ioat_idle(status)) {
237 if (tmo && time_after(jiffies, end)) {
238 err = -ETIMEDOUT;
239 break;
240 }
241 status = ioat_chansts(ioat_chan);
242 cpu_relax();
243 }
244
245 return err;
246 }
247
ioat_reset_sync(struct ioatdma_chan * ioat_chan,unsigned long tmo)248 static int ioat_reset_sync(struct ioatdma_chan *ioat_chan, unsigned long tmo)
249 {
250 unsigned long end = jiffies + tmo;
251 int err = 0;
252
253 ioat_reset(ioat_chan);
254 while (ioat_reset_pending(ioat_chan)) {
255 if (end && time_after(jiffies, end)) {
256 err = -ETIMEDOUT;
257 break;
258 }
259 cpu_relax();
260 }
261
262 return err;
263 }
264
ioat_tx_submit_unlock(struct dma_async_tx_descriptor * tx)265 static dma_cookie_t ioat_tx_submit_unlock(struct dma_async_tx_descriptor *tx)
266 __releases(&ioat_chan->prep_lock)
267 {
268 struct dma_chan *c = tx->chan;
269 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
270 dma_cookie_t cookie;
271
272 cookie = dma_cookie_assign(tx);
273 dev_dbg(to_dev(ioat_chan), "%s: cookie: %d\n", __func__, cookie);
274
275 if (!test_and_set_bit(IOAT_CHAN_ACTIVE, &ioat_chan->state))
276 mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT);
277
278 /* make descriptor updates visible before advancing ioat->head,
279 * this is purposefully not smp_wmb() since we are also
280 * publishing the descriptor updates to a dma device
281 */
282 wmb();
283
284 ioat_chan->head += ioat_chan->produce;
285
286 ioat_update_pending(ioat_chan);
287 spin_unlock_bh(&ioat_chan->prep_lock);
288
289 return cookie;
290 }
291
292 static struct ioat_ring_ent *
ioat_alloc_ring_ent(struct dma_chan * chan,gfp_t flags)293 ioat_alloc_ring_ent(struct dma_chan *chan, gfp_t flags)
294 {
295 struct ioat_dma_descriptor *hw;
296 struct ioat_ring_ent *desc;
297 struct ioatdma_device *ioat_dma;
298 dma_addr_t phys;
299
300 ioat_dma = to_ioatdma_device(chan->device);
301 hw = pci_pool_alloc(ioat_dma->dma_pool, flags, &phys);
302 if (!hw)
303 return NULL;
304 memset(hw, 0, sizeof(*hw));
305
306 desc = kmem_cache_zalloc(ioat_cache, flags);
307 if (!desc) {
308 pci_pool_free(ioat_dma->dma_pool, hw, phys);
309 return NULL;
310 }
311
312 dma_async_tx_descriptor_init(&desc->txd, chan);
313 desc->txd.tx_submit = ioat_tx_submit_unlock;
314 desc->hw = hw;
315 desc->txd.phys = phys;
316 return desc;
317 }
318
ioat_free_ring_ent(struct ioat_ring_ent * desc,struct dma_chan * chan)319 void ioat_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan)
320 {
321 struct ioatdma_device *ioat_dma;
322
323 ioat_dma = to_ioatdma_device(chan->device);
324 pci_pool_free(ioat_dma->dma_pool, desc->hw, desc->txd.phys);
325 kmem_cache_free(ioat_cache, desc);
326 }
327
328 struct ioat_ring_ent **
ioat_alloc_ring(struct dma_chan * c,int order,gfp_t flags)329 ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags)
330 {
331 struct ioat_ring_ent **ring;
332 int descs = 1 << order;
333 int i;
334
335 if (order > ioat_get_max_alloc_order())
336 return NULL;
337
338 /* allocate the array to hold the software ring */
339 ring = kcalloc(descs, sizeof(*ring), flags);
340 if (!ring)
341 return NULL;
342 for (i = 0; i < descs; i++) {
343 ring[i] = ioat_alloc_ring_ent(c, flags);
344 if (!ring[i]) {
345 while (i--)
346 ioat_free_ring_ent(ring[i], c);
347 kfree(ring);
348 return NULL;
349 }
350 set_desc_id(ring[i], i);
351 }
352
353 /* link descs */
354 for (i = 0; i < descs-1; i++) {
355 struct ioat_ring_ent *next = ring[i+1];
356 struct ioat_dma_descriptor *hw = ring[i]->hw;
357
358 hw->next = next->txd.phys;
359 }
360 ring[i]->hw->next = ring[0]->txd.phys;
361
362 return ring;
363 }
364
reshape_ring(struct ioatdma_chan * ioat_chan,int order)365 static bool reshape_ring(struct ioatdma_chan *ioat_chan, int order)
366 {
367 /* reshape differs from normal ring allocation in that we want
368 * to allocate a new software ring while only
369 * extending/truncating the hardware ring
370 */
371 struct dma_chan *c = &ioat_chan->dma_chan;
372 const u32 curr_size = ioat_ring_size(ioat_chan);
373 const u16 active = ioat_ring_active(ioat_chan);
374 const u32 new_size = 1 << order;
375 struct ioat_ring_ent **ring;
376 u32 i;
377
378 if (order > ioat_get_max_alloc_order())
379 return false;
380
381 /* double check that we have at least 1 free descriptor */
382 if (active == curr_size)
383 return false;
384
385 /* when shrinking, verify that we can hold the current active
386 * set in the new ring
387 */
388 if (active >= new_size)
389 return false;
390
391 /* allocate the array to hold the software ring */
392 ring = kcalloc(new_size, sizeof(*ring), GFP_NOWAIT);
393 if (!ring)
394 return false;
395
396 /* allocate/trim descriptors as needed */
397 if (new_size > curr_size) {
398 /* copy current descriptors to the new ring */
399 for (i = 0; i < curr_size; i++) {
400 u16 curr_idx = (ioat_chan->tail+i) & (curr_size-1);
401 u16 new_idx = (ioat_chan->tail+i) & (new_size-1);
402
403 ring[new_idx] = ioat_chan->ring[curr_idx];
404 set_desc_id(ring[new_idx], new_idx);
405 }
406
407 /* add new descriptors to the ring */
408 for (i = curr_size; i < new_size; i++) {
409 u16 new_idx = (ioat_chan->tail+i) & (new_size-1);
410
411 ring[new_idx] = ioat_alloc_ring_ent(c, GFP_NOWAIT);
412 if (!ring[new_idx]) {
413 while (i--) {
414 u16 new_idx = (ioat_chan->tail+i) &
415 (new_size-1);
416
417 ioat_free_ring_ent(ring[new_idx], c);
418 }
419 kfree(ring);
420 return false;
421 }
422 set_desc_id(ring[new_idx], new_idx);
423 }
424
425 /* hw link new descriptors */
426 for (i = curr_size-1; i < new_size; i++) {
427 u16 new_idx = (ioat_chan->tail+i) & (new_size-1);
428 struct ioat_ring_ent *next =
429 ring[(new_idx+1) & (new_size-1)];
430 struct ioat_dma_descriptor *hw = ring[new_idx]->hw;
431
432 hw->next = next->txd.phys;
433 }
434 } else {
435 struct ioat_dma_descriptor *hw;
436 struct ioat_ring_ent *next;
437
438 /* copy current descriptors to the new ring, dropping the
439 * removed descriptors
440 */
441 for (i = 0; i < new_size; i++) {
442 u16 curr_idx = (ioat_chan->tail+i) & (curr_size-1);
443 u16 new_idx = (ioat_chan->tail+i) & (new_size-1);
444
445 ring[new_idx] = ioat_chan->ring[curr_idx];
446 set_desc_id(ring[new_idx], new_idx);
447 }
448
449 /* free deleted descriptors */
450 for (i = new_size; i < curr_size; i++) {
451 struct ioat_ring_ent *ent;
452
453 ent = ioat_get_ring_ent(ioat_chan, ioat_chan->tail+i);
454 ioat_free_ring_ent(ent, c);
455 }
456
457 /* fix up hardware ring */
458 hw = ring[(ioat_chan->tail+new_size-1) & (new_size-1)]->hw;
459 next = ring[(ioat_chan->tail+new_size) & (new_size-1)];
460 hw->next = next->txd.phys;
461 }
462
463 dev_dbg(to_dev(ioat_chan), "%s: allocated %d descriptors\n",
464 __func__, new_size);
465
466 kfree(ioat_chan->ring);
467 ioat_chan->ring = ring;
468 ioat_chan->alloc_order = order;
469
470 return true;
471 }
472
473 /**
474 * ioat_check_space_lock - verify space and grab ring producer lock
475 * @ioat: ioat,3 channel (ring) to operate on
476 * @num_descs: allocation length
477 */
ioat_check_space_lock(struct ioatdma_chan * ioat_chan,int num_descs)478 int ioat_check_space_lock(struct ioatdma_chan *ioat_chan, int num_descs)
479 __acquires(&ioat_chan->prep_lock)
480 {
481 bool retry;
482
483 retry:
484 spin_lock_bh(&ioat_chan->prep_lock);
485 /* never allow the last descriptor to be consumed, we need at
486 * least one free at all times to allow for on-the-fly ring
487 * resizing.
488 */
489 if (likely(ioat_ring_space(ioat_chan) > num_descs)) {
490 dev_dbg(to_dev(ioat_chan), "%s: num_descs: %d (%x:%x:%x)\n",
491 __func__, num_descs, ioat_chan->head,
492 ioat_chan->tail, ioat_chan->issued);
493 ioat_chan->produce = num_descs;
494 return 0; /* with ioat->prep_lock held */
495 }
496 retry = test_and_set_bit(IOAT_RESHAPE_PENDING, &ioat_chan->state);
497 spin_unlock_bh(&ioat_chan->prep_lock);
498
499 /* is another cpu already trying to expand the ring? */
500 if (retry)
501 goto retry;
502
503 spin_lock_bh(&ioat_chan->cleanup_lock);
504 spin_lock_bh(&ioat_chan->prep_lock);
505 retry = reshape_ring(ioat_chan, ioat_chan->alloc_order + 1);
506 clear_bit(IOAT_RESHAPE_PENDING, &ioat_chan->state);
507 spin_unlock_bh(&ioat_chan->prep_lock);
508 spin_unlock_bh(&ioat_chan->cleanup_lock);
509
510 /* if we were able to expand the ring retry the allocation */
511 if (retry)
512 goto retry;
513
514 dev_dbg_ratelimited(to_dev(ioat_chan),
515 "%s: ring full! num_descs: %d (%x:%x:%x)\n",
516 __func__, num_descs, ioat_chan->head,
517 ioat_chan->tail, ioat_chan->issued);
518
519 /* progress reclaim in the allocation failure case we may be
520 * called under bh_disabled so we need to trigger the timer
521 * event directly
522 */
523 if (time_is_before_jiffies(ioat_chan->timer.expires)
524 && timer_pending(&ioat_chan->timer)) {
525 mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT);
526 ioat_timer_event((unsigned long)ioat_chan);
527 }
528
529 return -ENOMEM;
530 }
531
desc_has_ext(struct ioat_ring_ent * desc)532 static bool desc_has_ext(struct ioat_ring_ent *desc)
533 {
534 struct ioat_dma_descriptor *hw = desc->hw;
535
536 if (hw->ctl_f.op == IOAT_OP_XOR ||
537 hw->ctl_f.op == IOAT_OP_XOR_VAL) {
538 struct ioat_xor_descriptor *xor = desc->xor;
539
540 if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5)
541 return true;
542 } else if (hw->ctl_f.op == IOAT_OP_PQ ||
543 hw->ctl_f.op == IOAT_OP_PQ_VAL) {
544 struct ioat_pq_descriptor *pq = desc->pq;
545
546 if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3)
547 return true;
548 }
549
550 return false;
551 }
552
553 static void
ioat_free_sed(struct ioatdma_device * ioat_dma,struct ioat_sed_ent * sed)554 ioat_free_sed(struct ioatdma_device *ioat_dma, struct ioat_sed_ent *sed)
555 {
556 if (!sed)
557 return;
558
559 dma_pool_free(ioat_dma->sed_hw_pool[sed->hw_pool], sed->hw, sed->dma);
560 kmem_cache_free(ioat_sed_cache, sed);
561 }
562
ioat_get_current_completion(struct ioatdma_chan * ioat_chan)563 static u64 ioat_get_current_completion(struct ioatdma_chan *ioat_chan)
564 {
565 u64 phys_complete;
566 u64 completion;
567
568 completion = *ioat_chan->completion;
569 phys_complete = ioat_chansts_to_addr(completion);
570
571 dev_dbg(to_dev(ioat_chan), "%s: phys_complete: %#llx\n", __func__,
572 (unsigned long long) phys_complete);
573
574 return phys_complete;
575 }
576
ioat_cleanup_preamble(struct ioatdma_chan * ioat_chan,u64 * phys_complete)577 static bool ioat_cleanup_preamble(struct ioatdma_chan *ioat_chan,
578 u64 *phys_complete)
579 {
580 *phys_complete = ioat_get_current_completion(ioat_chan);
581 if (*phys_complete == ioat_chan->last_completion)
582 return false;
583
584 clear_bit(IOAT_COMPLETION_ACK, &ioat_chan->state);
585 mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT);
586
587 return true;
588 }
589
590 static void
desc_get_errstat(struct ioatdma_chan * ioat_chan,struct ioat_ring_ent * desc)591 desc_get_errstat(struct ioatdma_chan *ioat_chan, struct ioat_ring_ent *desc)
592 {
593 struct ioat_dma_descriptor *hw = desc->hw;
594
595 switch (hw->ctl_f.op) {
596 case IOAT_OP_PQ_VAL:
597 case IOAT_OP_PQ_VAL_16S:
598 {
599 struct ioat_pq_descriptor *pq = desc->pq;
600
601 /* check if there's error written */
602 if (!pq->dwbes_f.wbes)
603 return;
604
605 /* need to set a chanerr var for checking to clear later */
606
607 if (pq->dwbes_f.p_val_err)
608 *desc->result |= SUM_CHECK_P_RESULT;
609
610 if (pq->dwbes_f.q_val_err)
611 *desc->result |= SUM_CHECK_Q_RESULT;
612
613 return;
614 }
615 default:
616 return;
617 }
618 }
619
620 /**
621 * __cleanup - reclaim used descriptors
622 * @ioat: channel (ring) to clean
623 */
__cleanup(struct ioatdma_chan * ioat_chan,dma_addr_t phys_complete)624 static void __cleanup(struct ioatdma_chan *ioat_chan, dma_addr_t phys_complete)
625 {
626 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;
627 struct ioat_ring_ent *desc;
628 bool seen_current = false;
629 int idx = ioat_chan->tail, i;
630 u16 active;
631
632 dev_dbg(to_dev(ioat_chan), "%s: head: %#x tail: %#x issued: %#x\n",
633 __func__, ioat_chan->head, ioat_chan->tail, ioat_chan->issued);
634
635 /*
636 * At restart of the channel, the completion address and the
637 * channel status will be 0 due to starting a new chain. Since
638 * it's new chain and the first descriptor "fails", there is
639 * nothing to clean up. We do not want to reap the entire submitted
640 * chain due to this 0 address value and then BUG.
641 */
642 if (!phys_complete)
643 return;
644
645 active = ioat_ring_active(ioat_chan);
646 for (i = 0; i < active && !seen_current; i++) {
647 struct dma_async_tx_descriptor *tx;
648
649 smp_read_barrier_depends();
650 prefetch(ioat_get_ring_ent(ioat_chan, idx + i + 1));
651 desc = ioat_get_ring_ent(ioat_chan, idx + i);
652 dump_desc_dbg(ioat_chan, desc);
653
654 /* set err stat if we are using dwbes */
655 if (ioat_dma->cap & IOAT_CAP_DWBES)
656 desc_get_errstat(ioat_chan, desc);
657
658 tx = &desc->txd;
659 if (tx->cookie) {
660 dma_cookie_complete(tx);
661 dma_descriptor_unmap(tx);
662 if (tx->callback) {
663 tx->callback(tx->callback_param);
664 tx->callback = NULL;
665 }
666 }
667
668 if (tx->phys == phys_complete)
669 seen_current = true;
670
671 /* skip extended descriptors */
672 if (desc_has_ext(desc)) {
673 BUG_ON(i + 1 >= active);
674 i++;
675 }
676
677 /* cleanup super extended descriptors */
678 if (desc->sed) {
679 ioat_free_sed(ioat_dma, desc->sed);
680 desc->sed = NULL;
681 }
682 }
683
684 /* finish all descriptor reads before incrementing tail */
685 smp_mb();
686 ioat_chan->tail = idx + i;
687 /* no active descs have written a completion? */
688 BUG_ON(active && !seen_current);
689 ioat_chan->last_completion = phys_complete;
690
691 if (active - i == 0) {
692 dev_dbg(to_dev(ioat_chan), "%s: cancel completion timeout\n",
693 __func__);
694 mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT);
695 }
696
697 /* 5 microsecond delay per pending descriptor */
698 writew(min((5 * (active - i)), IOAT_INTRDELAY_MASK),
699 ioat_chan->ioat_dma->reg_base + IOAT_INTRDELAY_OFFSET);
700 }
701
ioat_cleanup(struct ioatdma_chan * ioat_chan)702 static void ioat_cleanup(struct ioatdma_chan *ioat_chan)
703 {
704 u64 phys_complete;
705
706 spin_lock_bh(&ioat_chan->cleanup_lock);
707
708 if (ioat_cleanup_preamble(ioat_chan, &phys_complete))
709 __cleanup(ioat_chan, phys_complete);
710
711 if (is_ioat_halted(*ioat_chan->completion)) {
712 u32 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
713
714 if (chanerr & IOAT_CHANERR_HANDLE_MASK) {
715 mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT);
716 ioat_eh(ioat_chan);
717 }
718 }
719
720 spin_unlock_bh(&ioat_chan->cleanup_lock);
721 }
722
ioat_cleanup_event(unsigned long data)723 void ioat_cleanup_event(unsigned long data)
724 {
725 struct ioatdma_chan *ioat_chan = to_ioat_chan((void *)data);
726
727 ioat_cleanup(ioat_chan);
728 if (!test_bit(IOAT_RUN, &ioat_chan->state))
729 return;
730 writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
731 }
732
ioat_restart_channel(struct ioatdma_chan * ioat_chan)733 static void ioat_restart_channel(struct ioatdma_chan *ioat_chan)
734 {
735 u64 phys_complete;
736
737 ioat_quiesce(ioat_chan, 0);
738 if (ioat_cleanup_preamble(ioat_chan, &phys_complete))
739 __cleanup(ioat_chan, phys_complete);
740
741 __ioat_restart_chan(ioat_chan);
742 }
743
ioat_eh(struct ioatdma_chan * ioat_chan)744 static void ioat_eh(struct ioatdma_chan *ioat_chan)
745 {
746 struct pci_dev *pdev = to_pdev(ioat_chan);
747 struct ioat_dma_descriptor *hw;
748 struct dma_async_tx_descriptor *tx;
749 u64 phys_complete;
750 struct ioat_ring_ent *desc;
751 u32 err_handled = 0;
752 u32 chanerr_int;
753 u32 chanerr;
754
755 /* cleanup so tail points to descriptor that caused the error */
756 if (ioat_cleanup_preamble(ioat_chan, &phys_complete))
757 __cleanup(ioat_chan, phys_complete);
758
759 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
760 pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr_int);
761
762 dev_dbg(to_dev(ioat_chan), "%s: error = %x:%x\n",
763 __func__, chanerr, chanerr_int);
764
765 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail);
766 hw = desc->hw;
767 dump_desc_dbg(ioat_chan, desc);
768
769 switch (hw->ctl_f.op) {
770 case IOAT_OP_XOR_VAL:
771 if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) {
772 *desc->result |= SUM_CHECK_P_RESULT;
773 err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR;
774 }
775 break;
776 case IOAT_OP_PQ_VAL:
777 case IOAT_OP_PQ_VAL_16S:
778 if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) {
779 *desc->result |= SUM_CHECK_P_RESULT;
780 err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR;
781 }
782 if (chanerr & IOAT_CHANERR_XOR_Q_ERR) {
783 *desc->result |= SUM_CHECK_Q_RESULT;
784 err_handled |= IOAT_CHANERR_XOR_Q_ERR;
785 }
786 break;
787 }
788
789 /* fault on unhandled error or spurious halt */
790 if (chanerr ^ err_handled || chanerr == 0) {
791 dev_err(to_dev(ioat_chan), "%s: fatal error (%x:%x)\n",
792 __func__, chanerr, err_handled);
793 BUG();
794 } else { /* cleanup the faulty descriptor */
795 tx = &desc->txd;
796 if (tx->cookie) {
797 dma_cookie_complete(tx);
798 dma_descriptor_unmap(tx);
799 if (tx->callback) {
800 tx->callback(tx->callback_param);
801 tx->callback = NULL;
802 }
803 }
804 }
805
806 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
807 pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr_int);
808
809 /* mark faulting descriptor as complete */
810 *ioat_chan->completion = desc->txd.phys;
811
812 spin_lock_bh(&ioat_chan->prep_lock);
813 ioat_restart_channel(ioat_chan);
814 spin_unlock_bh(&ioat_chan->prep_lock);
815 }
816
check_active(struct ioatdma_chan * ioat_chan)817 static void check_active(struct ioatdma_chan *ioat_chan)
818 {
819 if (ioat_ring_active(ioat_chan)) {
820 mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT);
821 return;
822 }
823
824 if (test_and_clear_bit(IOAT_CHAN_ACTIVE, &ioat_chan->state))
825 mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT);
826 else if (ioat_chan->alloc_order > ioat_get_alloc_order()) {
827 /* if the ring is idle, empty, and oversized try to step
828 * down the size
829 */
830 reshape_ring(ioat_chan, ioat_chan->alloc_order - 1);
831
832 /* keep shrinking until we get back to our minimum
833 * default size
834 */
835 if (ioat_chan->alloc_order > ioat_get_alloc_order())
836 mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT);
837 }
838
839 }
840
ioat_timer_event(unsigned long data)841 void ioat_timer_event(unsigned long data)
842 {
843 struct ioatdma_chan *ioat_chan = to_ioat_chan((void *)data);
844 dma_addr_t phys_complete;
845 u64 status;
846
847 status = ioat_chansts(ioat_chan);
848
849 /* when halted due to errors check for channel
850 * programming errors before advancing the completion state
851 */
852 if (is_ioat_halted(status)) {
853 u32 chanerr;
854
855 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
856 dev_err(to_dev(ioat_chan), "%s: Channel halted (%x)\n",
857 __func__, chanerr);
858 if (test_bit(IOAT_RUN, &ioat_chan->state))
859 BUG_ON(is_ioat_bug(chanerr));
860 else /* we never got off the ground */
861 return;
862 }
863
864 /* if we haven't made progress and we have already
865 * acknowledged a pending completion once, then be more
866 * forceful with a restart
867 */
868 spin_lock_bh(&ioat_chan->cleanup_lock);
869 if (ioat_cleanup_preamble(ioat_chan, &phys_complete))
870 __cleanup(ioat_chan, phys_complete);
871 else if (test_bit(IOAT_COMPLETION_ACK, &ioat_chan->state)) {
872 spin_lock_bh(&ioat_chan->prep_lock);
873 ioat_restart_channel(ioat_chan);
874 spin_unlock_bh(&ioat_chan->prep_lock);
875 spin_unlock_bh(&ioat_chan->cleanup_lock);
876 return;
877 } else {
878 set_bit(IOAT_COMPLETION_ACK, &ioat_chan->state);
879 mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT);
880 }
881
882
883 if (ioat_ring_active(ioat_chan))
884 mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT);
885 else {
886 spin_lock_bh(&ioat_chan->prep_lock);
887 check_active(ioat_chan);
888 spin_unlock_bh(&ioat_chan->prep_lock);
889 }
890 spin_unlock_bh(&ioat_chan->cleanup_lock);
891 }
892
893 enum dma_status
ioat_tx_status(struct dma_chan * c,dma_cookie_t cookie,struct dma_tx_state * txstate)894 ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie,
895 struct dma_tx_state *txstate)
896 {
897 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
898 enum dma_status ret;
899
900 ret = dma_cookie_status(c, cookie, txstate);
901 if (ret == DMA_COMPLETE)
902 return ret;
903
904 ioat_cleanup(ioat_chan);
905
906 return dma_cookie_status(c, cookie, txstate);
907 }
908
ioat_irq_reinit(struct ioatdma_device * ioat_dma)909 static int ioat_irq_reinit(struct ioatdma_device *ioat_dma)
910 {
911 struct pci_dev *pdev = ioat_dma->pdev;
912 int irq = pdev->irq, i;
913
914 if (!is_bwd_ioat(pdev))
915 return 0;
916
917 switch (ioat_dma->irq_mode) {
918 case IOAT_MSIX:
919 for (i = 0; i < ioat_dma->dma_dev.chancnt; i++) {
920 struct msix_entry *msix = &ioat_dma->msix_entries[i];
921 struct ioatdma_chan *ioat_chan;
922
923 ioat_chan = ioat_chan_by_index(ioat_dma, i);
924 devm_free_irq(&pdev->dev, msix->vector, ioat_chan);
925 }
926
927 pci_disable_msix(pdev);
928 break;
929 case IOAT_MSI:
930 pci_disable_msi(pdev);
931 /* fall through */
932 case IOAT_INTX:
933 devm_free_irq(&pdev->dev, irq, ioat_dma);
934 break;
935 default:
936 return 0;
937 }
938 ioat_dma->irq_mode = IOAT_NOIRQ;
939
940 return ioat_dma_setup_interrupts(ioat_dma);
941 }
942
ioat_reset_hw(struct ioatdma_chan * ioat_chan)943 int ioat_reset_hw(struct ioatdma_chan *ioat_chan)
944 {
945 /* throw away whatever the channel was doing and get it
946 * initialized, with ioat3 specific workarounds
947 */
948 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;
949 struct pci_dev *pdev = ioat_dma->pdev;
950 u32 chanerr;
951 u16 dev_id;
952 int err;
953
954 ioat_quiesce(ioat_chan, msecs_to_jiffies(100));
955
956 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
957 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
958
959 if (ioat_dma->version < IOAT_VER_3_3) {
960 /* clear any pending errors */
961 err = pci_read_config_dword(pdev,
962 IOAT_PCI_CHANERR_INT_OFFSET, &chanerr);
963 if (err) {
964 dev_err(&pdev->dev,
965 "channel error register unreachable\n");
966 return err;
967 }
968 pci_write_config_dword(pdev,
969 IOAT_PCI_CHANERR_INT_OFFSET, chanerr);
970
971 /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
972 * (workaround for spurious config parity error after restart)
973 */
974 pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id);
975 if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) {
976 pci_write_config_dword(pdev,
977 IOAT_PCI_DMAUNCERRSTS_OFFSET,
978 0x10);
979 }
980 }
981
982 err = ioat_reset_sync(ioat_chan, msecs_to_jiffies(200));
983 if (!err)
984 err = ioat_irq_reinit(ioat_dma);
985
986 if (err)
987 dev_err(&pdev->dev, "Failed to reset: %d\n", err);
988
989 return err;
990 }
991