1 /*
2 ** ccio-dma.c:
3 ** DMA management routines for first generation cache-coherent machines.
4 ** Program U2/Uturn in "Virtual Mode" and use the I/O MMU.
5 **
6 ** (c) Copyright 2000 Grant Grundler
7 ** (c) Copyright 2000 Ryan Bradetich
8 ** (c) Copyright 2000 Hewlett-Packard Company
9 **
10 ** This program is free software; you can redistribute it and/or modify
11 ** it under the terms of the GNU General Public License as published by
12 ** the Free Software Foundation; either version 2 of the License, or
13 ** (at your option) any later version.
14 **
15 **
16 ** "Real Mode" operation refers to U2/Uturn chip operation.
17 ** U2/Uturn were designed to perform coherency checks w/o using
18 ** the I/O MMU - basically what x86 does.
19 **
20 ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at:
21 ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc
22 ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c
23 **
24 ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c.
25 **
26 ** Drawbacks of using Real Mode are:
27 ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
28 ** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute.
29 ** o Ability to do scatter/gather in HW is lost.
30 ** o Doesn't work under PCX-U/U+ machines since they didn't follow
31 ** the coherency design originally worked out. Only PCX-W does.
32 */
33
34 #include <linux/types.h>
35 #include <linux/kernel.h>
36 #include <linux/init.h>
37 #include <linux/mm.h>
38 #include <linux/spinlock.h>
39 #include <linux/slab.h>
40 #include <linux/string.h>
41 #include <linux/pci.h>
42 #include <linux/reboot.h>
43 #include <linux/proc_fs.h>
44 #include <linux/seq_file.h>
45 #include <linux/scatterlist.h>
46 #include <linux/iommu-helper.h>
47 #include <linux/export.h>
48
49 #include <asm/byteorder.h>
50 #include <asm/cache.h> /* for L1_CACHE_BYTES */
51 #include <asm/uaccess.h>
52 #include <asm/page.h>
53 #include <asm/dma.h>
54 #include <asm/io.h>
55 #include <asm/hardware.h> /* for register_module() */
56 #include <asm/parisc-device.h>
57
58 /*
59 ** Choose "ccio" since that's what HP-UX calls it.
60 ** Make it easier for folks to migrate from one to the other :^)
61 */
62 #define MODULE_NAME "ccio"
63
64 #undef DEBUG_CCIO_RES
65 #undef DEBUG_CCIO_RUN
66 #undef DEBUG_CCIO_INIT
67 #undef DEBUG_CCIO_RUN_SG
68
69 #ifdef CONFIG_PROC_FS
70 /* depends on proc fs support. But costs CPU performance. */
71 #undef CCIO_COLLECT_STATS
72 #endif
73
74 #include <asm/runway.h> /* for proc_runway_root */
75
76 #ifdef DEBUG_CCIO_INIT
77 #define DBG_INIT(x...) printk(x)
78 #else
79 #define DBG_INIT(x...)
80 #endif
81
82 #ifdef DEBUG_CCIO_RUN
83 #define DBG_RUN(x...) printk(x)
84 #else
85 #define DBG_RUN(x...)
86 #endif
87
88 #ifdef DEBUG_CCIO_RES
89 #define DBG_RES(x...) printk(x)
90 #else
91 #define DBG_RES(x...)
92 #endif
93
94 #ifdef DEBUG_CCIO_RUN_SG
95 #define DBG_RUN_SG(x...) printk(x)
96 #else
97 #define DBG_RUN_SG(x...)
98 #endif
99
100 #define CCIO_INLINE inline
101 #define WRITE_U32(value, addr) __raw_writel(value, addr)
102 #define READ_U32(addr) __raw_readl(addr)
103
104 #define U2_IOA_RUNWAY 0x580
105 #define U2_BC_GSC 0x501
106 #define UTURN_IOA_RUNWAY 0x581
107 #define UTURN_BC_GSC 0x502
108
109 #define IOA_NORMAL_MODE 0x00020080 /* IO_CONTROL to turn on CCIO */
110 #define CMD_TLB_DIRECT_WRITE 35 /* IO_COMMAND for I/O TLB Writes */
111 #define CMD_TLB_PURGE 33 /* IO_COMMAND to Purge I/O TLB entry */
112
113 struct ioa_registers {
114 /* Runway Supervisory Set */
115 int32_t unused1[12];
116 uint32_t io_command; /* Offset 12 */
117 uint32_t io_status; /* Offset 13 */
118 uint32_t io_control; /* Offset 14 */
119 int32_t unused2[1];
120
121 /* Runway Auxiliary Register Set */
122 uint32_t io_err_resp; /* Offset 0 */
123 uint32_t io_err_info; /* Offset 1 */
124 uint32_t io_err_req; /* Offset 2 */
125 uint32_t io_err_resp_hi; /* Offset 3 */
126 uint32_t io_tlb_entry_m; /* Offset 4 */
127 uint32_t io_tlb_entry_l; /* Offset 5 */
128 uint32_t unused3[1];
129 uint32_t io_pdir_base; /* Offset 7 */
130 uint32_t io_io_low_hv; /* Offset 8 */
131 uint32_t io_io_high_hv; /* Offset 9 */
132 uint32_t unused4[1];
133 uint32_t io_chain_id_mask; /* Offset 11 */
134 uint32_t unused5[2];
135 uint32_t io_io_low; /* Offset 14 */
136 uint32_t io_io_high; /* Offset 15 */
137 };
138
139 /*
140 ** IOA Registers
141 ** -------------
142 **
143 ** Runway IO_CONTROL Register (+0x38)
144 **
145 ** The Runway IO_CONTROL register controls the forwarding of transactions.
146 **
147 ** | 0 ... 13 | 14 15 | 16 ... 21 | 22 | 23 24 | 25 ... 31 |
148 ** | HV | TLB | reserved | HV | mode | reserved |
149 **
150 ** o mode field indicates the address translation of transactions
151 ** forwarded from Runway to GSC+:
152 ** Mode Name Value Definition
153 ** Off (default) 0 Opaque to matching addresses.
154 ** Include 1 Transparent for matching addresses.
155 ** Peek 3 Map matching addresses.
156 **
157 ** + "Off" mode: Runway transactions which match the I/O range
158 ** specified by the IO_IO_LOW/IO_IO_HIGH registers will be ignored.
159 ** + "Include" mode: all addresses within the I/O range specified
160 ** by the IO_IO_LOW and IO_IO_HIGH registers are transparently
161 ** forwarded. This is the I/O Adapter's normal operating mode.
162 ** + "Peek" mode: used during system configuration to initialize the
163 ** GSC+ bus. Runway Write_Shorts in the address range specified by
164 ** IO_IO_LOW and IO_IO_HIGH are forwarded through the I/O Adapter
165 ** *AND* the GSC+ address is remapped to the Broadcast Physical
166 ** Address space by setting the 14 high order address bits of the
167 ** 32 bit GSC+ address to ones.
168 **
169 ** o TLB field affects transactions which are forwarded from GSC+ to Runway.
170 ** "Real" mode is the poweron default.
171 **
172 ** TLB Mode Value Description
173 ** Real 0 No TLB translation. Address is directly mapped and the
174 ** virtual address is composed of selected physical bits.
175 ** Error 1 Software fills the TLB manually.
176 ** Normal 2 IOA fetches IO TLB misses from IO PDIR (in host memory).
177 **
178 **
179 ** IO_IO_LOW_HV +0x60 (HV dependent)
180 ** IO_IO_HIGH_HV +0x64 (HV dependent)
181 ** IO_IO_LOW +0x78 (Architected register)
182 ** IO_IO_HIGH +0x7c (Architected register)
183 **
184 ** IO_IO_LOW and IO_IO_HIGH set the lower and upper bounds of the
185 ** I/O Adapter address space, respectively.
186 **
187 ** 0 ... 7 | 8 ... 15 | 16 ... 31 |
188 ** 11111111 | 11111111 | address |
189 **
190 ** Each LOW/HIGH pair describes a disjoint address space region.
191 ** (2 per GSC+ port). Each incoming Runway transaction address is compared
192 ** with both sets of LOW/HIGH registers. If the address is in the range
193 ** greater than or equal to IO_IO_LOW and less than IO_IO_HIGH the transaction
194 ** for forwarded to the respective GSC+ bus.
195 ** Specify IO_IO_LOW equal to or greater than IO_IO_HIGH to avoid specifying
196 ** an address space region.
197 **
198 ** In order for a Runway address to reside within GSC+ extended address space:
199 ** Runway Address [0:7] must identically compare to 8'b11111111
200 ** Runway Address [8:11] must be equal to IO_IO_LOW(_HV)[16:19]
201 ** Runway Address [12:23] must be greater than or equal to
202 ** IO_IO_LOW(_HV)[20:31] and less than IO_IO_HIGH(_HV)[20:31].
203 ** Runway Address [24:39] is not used in the comparison.
204 **
205 ** When the Runway transaction is forwarded to GSC+, the GSC+ address is
206 ** as follows:
207 ** GSC+ Address[0:3] 4'b1111
208 ** GSC+ Address[4:29] Runway Address[12:37]
209 ** GSC+ Address[30:31] 2'b00
210 **
211 ** All 4 Low/High registers must be initialized (by PDC) once the lower bus
212 ** is interrogated and address space is defined. The operating system will
213 ** modify the architectural IO_IO_LOW and IO_IO_HIGH registers following
214 ** the PDC initialization. However, the hardware version dependent IO_IO_LOW
215 ** and IO_IO_HIGH registers should not be subsequently altered by the OS.
216 **
217 ** Writes to both sets of registers will take effect immediately, bypassing
218 ** the queues, which ensures that subsequent Runway transactions are checked
219 ** against the updated bounds values. However reads are queued, introducing
220 ** the possibility of a read being bypassed by a subsequent write to the same
221 ** register. This sequence can be avoided by having software wait for read
222 ** returns before issuing subsequent writes.
223 */
224
225 struct ioc {
226 struct ioa_registers __iomem *ioc_regs; /* I/O MMU base address */
227 u8 *res_map; /* resource map, bit == pdir entry */
228 u64 *pdir_base; /* physical base address */
229 u32 pdir_size; /* bytes, function of IOV Space size */
230 u32 res_hint; /* next available IOVP -
231 circular search */
232 u32 res_size; /* size of resource map in bytes */
233 spinlock_t res_lock;
234
235 #ifdef CCIO_COLLECT_STATS
236 #define CCIO_SEARCH_SAMPLE 0x100
237 unsigned long avg_search[CCIO_SEARCH_SAMPLE];
238 unsigned long avg_idx; /* current index into avg_search */
239 unsigned long used_pages;
240 unsigned long msingle_calls;
241 unsigned long msingle_pages;
242 unsigned long msg_calls;
243 unsigned long msg_pages;
244 unsigned long usingle_calls;
245 unsigned long usingle_pages;
246 unsigned long usg_calls;
247 unsigned long usg_pages;
248 #endif
249 unsigned short cujo20_bug;
250
251 /* STUFF We don't need in performance path */
252 u32 chainid_shift; /* specify bit location of chain_id */
253 struct ioc *next; /* Linked list of discovered iocs */
254 const char *name; /* device name from firmware */
255 unsigned int hw_path; /* the hardware path this ioc is associatd with */
256 struct pci_dev *fake_pci_dev; /* the fake pci_dev for non-pci devs */
257 struct resource mmio_region[2]; /* The "routed" MMIO regions */
258 };
259
260 static struct ioc *ioc_list;
261 static int ioc_count;
262
263 /**************************************************************
264 *
265 * I/O Pdir Resource Management
266 *
267 * Bits set in the resource map are in use.
268 * Each bit can represent a number of pages.
269 * LSbs represent lower addresses (IOVA's).
270 *
271 * This was was copied from sba_iommu.c. Don't try to unify
272 * the two resource managers unless a way to have different
273 * allocation policies is also adjusted. We'd like to avoid
274 * I/O TLB thrashing by having resource allocation policy
275 * match the I/O TLB replacement policy.
276 *
277 ***************************************************************/
278 #define IOVP_SIZE PAGE_SIZE
279 #define IOVP_SHIFT PAGE_SHIFT
280 #define IOVP_MASK PAGE_MASK
281
282 /* Convert from IOVP to IOVA and vice versa. */
283 #define CCIO_IOVA(iovp,offset) ((iovp) | (offset))
284 #define CCIO_IOVP(iova) ((iova) & IOVP_MASK)
285
286 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
287 #define MKIOVP(pdir_idx) ((long)(pdir_idx) << IOVP_SHIFT)
288 #define MKIOVA(iovp,offset) (dma_addr_t)((long)iovp | (long)offset)
289
290 /*
291 ** Don't worry about the 150% average search length on a miss.
292 ** If the search wraps around, and passes the res_hint, it will
293 ** cause the kernel to panic anyhow.
294 */
295 #define CCIO_SEARCH_LOOP(ioc, res_idx, mask, size) \
296 for(; res_ptr < res_end; ++res_ptr) { \
297 int ret;\
298 unsigned int idx;\
299 idx = (unsigned int)((unsigned long)res_ptr - (unsigned long)ioc->res_map); \
300 ret = iommu_is_span_boundary(idx << 3, pages_needed, 0, boundary_size);\
301 if ((0 == (*res_ptr & mask)) && !ret) { \
302 *res_ptr |= mask; \
303 res_idx = idx;\
304 ioc->res_hint = res_idx + (size >> 3); \
305 goto resource_found; \
306 } \
307 }
308
309 #define CCIO_FIND_FREE_MAPPING(ioa, res_idx, mask, size) \
310 u##size *res_ptr = (u##size *)&((ioc)->res_map[ioa->res_hint & ~((size >> 3) - 1)]); \
311 u##size *res_end = (u##size *)&(ioc)->res_map[ioa->res_size]; \
312 CCIO_SEARCH_LOOP(ioc, res_idx, mask, size); \
313 res_ptr = (u##size *)&(ioc)->res_map[0]; \
314 CCIO_SEARCH_LOOP(ioa, res_idx, mask, size);
315
316 /*
317 ** Find available bit in this ioa's resource map.
318 ** Use a "circular" search:
319 ** o Most IOVA's are "temporary" - avg search time should be small.
320 ** o keep a history of what happened for debugging
321 ** o KISS.
322 **
323 ** Perf optimizations:
324 ** o search for log2(size) bits at a time.
325 ** o search for available resource bits using byte/word/whatever.
326 ** o use different search for "large" (eg > 4 pages) or "very large"
327 ** (eg > 16 pages) mappings.
328 */
329
330 /**
331 * ccio_alloc_range - Allocate pages in the ioc's resource map.
332 * @ioc: The I/O Controller.
333 * @pages_needed: The requested number of pages to be mapped into the
334 * I/O Pdir...
335 *
336 * This function searches the resource map of the ioc to locate a range
337 * of available pages for the requested size.
338 */
339 static int
ccio_alloc_range(struct ioc * ioc,struct device * dev,size_t size)340 ccio_alloc_range(struct ioc *ioc, struct device *dev, size_t size)
341 {
342 unsigned int pages_needed = size >> IOVP_SHIFT;
343 unsigned int res_idx;
344 unsigned long boundary_size;
345 #ifdef CCIO_COLLECT_STATS
346 unsigned long cr_start = mfctl(16);
347 #endif
348
349 BUG_ON(pages_needed == 0);
350 BUG_ON((pages_needed * IOVP_SIZE) > DMA_CHUNK_SIZE);
351
352 DBG_RES("%s() size: %d pages_needed %d\n",
353 __func__, size, pages_needed);
354
355 /*
356 ** "seek and ye shall find"...praying never hurts either...
357 ** ggg sacrifices another 710 to the computer gods.
358 */
359
360 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1,
361 1ULL << IOVP_SHIFT) >> IOVP_SHIFT;
362
363 if (pages_needed <= 8) {
364 /*
365 * LAN traffic will not thrash the TLB IFF the same NIC
366 * uses 8 adjacent pages to map separate payload data.
367 * ie the same byte in the resource bit map.
368 */
369 #if 0
370 /* FIXME: bit search should shift it's way through
371 * an unsigned long - not byte at a time. As it is now,
372 * we effectively allocate this byte to this mapping.
373 */
374 unsigned long mask = ~(~0UL >> pages_needed);
375 CCIO_FIND_FREE_MAPPING(ioc, res_idx, mask, 8);
376 #else
377 CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xff, 8);
378 #endif
379 } else if (pages_needed <= 16) {
380 CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xffff, 16);
381 } else if (pages_needed <= 32) {
382 CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~(unsigned int)0, 32);
383 #ifdef __LP64__
384 } else if (pages_needed <= 64) {
385 CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~0UL, 64);
386 #endif
387 } else {
388 panic("%s: %s() Too many pages to map. pages_needed: %u\n",
389 __FILE__, __func__, pages_needed);
390 }
391
392 panic("%s: %s() I/O MMU is out of mapping resources.\n", __FILE__,
393 __func__);
394
395 resource_found:
396
397 DBG_RES("%s() res_idx %d res_hint: %d\n",
398 __func__, res_idx, ioc->res_hint);
399
400 #ifdef CCIO_COLLECT_STATS
401 {
402 unsigned long cr_end = mfctl(16);
403 unsigned long tmp = cr_end - cr_start;
404 /* check for roll over */
405 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
406 }
407 ioc->avg_search[ioc->avg_idx++] = cr_start;
408 ioc->avg_idx &= CCIO_SEARCH_SAMPLE - 1;
409 ioc->used_pages += pages_needed;
410 #endif
411 /*
412 ** return the bit address.
413 */
414 return res_idx << 3;
415 }
416
417 #define CCIO_FREE_MAPPINGS(ioc, res_idx, mask, size) \
418 u##size *res_ptr = (u##size *)&((ioc)->res_map[res_idx]); \
419 BUG_ON((*res_ptr & mask) != mask); \
420 *res_ptr &= ~(mask);
421
422 /**
423 * ccio_free_range - Free pages from the ioc's resource map.
424 * @ioc: The I/O Controller.
425 * @iova: The I/O Virtual Address.
426 * @pages_mapped: The requested number of pages to be freed from the
427 * I/O Pdir.
428 *
429 * This function frees the resouces allocated for the iova.
430 */
431 static void
ccio_free_range(struct ioc * ioc,dma_addr_t iova,unsigned long pages_mapped)432 ccio_free_range(struct ioc *ioc, dma_addr_t iova, unsigned long pages_mapped)
433 {
434 unsigned long iovp = CCIO_IOVP(iova);
435 unsigned int res_idx = PDIR_INDEX(iovp) >> 3;
436
437 BUG_ON(pages_mapped == 0);
438 BUG_ON((pages_mapped * IOVP_SIZE) > DMA_CHUNK_SIZE);
439 BUG_ON(pages_mapped > BITS_PER_LONG);
440
441 DBG_RES("%s(): res_idx: %d pages_mapped %d\n",
442 __func__, res_idx, pages_mapped);
443
444 #ifdef CCIO_COLLECT_STATS
445 ioc->used_pages -= pages_mapped;
446 #endif
447
448 if(pages_mapped <= 8) {
449 #if 0
450 /* see matching comments in alloc_range */
451 unsigned long mask = ~(~0UL >> pages_mapped);
452 CCIO_FREE_MAPPINGS(ioc, res_idx, mask, 8);
453 #else
454 CCIO_FREE_MAPPINGS(ioc, res_idx, 0xffUL, 8);
455 #endif
456 } else if(pages_mapped <= 16) {
457 CCIO_FREE_MAPPINGS(ioc, res_idx, 0xffffUL, 16);
458 } else if(pages_mapped <= 32) {
459 CCIO_FREE_MAPPINGS(ioc, res_idx, ~(unsigned int)0, 32);
460 #ifdef __LP64__
461 } else if(pages_mapped <= 64) {
462 CCIO_FREE_MAPPINGS(ioc, res_idx, ~0UL, 64);
463 #endif
464 } else {
465 panic("%s:%s() Too many pages to unmap.\n", __FILE__,
466 __func__);
467 }
468 }
469
470 /****************************************************************
471 **
472 ** CCIO dma_ops support routines
473 **
474 *****************************************************************/
475
476 typedef unsigned long space_t;
477 #define KERNEL_SPACE 0
478
479 /*
480 ** DMA "Page Type" and Hints
481 ** o if SAFE_DMA isn't set, mapping is for FAST_DMA. SAFE_DMA should be
482 ** set for subcacheline DMA transfers since we don't want to damage the
483 ** other part of a cacheline.
484 ** o SAFE_DMA must be set for "memory" allocated via pci_alloc_consistent().
485 ** This bit tells U2 to do R/M/W for partial cachelines. "Streaming"
486 ** data can avoid this if the mapping covers full cache lines.
487 ** o STOP_MOST is needed for atomicity across cachelines.
488 ** Apparently only "some EISA devices" need this.
489 ** Using CONFIG_ISA is hack. Only the IOA with EISA under it needs
490 ** to use this hint iff the EISA devices needs this feature.
491 ** According to the U2 ERS, STOP_MOST enabled pages hurt performance.
492 ** o PREFETCH should *not* be set for cases like Multiple PCI devices
493 ** behind GSCtoPCI (dino) bus converter. Only one cacheline per GSC
494 ** device can be fetched and multiply DMA streams will thrash the
495 ** prefetch buffer and burn memory bandwidth. See 6.7.3 "Prefetch Rules
496 ** and Invalidation of Prefetch Entries".
497 **
498 ** FIXME: the default hints need to be per GSC device - not global.
499 **
500 ** HP-UX dorks: linux device driver programming model is totally different
501 ** than HP-UX's. HP-UX always sets HINT_PREFETCH since it's drivers
502 ** do special things to work on non-coherent platforms...linux has to
503 ** be much more careful with this.
504 */
505 #define IOPDIR_VALID 0x01UL
506 #define HINT_SAFE_DMA 0x02UL /* used for pci_alloc_consistent() pages */
507 #ifdef CONFIG_EISA
508 #define HINT_STOP_MOST 0x04UL /* LSL support */
509 #else
510 #define HINT_STOP_MOST 0x00UL /* only needed for "some EISA devices" */
511 #endif
512 #define HINT_UDPATE_ENB 0x08UL /* not used/supported by U2 */
513 #define HINT_PREFETCH 0x10UL /* for outbound pages which are not SAFE */
514
515
516 /*
517 ** Use direction (ie PCI_DMA_TODEVICE) to pick hint.
518 ** ccio_alloc_consistent() depends on this to get SAFE_DMA
519 ** when it passes in BIDIRECTIONAL flag.
520 */
521 static u32 hint_lookup[] = {
522 [PCI_DMA_BIDIRECTIONAL] = HINT_STOP_MOST | HINT_SAFE_DMA | IOPDIR_VALID,
523 [PCI_DMA_TODEVICE] = HINT_STOP_MOST | HINT_PREFETCH | IOPDIR_VALID,
524 [PCI_DMA_FROMDEVICE] = HINT_STOP_MOST | IOPDIR_VALID,
525 };
526
527 /**
528 * ccio_io_pdir_entry - Initialize an I/O Pdir.
529 * @pdir_ptr: A pointer into I/O Pdir.
530 * @sid: The Space Identifier.
531 * @vba: The virtual address.
532 * @hints: The DMA Hint.
533 *
534 * Given a virtual address (vba, arg2) and space id, (sid, arg1),
535 * load the I/O PDIR entry pointed to by pdir_ptr (arg0). Each IO Pdir
536 * entry consists of 8 bytes as shown below (MSB == bit 0):
537 *
538 *
539 * WORD 0:
540 * +------+----------------+-----------------------------------------------+
541 * | Phys | Virtual Index | Phys |
542 * | 0:3 | 0:11 | 4:19 |
543 * |4 bits| 12 bits | 16 bits |
544 * +------+----------------+-----------------------------------------------+
545 * WORD 1:
546 * +-----------------------+-----------------------------------------------+
547 * | Phys | Rsvd | Prefetch |Update |Rsvd |Lock |Safe |Valid |
548 * | 20:39 | | Enable |Enable | |Enable|DMA | |
549 * | 20 bits | 5 bits | 1 bit |1 bit |2 bits|1 bit |1 bit |1 bit |
550 * +-----------------------+-----------------------------------------------+
551 *
552 * The virtual index field is filled with the results of the LCI
553 * (Load Coherence Index) instruction. The 8 bits used for the virtual
554 * index are bits 12:19 of the value returned by LCI.
555 */
556 static void CCIO_INLINE
ccio_io_pdir_entry(u64 * pdir_ptr,space_t sid,unsigned long vba,unsigned long hints)557 ccio_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
558 unsigned long hints)
559 {
560 register unsigned long pa;
561 register unsigned long ci; /* coherent index */
562
563 /* We currently only support kernel addresses */
564 BUG_ON(sid != KERNEL_SPACE);
565
566 /*
567 ** WORD 1 - low order word
568 ** "hints" parm includes the VALID bit!
569 ** "dep" clobbers the physical address offset bits as well.
570 */
571 pa = virt_to_phys(vba);
572 asm volatile("depw %1,31,12,%0" : "+r" (pa) : "r" (hints));
573 ((u32 *)pdir_ptr)[1] = (u32) pa;
574
575 /*
576 ** WORD 0 - high order word
577 */
578
579 #ifdef __LP64__
580 /*
581 ** get bits 12:15 of physical address
582 ** shift bits 16:31 of physical address
583 ** and deposit them
584 */
585 asm volatile ("extrd,u %1,15,4,%0" : "=r" (ci) : "r" (pa));
586 asm volatile ("extrd,u %1,31,16,%0" : "+r" (pa) : "r" (pa));
587 asm volatile ("depd %1,35,4,%0" : "+r" (pa) : "r" (ci));
588 #else
589 pa = 0;
590 #endif
591 /*
592 ** get CPU coherency index bits
593 ** Grab virtual index [0:11]
594 ** Deposit virt_idx bits into I/O PDIR word
595 */
596 asm volatile ("lci %%r0(%1), %0" : "=r" (ci) : "r" (vba));
597 asm volatile ("extru %1,19,12,%0" : "+r" (ci) : "r" (ci));
598 asm volatile ("depw %1,15,12,%0" : "+r" (pa) : "r" (ci));
599
600 ((u32 *)pdir_ptr)[0] = (u32) pa;
601
602
603 /* FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360)
604 ** PCX-U/U+ do. (eg C200/C240)
605 ** PCX-T'? Don't know. (eg C110 or similar K-class)
606 **
607 ** See PDC_MODEL/option 0/SW_CAP word for "Non-coherent IO-PDIR bit".
608 ** Hopefully we can patch (NOP) these out at boot time somehow.
609 **
610 ** "Since PCX-U employs an offset hash that is incompatible with
611 ** the real mode coherence index generation of U2, the PDIR entry
612 ** must be flushed to memory to retain coherence."
613 */
614 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
615 asm volatile("sync");
616 }
617
618 /**
619 * ccio_clear_io_tlb - Remove stale entries from the I/O TLB.
620 * @ioc: The I/O Controller.
621 * @iovp: The I/O Virtual Page.
622 * @byte_cnt: The requested number of bytes to be freed from the I/O Pdir.
623 *
624 * Purge invalid I/O PDIR entries from the I/O TLB.
625 *
626 * FIXME: Can we change the byte_cnt to pages_mapped?
627 */
628 static CCIO_INLINE void
ccio_clear_io_tlb(struct ioc * ioc,dma_addr_t iovp,size_t byte_cnt)629 ccio_clear_io_tlb(struct ioc *ioc, dma_addr_t iovp, size_t byte_cnt)
630 {
631 u32 chain_size = 1 << ioc->chainid_shift;
632
633 iovp &= IOVP_MASK; /* clear offset bits, just want pagenum */
634 byte_cnt += chain_size;
635
636 while(byte_cnt > chain_size) {
637 WRITE_U32(CMD_TLB_PURGE | iovp, &ioc->ioc_regs->io_command);
638 iovp += chain_size;
639 byte_cnt -= chain_size;
640 }
641 }
642
643 /**
644 * ccio_mark_invalid - Mark the I/O Pdir entries invalid.
645 * @ioc: The I/O Controller.
646 * @iova: The I/O Virtual Address.
647 * @byte_cnt: The requested number of bytes to be freed from the I/O Pdir.
648 *
649 * Mark the I/O Pdir entries invalid and blow away the corresponding I/O
650 * TLB entries.
651 *
652 * FIXME: at some threshold it might be "cheaper" to just blow
653 * away the entire I/O TLB instead of individual entries.
654 *
655 * FIXME: Uturn has 256 TLB entries. We don't need to purge every
656 * PDIR entry - just once for each possible TLB entry.
657 * (We do need to maker I/O PDIR entries invalid regardless).
658 *
659 * FIXME: Can we change byte_cnt to pages_mapped?
660 */
661 static CCIO_INLINE void
ccio_mark_invalid(struct ioc * ioc,dma_addr_t iova,size_t byte_cnt)662 ccio_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
663 {
664 u32 iovp = (u32)CCIO_IOVP(iova);
665 size_t saved_byte_cnt;
666
667 /* round up to nearest page size */
668 saved_byte_cnt = byte_cnt = ALIGN(byte_cnt, IOVP_SIZE);
669
670 while(byte_cnt > 0) {
671 /* invalidate one page at a time */
672 unsigned int idx = PDIR_INDEX(iovp);
673 char *pdir_ptr = (char *) &(ioc->pdir_base[idx]);
674
675 BUG_ON(idx >= (ioc->pdir_size / sizeof(u64)));
676 pdir_ptr[7] = 0; /* clear only VALID bit */
677 /*
678 ** FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360)
679 ** PCX-U/U+ do. (eg C200/C240)
680 ** See PDC_MODEL/option 0/SW_CAP for "Non-coherent IO-PDIR bit".
681 **
682 ** Hopefully someone figures out how to patch (NOP) the
683 ** FDC/SYNC out at boot time.
684 */
685 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr[7]));
686
687 iovp += IOVP_SIZE;
688 byte_cnt -= IOVP_SIZE;
689 }
690
691 asm volatile("sync");
692 ccio_clear_io_tlb(ioc, CCIO_IOVP(iova), saved_byte_cnt);
693 }
694
695 /****************************************************************
696 **
697 ** CCIO dma_ops
698 **
699 *****************************************************************/
700
701 /**
702 * ccio_dma_supported - Verify the IOMMU supports the DMA address range.
703 * @dev: The PCI device.
704 * @mask: A bit mask describing the DMA address range of the device.
705 */
706 static int
ccio_dma_supported(struct device * dev,u64 mask)707 ccio_dma_supported(struct device *dev, u64 mask)
708 {
709 if(dev == NULL) {
710 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
711 BUG();
712 return 0;
713 }
714
715 /* only support 32-bit devices (ie PCI/GSC) */
716 return (int)(mask == 0xffffffffUL);
717 }
718
719 /**
720 * ccio_map_single - Map an address range into the IOMMU.
721 * @dev: The PCI device.
722 * @addr: The start address of the DMA region.
723 * @size: The length of the DMA region.
724 * @direction: The direction of the DMA transaction (to/from device).
725 *
726 * This function implements the pci_map_single function.
727 */
728 static dma_addr_t
ccio_map_single(struct device * dev,void * addr,size_t size,enum dma_data_direction direction)729 ccio_map_single(struct device *dev, void *addr, size_t size,
730 enum dma_data_direction direction)
731 {
732 int idx;
733 struct ioc *ioc;
734 unsigned long flags;
735 dma_addr_t iovp;
736 dma_addr_t offset;
737 u64 *pdir_start;
738 unsigned long hint = hint_lookup[(int)direction];
739
740 BUG_ON(!dev);
741 ioc = GET_IOC(dev);
742 if (!ioc)
743 return DMA_ERROR_CODE;
744
745 BUG_ON(size <= 0);
746
747 /* save offset bits */
748 offset = ((unsigned long) addr) & ~IOVP_MASK;
749
750 /* round up to nearest IOVP_SIZE */
751 size = ALIGN(size + offset, IOVP_SIZE);
752 spin_lock_irqsave(&ioc->res_lock, flags);
753
754 #ifdef CCIO_COLLECT_STATS
755 ioc->msingle_calls++;
756 ioc->msingle_pages += size >> IOVP_SHIFT;
757 #endif
758
759 idx = ccio_alloc_range(ioc, dev, size);
760 iovp = (dma_addr_t)MKIOVP(idx);
761
762 pdir_start = &(ioc->pdir_base[idx]);
763
764 DBG_RUN("%s() 0x%p -> 0x%lx size: %0x%x\n",
765 __func__, addr, (long)iovp | offset, size);
766
767 /* If not cacheline aligned, force SAFE_DMA on the whole mess */
768 if((size % L1_CACHE_BYTES) || ((unsigned long)addr % L1_CACHE_BYTES))
769 hint |= HINT_SAFE_DMA;
770
771 while(size > 0) {
772 ccio_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long)addr, hint);
773
774 DBG_RUN(" pdir %p %08x%08x\n",
775 pdir_start,
776 (u32) (((u32 *) pdir_start)[0]),
777 (u32) (((u32 *) pdir_start)[1]));
778 ++pdir_start;
779 addr += IOVP_SIZE;
780 size -= IOVP_SIZE;
781 }
782
783 spin_unlock_irqrestore(&ioc->res_lock, flags);
784
785 /* form complete address */
786 return CCIO_IOVA(iovp, offset);
787 }
788
789 /**
790 * ccio_unmap_single - Unmap an address range from the IOMMU.
791 * @dev: The PCI device.
792 * @addr: The start address of the DMA region.
793 * @size: The length of the DMA region.
794 * @direction: The direction of the DMA transaction (to/from device).
795 *
796 * This function implements the pci_unmap_single function.
797 */
798 static void
ccio_unmap_single(struct device * dev,dma_addr_t iova,size_t size,enum dma_data_direction direction)799 ccio_unmap_single(struct device *dev, dma_addr_t iova, size_t size,
800 enum dma_data_direction direction)
801 {
802 struct ioc *ioc;
803 unsigned long flags;
804 dma_addr_t offset = iova & ~IOVP_MASK;
805
806 BUG_ON(!dev);
807 ioc = GET_IOC(dev);
808 if (!ioc) {
809 WARN_ON(!ioc);
810 return;
811 }
812
813 DBG_RUN("%s() iovp 0x%lx/%x\n",
814 __func__, (long)iova, size);
815
816 iova ^= offset; /* clear offset bits */
817 size += offset;
818 size = ALIGN(size, IOVP_SIZE);
819
820 spin_lock_irqsave(&ioc->res_lock, flags);
821
822 #ifdef CCIO_COLLECT_STATS
823 ioc->usingle_calls++;
824 ioc->usingle_pages += size >> IOVP_SHIFT;
825 #endif
826
827 ccio_mark_invalid(ioc, iova, size);
828 ccio_free_range(ioc, iova, (size >> IOVP_SHIFT));
829 spin_unlock_irqrestore(&ioc->res_lock, flags);
830 }
831
832 /**
833 * ccio_alloc_consistent - Allocate a consistent DMA mapping.
834 * @dev: The PCI device.
835 * @size: The length of the DMA region.
836 * @dma_handle: The DMA address handed back to the device (not the cpu).
837 *
838 * This function implements the pci_alloc_consistent function.
839 */
840 static void *
ccio_alloc_consistent(struct device * dev,size_t size,dma_addr_t * dma_handle,gfp_t flag)841 ccio_alloc_consistent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag)
842 {
843 void *ret;
844 #if 0
845 /* GRANT Need to establish hierarchy for non-PCI devs as well
846 ** and then provide matching gsc_map_xxx() functions for them as well.
847 */
848 if(!hwdev) {
849 /* only support PCI */
850 *dma_handle = 0;
851 return 0;
852 }
853 #endif
854 ret = (void *) __get_free_pages(flag, get_order(size));
855
856 if (ret) {
857 memset(ret, 0, size);
858 *dma_handle = ccio_map_single(dev, ret, size, PCI_DMA_BIDIRECTIONAL);
859 }
860
861 return ret;
862 }
863
864 /**
865 * ccio_free_consistent - Free a consistent DMA mapping.
866 * @dev: The PCI device.
867 * @size: The length of the DMA region.
868 * @cpu_addr: The cpu address returned from the ccio_alloc_consistent.
869 * @dma_handle: The device address returned from the ccio_alloc_consistent.
870 *
871 * This function implements the pci_free_consistent function.
872 */
873 static void
ccio_free_consistent(struct device * dev,size_t size,void * cpu_addr,dma_addr_t dma_handle)874 ccio_free_consistent(struct device *dev, size_t size, void *cpu_addr,
875 dma_addr_t dma_handle)
876 {
877 ccio_unmap_single(dev, dma_handle, size, 0);
878 free_pages((unsigned long)cpu_addr, get_order(size));
879 }
880
881 /*
882 ** Since 0 is a valid pdir_base index value, can't use that
883 ** to determine if a value is valid or not. Use a flag to indicate
884 ** the SG list entry contains a valid pdir index.
885 */
886 #define PIDE_FLAG 0x80000000UL
887
888 #ifdef CCIO_COLLECT_STATS
889 #define IOMMU_MAP_STATS
890 #endif
891 #include "iommu-helpers.h"
892
893 /**
894 * ccio_map_sg - Map the scatter/gather list into the IOMMU.
895 * @dev: The PCI device.
896 * @sglist: The scatter/gather list to be mapped in the IOMMU.
897 * @nents: The number of entries in the scatter/gather list.
898 * @direction: The direction of the DMA transaction (to/from device).
899 *
900 * This function implements the pci_map_sg function.
901 */
902 static int
ccio_map_sg(struct device * dev,struct scatterlist * sglist,int nents,enum dma_data_direction direction)903 ccio_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
904 enum dma_data_direction direction)
905 {
906 struct ioc *ioc;
907 int coalesced, filled = 0;
908 unsigned long flags;
909 unsigned long hint = hint_lookup[(int)direction];
910 unsigned long prev_len = 0, current_len = 0;
911 int i;
912
913 BUG_ON(!dev);
914 ioc = GET_IOC(dev);
915 if (!ioc)
916 return 0;
917
918 DBG_RUN_SG("%s() START %d entries\n", __func__, nents);
919
920 /* Fast path single entry scatterlists. */
921 if (nents == 1) {
922 sg_dma_address(sglist) = ccio_map_single(dev,
923 sg_virt(sglist), sglist->length,
924 direction);
925 sg_dma_len(sglist) = sglist->length;
926 return 1;
927 }
928
929 for(i = 0; i < nents; i++)
930 prev_len += sglist[i].length;
931
932 spin_lock_irqsave(&ioc->res_lock, flags);
933
934 #ifdef CCIO_COLLECT_STATS
935 ioc->msg_calls++;
936 #endif
937
938 /*
939 ** First coalesce the chunks and allocate I/O pdir space
940 **
941 ** If this is one DMA stream, we can properly map using the
942 ** correct virtual address associated with each DMA page.
943 ** w/o this association, we wouldn't have coherent DMA!
944 ** Access to the virtual address is what forces a two pass algorithm.
945 */
946 coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, ccio_alloc_range);
947
948 /*
949 ** Program the I/O Pdir
950 **
951 ** map the virtual addresses to the I/O Pdir
952 ** o dma_address will contain the pdir index
953 ** o dma_len will contain the number of bytes to map
954 ** o page/offset contain the virtual address.
955 */
956 filled = iommu_fill_pdir(ioc, sglist, nents, hint, ccio_io_pdir_entry);
957
958 spin_unlock_irqrestore(&ioc->res_lock, flags);
959
960 BUG_ON(coalesced != filled);
961
962 DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled);
963
964 for (i = 0; i < filled; i++)
965 current_len += sg_dma_len(sglist + i);
966
967 BUG_ON(current_len != prev_len);
968
969 return filled;
970 }
971
972 /**
973 * ccio_unmap_sg - Unmap the scatter/gather list from the IOMMU.
974 * @dev: The PCI device.
975 * @sglist: The scatter/gather list to be unmapped from the IOMMU.
976 * @nents: The number of entries in the scatter/gather list.
977 * @direction: The direction of the DMA transaction (to/from device).
978 *
979 * This function implements the pci_unmap_sg function.
980 */
981 static void
ccio_unmap_sg(struct device * dev,struct scatterlist * sglist,int nents,enum dma_data_direction direction)982 ccio_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
983 enum dma_data_direction direction)
984 {
985 struct ioc *ioc;
986
987 BUG_ON(!dev);
988 ioc = GET_IOC(dev);
989 if (!ioc) {
990 WARN_ON(!ioc);
991 return;
992 }
993
994 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
995 __func__, nents, sg_virt(sglist), sglist->length);
996
997 #ifdef CCIO_COLLECT_STATS
998 ioc->usg_calls++;
999 #endif
1000
1001 while(sg_dma_len(sglist) && nents--) {
1002
1003 #ifdef CCIO_COLLECT_STATS
1004 ioc->usg_pages += sg_dma_len(sglist) >> PAGE_SHIFT;
1005 #endif
1006 ccio_unmap_single(dev, sg_dma_address(sglist),
1007 sg_dma_len(sglist), direction);
1008 ++sglist;
1009 }
1010
1011 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents);
1012 }
1013
1014 static struct hppa_dma_ops ccio_ops = {
1015 .dma_supported = ccio_dma_supported,
1016 .alloc_consistent = ccio_alloc_consistent,
1017 .alloc_noncoherent = ccio_alloc_consistent,
1018 .free_consistent = ccio_free_consistent,
1019 .map_single = ccio_map_single,
1020 .unmap_single = ccio_unmap_single,
1021 .map_sg = ccio_map_sg,
1022 .unmap_sg = ccio_unmap_sg,
1023 .dma_sync_single_for_cpu = NULL, /* NOP for U2/Uturn */
1024 .dma_sync_single_for_device = NULL, /* NOP for U2/Uturn */
1025 .dma_sync_sg_for_cpu = NULL, /* ditto */
1026 .dma_sync_sg_for_device = NULL, /* ditto */
1027 };
1028
1029 #ifdef CONFIG_PROC_FS
ccio_proc_info(struct seq_file * m,void * p)1030 static int ccio_proc_info(struct seq_file *m, void *p)
1031 {
1032 struct ioc *ioc = ioc_list;
1033
1034 while (ioc != NULL) {
1035 unsigned int total_pages = ioc->res_size << 3;
1036 #ifdef CCIO_COLLECT_STATS
1037 unsigned long avg = 0, min, max;
1038 int j;
1039 #endif
1040
1041 seq_printf(m, "%s\n", ioc->name);
1042
1043 seq_printf(m, "Cujo 2.0 bug : %s\n",
1044 (ioc->cujo20_bug ? "yes" : "no"));
1045
1046 seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
1047 total_pages * 8, total_pages);
1048
1049 #ifdef CCIO_COLLECT_STATS
1050 seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
1051 total_pages - ioc->used_pages, ioc->used_pages,
1052 (int)(ioc->used_pages * 100 / total_pages));
1053 #endif
1054
1055 seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
1056 ioc->res_size, total_pages);
1057
1058 #ifdef CCIO_COLLECT_STATS
1059 min = max = ioc->avg_search[0];
1060 for(j = 0; j < CCIO_SEARCH_SAMPLE; ++j) {
1061 avg += ioc->avg_search[j];
1062 if(ioc->avg_search[j] > max)
1063 max = ioc->avg_search[j];
1064 if(ioc->avg_search[j] < min)
1065 min = ioc->avg_search[j];
1066 }
1067 avg /= CCIO_SEARCH_SAMPLE;
1068 seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1069 min, avg, max);
1070
1071 seq_printf(m, "pci_map_single(): %8ld calls %8ld pages (avg %d/1000)\n",
1072 ioc->msingle_calls, ioc->msingle_pages,
1073 (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls));
1074
1075 /* KLUGE - unmap_sg calls unmap_single for each mapped page */
1076 min = ioc->usingle_calls - ioc->usg_calls;
1077 max = ioc->usingle_pages - ioc->usg_pages;
1078 seq_printf(m, "pci_unmap_single: %8ld calls %8ld pages (avg %d/1000)\n",
1079 min, max, (int)((max * 1000)/min));
1080
1081 seq_printf(m, "pci_map_sg() : %8ld calls %8ld pages (avg %d/1000)\n",
1082 ioc->msg_calls, ioc->msg_pages,
1083 (int)((ioc->msg_pages * 1000)/ioc->msg_calls));
1084
1085 seq_printf(m, "pci_unmap_sg() : %8ld calls %8ld pages (avg %d/1000)\n\n\n",
1086 ioc->usg_calls, ioc->usg_pages,
1087 (int)((ioc->usg_pages * 1000)/ioc->usg_calls));
1088 #endif /* CCIO_COLLECT_STATS */
1089
1090 ioc = ioc->next;
1091 }
1092
1093 return 0;
1094 }
1095
ccio_proc_info_open(struct inode * inode,struct file * file)1096 static int ccio_proc_info_open(struct inode *inode, struct file *file)
1097 {
1098 return single_open(file, &ccio_proc_info, NULL);
1099 }
1100
1101 static const struct file_operations ccio_proc_info_fops = {
1102 .owner = THIS_MODULE,
1103 .open = ccio_proc_info_open,
1104 .read = seq_read,
1105 .llseek = seq_lseek,
1106 .release = single_release,
1107 };
1108
ccio_proc_bitmap_info(struct seq_file * m,void * p)1109 static int ccio_proc_bitmap_info(struct seq_file *m, void *p)
1110 {
1111 struct ioc *ioc = ioc_list;
1112
1113 while (ioc != NULL) {
1114 seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map,
1115 ioc->res_size, false);
1116 seq_putc(m, '\n');
1117 ioc = ioc->next;
1118 break; /* XXX - remove me */
1119 }
1120
1121 return 0;
1122 }
1123
ccio_proc_bitmap_open(struct inode * inode,struct file * file)1124 static int ccio_proc_bitmap_open(struct inode *inode, struct file *file)
1125 {
1126 return single_open(file, &ccio_proc_bitmap_info, NULL);
1127 }
1128
1129 static const struct file_operations ccio_proc_bitmap_fops = {
1130 .owner = THIS_MODULE,
1131 .open = ccio_proc_bitmap_open,
1132 .read = seq_read,
1133 .llseek = seq_lseek,
1134 .release = single_release,
1135 };
1136 #endif /* CONFIG_PROC_FS */
1137
1138 /**
1139 * ccio_find_ioc - Find the ioc in the ioc_list
1140 * @hw_path: The hardware path of the ioc.
1141 *
1142 * This function searches the ioc_list for an ioc that matches
1143 * the provide hardware path.
1144 */
ccio_find_ioc(int hw_path)1145 static struct ioc * ccio_find_ioc(int hw_path)
1146 {
1147 int i;
1148 struct ioc *ioc;
1149
1150 ioc = ioc_list;
1151 for (i = 0; i < ioc_count; i++) {
1152 if (ioc->hw_path == hw_path)
1153 return ioc;
1154
1155 ioc = ioc->next;
1156 }
1157
1158 return NULL;
1159 }
1160
1161 /**
1162 * ccio_get_iommu - Find the iommu which controls this device
1163 * @dev: The parisc device.
1164 *
1165 * This function searches through the registered IOMMU's and returns
1166 * the appropriate IOMMU for the device based on its hardware path.
1167 */
ccio_get_iommu(const struct parisc_device * dev)1168 void * ccio_get_iommu(const struct parisc_device *dev)
1169 {
1170 dev = find_pa_parent_type(dev, HPHW_IOA);
1171 if (!dev)
1172 return NULL;
1173
1174 return ccio_find_ioc(dev->hw_path);
1175 }
1176
1177 #define CUJO_20_STEP 0x10000000 /* inc upper nibble */
1178
1179 /* Cujo 2.0 has a bug which will silently corrupt data being transferred
1180 * to/from certain pages. To avoid this happening, we mark these pages
1181 * as `used', and ensure that nothing will try to allocate from them.
1182 */
ccio_cujo20_fixup(struct parisc_device * cujo,u32 iovp)1183 void ccio_cujo20_fixup(struct parisc_device *cujo, u32 iovp)
1184 {
1185 unsigned int idx;
1186 struct parisc_device *dev = parisc_parent(cujo);
1187 struct ioc *ioc = ccio_get_iommu(dev);
1188 u8 *res_ptr;
1189
1190 ioc->cujo20_bug = 1;
1191 res_ptr = ioc->res_map;
1192 idx = PDIR_INDEX(iovp) >> 3;
1193
1194 while (idx < ioc->res_size) {
1195 res_ptr[idx] |= 0xff;
1196 idx += PDIR_INDEX(CUJO_20_STEP) >> 3;
1197 }
1198 }
1199
1200 #if 0
1201 /* GRANT - is this needed for U2 or not? */
1202
1203 /*
1204 ** Get the size of the I/O TLB for this I/O MMU.
1205 **
1206 ** If spa_shift is non-zero (ie probably U2),
1207 ** then calculate the I/O TLB size using spa_shift.
1208 **
1209 ** Otherwise we are supposed to get the IODC entry point ENTRY TLB
1210 ** and execute it. However, both U2 and Uturn firmware supplies spa_shift.
1211 ** I think only Java (K/D/R-class too?) systems don't do this.
1212 */
1213 static int
1214 ccio_get_iotlb_size(struct parisc_device *dev)
1215 {
1216 if (dev->spa_shift == 0) {
1217 panic("%s() : Can't determine I/O TLB size.\n", __func__);
1218 }
1219 return (1 << dev->spa_shift);
1220 }
1221 #else
1222
1223 /* Uturn supports 256 TLB entries */
1224 #define CCIO_CHAINID_SHIFT 8
1225 #define CCIO_CHAINID_MASK 0xff
1226 #endif /* 0 */
1227
1228 /* We *can't* support JAVA (T600). Venture there at your own risk. */
1229 static const struct parisc_device_id ccio_tbl[] = {
1230 { HPHW_IOA, HVERSION_REV_ANY_ID, U2_IOA_RUNWAY, 0xb }, /* U2 */
1231 { HPHW_IOA, HVERSION_REV_ANY_ID, UTURN_IOA_RUNWAY, 0xb }, /* UTurn */
1232 { 0, }
1233 };
1234
1235 static int ccio_probe(struct parisc_device *dev);
1236
1237 static struct parisc_driver ccio_driver = {
1238 .name = "ccio",
1239 .id_table = ccio_tbl,
1240 .probe = ccio_probe,
1241 };
1242
1243 /**
1244 * ccio_ioc_init - Initialize the I/O Controller
1245 * @ioc: The I/O Controller.
1246 *
1247 * Initialize the I/O Controller which includes setting up the
1248 * I/O Page Directory, the resource map, and initalizing the
1249 * U2/Uturn chip into virtual mode.
1250 */
1251 static void
ccio_ioc_init(struct ioc * ioc)1252 ccio_ioc_init(struct ioc *ioc)
1253 {
1254 int i;
1255 unsigned int iov_order;
1256 u32 iova_space_size;
1257
1258 /*
1259 ** Determine IOVA Space size from memory size.
1260 **
1261 ** Ideally, PCI drivers would register the maximum number
1262 ** of DMA they can have outstanding for each device they
1263 ** own. Next best thing would be to guess how much DMA
1264 ** can be outstanding based on PCI Class/sub-class. Both
1265 ** methods still require some "extra" to support PCI
1266 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
1267 */
1268
1269 iova_space_size = (u32) (totalram_pages / count_parisc_driver(&ccio_driver));
1270
1271 /* limit IOVA space size to 1MB-1GB */
1272
1273 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
1274 iova_space_size = 1 << (20 - PAGE_SHIFT);
1275 #ifdef __LP64__
1276 } else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
1277 iova_space_size = 1 << (30 - PAGE_SHIFT);
1278 #endif
1279 }
1280
1281 /*
1282 ** iova space must be log2() in size.
1283 ** thus, pdir/res_map will also be log2().
1284 */
1285
1286 /* We could use larger page sizes in order to *decrease* the number
1287 ** of mappings needed. (ie 8k pages means 1/2 the mappings).
1288 **
1289 ** Note: Grant Grunder says "Using 8k I/O pages isn't trivial either
1290 ** since the pages must also be physically contiguous - typically
1291 ** this is the case under linux."
1292 */
1293
1294 iov_order = get_order(iova_space_size << PAGE_SHIFT);
1295
1296 /* iova_space_size is now bytes, not pages */
1297 iova_space_size = 1 << (iov_order + PAGE_SHIFT);
1298
1299 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
1300
1301 BUG_ON(ioc->pdir_size > 8 * 1024 * 1024); /* max pdir size <= 8MB */
1302
1303 /* Verify it's a power of two */
1304 BUG_ON((1 << get_order(ioc->pdir_size)) != (ioc->pdir_size >> PAGE_SHIFT));
1305
1306 DBG_INIT("%s() hpa 0x%p mem %luMB IOV %dMB (%d bits)\n",
1307 __func__, ioc->ioc_regs,
1308 (unsigned long) totalram_pages >> (20 - PAGE_SHIFT),
1309 iova_space_size>>20,
1310 iov_order + PAGE_SHIFT);
1311
1312 ioc->pdir_base = (u64 *)__get_free_pages(GFP_KERNEL,
1313 get_order(ioc->pdir_size));
1314 if(NULL == ioc->pdir_base) {
1315 panic("%s() could not allocate I/O Page Table\n", __func__);
1316 }
1317 memset(ioc->pdir_base, 0, ioc->pdir_size);
1318
1319 BUG_ON((((unsigned long)ioc->pdir_base) & PAGE_MASK) != (unsigned long)ioc->pdir_base);
1320 DBG_INIT(" base %p\n", ioc->pdir_base);
1321
1322 /* resource map size dictated by pdir_size */
1323 ioc->res_size = (ioc->pdir_size / sizeof(u64)) >> 3;
1324 DBG_INIT("%s() res_size 0x%x\n", __func__, ioc->res_size);
1325
1326 ioc->res_map = (u8 *)__get_free_pages(GFP_KERNEL,
1327 get_order(ioc->res_size));
1328 if(NULL == ioc->res_map) {
1329 panic("%s() could not allocate resource map\n", __func__);
1330 }
1331 memset(ioc->res_map, 0, ioc->res_size);
1332
1333 /* Initialize the res_hint to 16 */
1334 ioc->res_hint = 16;
1335
1336 /* Initialize the spinlock */
1337 spin_lock_init(&ioc->res_lock);
1338
1339 /*
1340 ** Chainid is the upper most bits of an IOVP used to determine
1341 ** which TLB entry an IOVP will use.
1342 */
1343 ioc->chainid_shift = get_order(iova_space_size) + PAGE_SHIFT - CCIO_CHAINID_SHIFT;
1344 DBG_INIT(" chainid_shift 0x%x\n", ioc->chainid_shift);
1345
1346 /*
1347 ** Initialize IOA hardware
1348 */
1349 WRITE_U32(CCIO_CHAINID_MASK << ioc->chainid_shift,
1350 &ioc->ioc_regs->io_chain_id_mask);
1351
1352 WRITE_U32(virt_to_phys(ioc->pdir_base),
1353 &ioc->ioc_regs->io_pdir_base);
1354
1355 /*
1356 ** Go to "Virtual Mode"
1357 */
1358 WRITE_U32(IOA_NORMAL_MODE, &ioc->ioc_regs->io_control);
1359
1360 /*
1361 ** Initialize all I/O TLB entries to 0 (Valid bit off).
1362 */
1363 WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_m);
1364 WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_l);
1365
1366 for(i = 1 << CCIO_CHAINID_SHIFT; i ; i--) {
1367 WRITE_U32((CMD_TLB_DIRECT_WRITE | (i << ioc->chainid_shift)),
1368 &ioc->ioc_regs->io_command);
1369 }
1370 }
1371
1372 static void __init
ccio_init_resource(struct resource * res,char * name,void __iomem * ioaddr)1373 ccio_init_resource(struct resource *res, char *name, void __iomem *ioaddr)
1374 {
1375 int result;
1376
1377 res->parent = NULL;
1378 res->flags = IORESOURCE_MEM;
1379 /*
1380 * bracing ((signed) ...) are required for 64bit kernel because
1381 * we only want to sign extend the lower 16 bits of the register.
1382 * The upper 16-bits of range registers are hardcoded to 0xffff.
1383 */
1384 res->start = (unsigned long)((signed) READ_U32(ioaddr) << 16);
1385 res->end = (unsigned long)((signed) (READ_U32(ioaddr + 4) << 16) - 1);
1386 res->name = name;
1387 /*
1388 * Check if this MMIO range is disable
1389 */
1390 if (res->end + 1 == res->start)
1391 return;
1392
1393 /* On some platforms (e.g. K-Class), we have already registered
1394 * resources for devices reported by firmware. Some are children
1395 * of ccio.
1396 * "insert" ccio ranges in the mmio hierarchy (/proc/iomem).
1397 */
1398 result = insert_resource(&iomem_resource, res);
1399 if (result < 0) {
1400 printk(KERN_ERR "%s() failed to claim CCIO bus address space (%08lx,%08lx)\n",
1401 __func__, (unsigned long)res->start, (unsigned long)res->end);
1402 }
1403 }
1404
ccio_init_resources(struct ioc * ioc)1405 static void __init ccio_init_resources(struct ioc *ioc)
1406 {
1407 struct resource *res = ioc->mmio_region;
1408 char *name = kmalloc(14, GFP_KERNEL);
1409
1410 snprintf(name, 14, "GSC Bus [%d/]", ioc->hw_path);
1411
1412 ccio_init_resource(res, name, &ioc->ioc_regs->io_io_low);
1413 ccio_init_resource(res + 1, name, &ioc->ioc_regs->io_io_low_hv);
1414 }
1415
new_ioc_area(struct resource * res,unsigned long size,unsigned long min,unsigned long max,unsigned long align)1416 static int new_ioc_area(struct resource *res, unsigned long size,
1417 unsigned long min, unsigned long max, unsigned long align)
1418 {
1419 if (max <= min)
1420 return -EBUSY;
1421
1422 res->start = (max - size + 1) &~ (align - 1);
1423 res->end = res->start + size;
1424
1425 /* We might be trying to expand the MMIO range to include
1426 * a child device that has already registered it's MMIO space.
1427 * Use "insert" instead of request_resource().
1428 */
1429 if (!insert_resource(&iomem_resource, res))
1430 return 0;
1431
1432 return new_ioc_area(res, size, min, max - size, align);
1433 }
1434
expand_ioc_area(struct resource * res,unsigned long size,unsigned long min,unsigned long max,unsigned long align)1435 static int expand_ioc_area(struct resource *res, unsigned long size,
1436 unsigned long min, unsigned long max, unsigned long align)
1437 {
1438 unsigned long start, len;
1439
1440 if (!res->parent)
1441 return new_ioc_area(res, size, min, max, align);
1442
1443 start = (res->start - size) &~ (align - 1);
1444 len = res->end - start + 1;
1445 if (start >= min) {
1446 if (!adjust_resource(res, start, len))
1447 return 0;
1448 }
1449
1450 start = res->start;
1451 len = ((size + res->end + align) &~ (align - 1)) - start;
1452 if (start + len <= max) {
1453 if (!adjust_resource(res, start, len))
1454 return 0;
1455 }
1456
1457 return -EBUSY;
1458 }
1459
1460 /*
1461 * Dino calls this function. Beware that we may get called on systems
1462 * which have no IOC (725, B180, C160L, etc) but do have a Dino.
1463 * So it's legal to find no parent IOC.
1464 *
1465 * Some other issues: one of the resources in the ioc may be unassigned.
1466 */
ccio_allocate_resource(const struct parisc_device * dev,struct resource * res,unsigned long size,unsigned long min,unsigned long max,unsigned long align)1467 int ccio_allocate_resource(const struct parisc_device *dev,
1468 struct resource *res, unsigned long size,
1469 unsigned long min, unsigned long max, unsigned long align)
1470 {
1471 struct resource *parent = &iomem_resource;
1472 struct ioc *ioc = ccio_get_iommu(dev);
1473 if (!ioc)
1474 goto out;
1475
1476 parent = ioc->mmio_region;
1477 if (parent->parent &&
1478 !allocate_resource(parent, res, size, min, max, align, NULL, NULL))
1479 return 0;
1480
1481 if ((parent + 1)->parent &&
1482 !allocate_resource(parent + 1, res, size, min, max, align,
1483 NULL, NULL))
1484 return 0;
1485
1486 if (!expand_ioc_area(parent, size, min, max, align)) {
1487 __raw_writel(((parent->start)>>16) | 0xffff0000,
1488 &ioc->ioc_regs->io_io_low);
1489 __raw_writel(((parent->end)>>16) | 0xffff0000,
1490 &ioc->ioc_regs->io_io_high);
1491 } else if (!expand_ioc_area(parent + 1, size, min, max, align)) {
1492 parent++;
1493 __raw_writel(((parent->start)>>16) | 0xffff0000,
1494 &ioc->ioc_regs->io_io_low_hv);
1495 __raw_writel(((parent->end)>>16) | 0xffff0000,
1496 &ioc->ioc_regs->io_io_high_hv);
1497 } else {
1498 return -EBUSY;
1499 }
1500
1501 out:
1502 return allocate_resource(parent, res, size, min, max, align, NULL,NULL);
1503 }
1504
ccio_request_resource(const struct parisc_device * dev,struct resource * res)1505 int ccio_request_resource(const struct parisc_device *dev,
1506 struct resource *res)
1507 {
1508 struct resource *parent;
1509 struct ioc *ioc = ccio_get_iommu(dev);
1510
1511 if (!ioc) {
1512 parent = &iomem_resource;
1513 } else if ((ioc->mmio_region->start <= res->start) &&
1514 (res->end <= ioc->mmio_region->end)) {
1515 parent = ioc->mmio_region;
1516 } else if (((ioc->mmio_region + 1)->start <= res->start) &&
1517 (res->end <= (ioc->mmio_region + 1)->end)) {
1518 parent = ioc->mmio_region + 1;
1519 } else {
1520 return -EBUSY;
1521 }
1522
1523 /* "transparent" bus bridges need to register MMIO resources
1524 * firmware assigned them. e.g. children of hppb.c (e.g. K-class)
1525 * registered their resources in the PDC "bus walk" (See
1526 * arch/parisc/kernel/inventory.c).
1527 */
1528 return insert_resource(parent, res);
1529 }
1530
1531 /**
1532 * ccio_probe - Determine if ccio should claim this device.
1533 * @dev: The device which has been found
1534 *
1535 * Determine if ccio should claim this chip (return 0) or not (return 1).
1536 * If so, initialize the chip and tell other partners in crime they
1537 * have work to do.
1538 */
ccio_probe(struct parisc_device * dev)1539 static int __init ccio_probe(struct parisc_device *dev)
1540 {
1541 int i;
1542 struct ioc *ioc, **ioc_p = &ioc_list;
1543
1544 ioc = kzalloc(sizeof(struct ioc), GFP_KERNEL);
1545 if (ioc == NULL) {
1546 printk(KERN_ERR MODULE_NAME ": memory allocation failure\n");
1547 return 1;
1548 }
1549
1550 ioc->name = dev->id.hversion == U2_IOA_RUNWAY ? "U2" : "UTurn";
1551
1552 printk(KERN_INFO "Found %s at 0x%lx\n", ioc->name,
1553 (unsigned long)dev->hpa.start);
1554
1555 for (i = 0; i < ioc_count; i++) {
1556 ioc_p = &(*ioc_p)->next;
1557 }
1558 *ioc_p = ioc;
1559
1560 ioc->hw_path = dev->hw_path;
1561 ioc->ioc_regs = ioremap_nocache(dev->hpa.start, 4096);
1562 ccio_ioc_init(ioc);
1563 ccio_init_resources(ioc);
1564 hppa_dma_ops = &ccio_ops;
1565 dev->dev.platform_data = kzalloc(sizeof(struct pci_hba_data), GFP_KERNEL);
1566
1567 /* if this fails, no I/O cards will work, so may as well bug */
1568 BUG_ON(dev->dev.platform_data == NULL);
1569 HBA_DATA(dev->dev.platform_data)->iommu = ioc;
1570
1571 #ifdef CONFIG_PROC_FS
1572 if (ioc_count == 0) {
1573 proc_create(MODULE_NAME, 0, proc_runway_root,
1574 &ccio_proc_info_fops);
1575 proc_create(MODULE_NAME"-bitmap", 0, proc_runway_root,
1576 &ccio_proc_bitmap_fops);
1577 }
1578 #endif
1579 ioc_count++;
1580
1581 parisc_has_iommu();
1582 return 0;
1583 }
1584
1585 /**
1586 * ccio_init - ccio initialization procedure.
1587 *
1588 * Register this driver.
1589 */
ccio_init(void)1590 void __init ccio_init(void)
1591 {
1592 register_parisc_driver(&ccio_driver);
1593 }
1594
1595