1 /*
2 * Copyright (C) 2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/clk-provider.h>
18 #include <linux/io.h>
19 #include <linux/of.h>
20 #include <linux/clkdev.h>
21 #include <linux/of_address.h>
22
23 #define IPROC_CLK_MAX_FREQ_POLICY 0x3
24 #define IPROC_CLK_POLICY_FREQ_OFFSET 0x008
25 #define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT 8
26 #define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK 0x7
27
28 #define IPROC_CLK_PLLARMA_OFFSET 0xc00
29 #define IPROC_CLK_PLLARMA_LOCK_SHIFT 28
30 #define IPROC_CLK_PLLARMA_PDIV_SHIFT 24
31 #define IPROC_CLK_PLLARMA_PDIV_MASK 0xf
32 #define IPROC_CLK_PLLARMA_NDIV_INT_SHIFT 8
33 #define IPROC_CLK_PLLARMA_NDIV_INT_MASK 0x3ff
34
35 #define IPROC_CLK_PLLARMB_OFFSET 0xc04
36 #define IPROC_CLK_PLLARMB_NDIV_FRAC_MASK 0xfffff
37
38 #define IPROC_CLK_PLLARMC_OFFSET 0xc08
39 #define IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT 8
40 #define IPROC_CLK_PLLARMC_MDIV_MASK 0xff
41
42 #define IPROC_CLK_PLLARMCTL5_OFFSET 0xc20
43 #define IPROC_CLK_PLLARMCTL5_H_MDIV_MASK 0xff
44
45 #define IPROC_CLK_PLLARM_OFFSET_OFFSET 0xc24
46 #define IPROC_CLK_PLLARM_SW_CTL_SHIFT 29
47 #define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT 20
48 #define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK 0xff
49 #define IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK 0xfffff
50
51 #define IPROC_CLK_ARM_DIV_OFFSET 0xe00
52 #define IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT 4
53 #define IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK 0xf
54
55 #define IPROC_CLK_POLICY_DBG_OFFSET 0xec0
56 #define IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT 12
57 #define IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK 0x7
58
59 enum iproc_arm_pll_fid {
60 ARM_PLL_FID_CRYSTAL_CLK = 0,
61 ARM_PLL_FID_SYS_CLK = 2,
62 ARM_PLL_FID_CH0_SLOW_CLK = 6,
63 ARM_PLL_FID_CH1_FAST_CLK = 7
64 };
65
66 struct iproc_arm_pll {
67 struct clk_hw hw;
68 void __iomem *base;
69 unsigned long rate;
70 };
71
72 #define to_iproc_arm_pll(hw) container_of(hw, struct iproc_arm_pll, hw)
73
__get_fid(struct iproc_arm_pll * pll)74 static unsigned int __get_fid(struct iproc_arm_pll *pll)
75 {
76 u32 val;
77 unsigned int policy, fid, active_fid;
78
79 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET);
80 if (val & (1 << IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT))
81 policy = val & IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK;
82 else
83 policy = 0;
84
85 /* something is seriously wrong */
86 BUG_ON(policy > IPROC_CLK_MAX_FREQ_POLICY);
87
88 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET);
89 fid = (val >> (IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT * policy)) &
90 IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK;
91
92 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET);
93 active_fid = IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK &
94 (val >> IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT);
95 if (fid != active_fid) {
96 pr_debug("%s: fid override %u->%u\n", __func__, fid,
97 active_fid);
98 fid = active_fid;
99 }
100
101 pr_debug("%s: active fid: %u\n", __func__, fid);
102
103 return fid;
104 }
105
106 /*
107 * Determine the mdiv (post divider) based on the frequency ID being used.
108 * There are 4 sources that can be used to derive the output clock rate:
109 * - 25 MHz Crystal
110 * - System clock
111 * - PLL channel 0 (slow clock)
112 * - PLL channel 1 (fast clock)
113 */
__get_mdiv(struct iproc_arm_pll * pll)114 static int __get_mdiv(struct iproc_arm_pll *pll)
115 {
116 unsigned int fid;
117 int mdiv;
118 u32 val;
119
120 fid = __get_fid(pll);
121
122 switch (fid) {
123 case ARM_PLL_FID_CRYSTAL_CLK:
124 case ARM_PLL_FID_SYS_CLK:
125 mdiv = 1;
126 break;
127
128 case ARM_PLL_FID_CH0_SLOW_CLK:
129 val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET);
130 mdiv = val & IPROC_CLK_PLLARMC_MDIV_MASK;
131 if (mdiv == 0)
132 mdiv = 256;
133 break;
134
135 case ARM_PLL_FID_CH1_FAST_CLK:
136 val = readl(pll->base + IPROC_CLK_PLLARMCTL5_OFFSET);
137 mdiv = val & IPROC_CLK_PLLARMCTL5_H_MDIV_MASK;
138 if (mdiv == 0)
139 mdiv = 256;
140 break;
141
142 default:
143 mdiv = -EFAULT;
144 }
145
146 return mdiv;
147 }
148
__get_ndiv(struct iproc_arm_pll * pll)149 static unsigned int __get_ndiv(struct iproc_arm_pll *pll)
150 {
151 u32 val;
152 unsigned int ndiv_int, ndiv_frac, ndiv;
153
154 val = readl(pll->base + IPROC_CLK_PLLARM_OFFSET_OFFSET);
155 if (val & (1 << IPROC_CLK_PLLARM_SW_CTL_SHIFT)) {
156 /*
157 * offset mode is active. Read the ndiv from the PLLARM OFFSET
158 * register
159 */
160 ndiv_int = (val >> IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT) &
161 IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK;
162 if (ndiv_int == 0)
163 ndiv_int = 256;
164
165 ndiv_frac = val & IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK;
166 } else {
167 /* offset mode not active */
168 val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET);
169 ndiv_int = (val >> IPROC_CLK_PLLARMA_NDIV_INT_SHIFT) &
170 IPROC_CLK_PLLARMA_NDIV_INT_MASK;
171 if (ndiv_int == 0)
172 ndiv_int = 1024;
173
174 val = readl(pll->base + IPROC_CLK_PLLARMB_OFFSET);
175 ndiv_frac = val & IPROC_CLK_PLLARMB_NDIV_FRAC_MASK;
176 }
177
178 ndiv = (ndiv_int << 20) | ndiv_frac;
179
180 return ndiv;
181 }
182
183 /*
184 * The output frequency of the ARM PLL is calculated based on the ARM PLL
185 * divider values:
186 * pdiv = ARM PLL pre-divider
187 * ndiv = ARM PLL multiplier
188 * mdiv = ARM PLL post divider
189 *
190 * The frequency is calculated by:
191 * ((ndiv * parent clock rate) / pdiv) / mdiv
192 */
iproc_arm_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)193 static unsigned long iproc_arm_pll_recalc_rate(struct clk_hw *hw,
194 unsigned long parent_rate)
195 {
196 struct iproc_arm_pll *pll = to_iproc_arm_pll(hw);
197 u32 val;
198 int mdiv;
199 u64 ndiv;
200 unsigned int pdiv;
201
202 /* in bypass mode, use parent rate */
203 val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET);
204 if (val & (1 << IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT)) {
205 pll->rate = parent_rate;
206 return pll->rate;
207 }
208
209 /* PLL needs to be locked */
210 val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET);
211 if (!(val & (1 << IPROC_CLK_PLLARMA_LOCK_SHIFT))) {
212 pll->rate = 0;
213 return 0;
214 }
215
216 pdiv = (val >> IPROC_CLK_PLLARMA_PDIV_SHIFT) &
217 IPROC_CLK_PLLARMA_PDIV_MASK;
218 if (pdiv == 0)
219 pdiv = 16;
220
221 ndiv = __get_ndiv(pll);
222 mdiv = __get_mdiv(pll);
223 if (mdiv <= 0) {
224 pll->rate = 0;
225 return 0;
226 }
227 pll->rate = (ndiv * parent_rate) >> 20;
228 pll->rate = (pll->rate / pdiv) / mdiv;
229
230 pr_debug("%s: ARM PLL rate: %lu. parent rate: %lu\n", __func__,
231 pll->rate, parent_rate);
232 pr_debug("%s: ndiv_int: %u, pdiv: %u, mdiv: %d\n", __func__,
233 (unsigned int)(ndiv >> 20), pdiv, mdiv);
234
235 return pll->rate;
236 }
237
238 static const struct clk_ops iproc_arm_pll_ops = {
239 .recalc_rate = iproc_arm_pll_recalc_rate,
240 };
241
iproc_armpll_setup(struct device_node * node)242 void __init iproc_armpll_setup(struct device_node *node)
243 {
244 int ret;
245 struct clk *clk;
246 struct iproc_arm_pll *pll;
247 struct clk_init_data init;
248 const char *parent_name;
249
250 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
251 if (WARN_ON(!pll))
252 return;
253
254 pll->base = of_iomap(node, 0);
255 if (WARN_ON(!pll->base))
256 goto err_free_pll;
257
258 init.name = node->name;
259 init.ops = &iproc_arm_pll_ops;
260 init.flags = 0;
261 parent_name = of_clk_get_parent_name(node, 0);
262 init.parent_names = (parent_name ? &parent_name : NULL);
263 init.num_parents = (parent_name ? 1 : 0);
264 pll->hw.init = &init;
265
266 clk = clk_register(NULL, &pll->hw);
267 if (WARN_ON(IS_ERR(clk)))
268 goto err_iounmap;
269
270 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
271 if (WARN_ON(ret))
272 goto err_clk_unregister;
273
274 return;
275
276 err_clk_unregister:
277 clk_unregister(clk);
278 err_iounmap:
279 iounmap(pll->base);
280 err_free_pll:
281 kfree(pll);
282 }
283