1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
5 *
6 * Portions of this file are derived from the ipw3945 project, as well
7 * as portions of the ieee80211 subsystem header files.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 *
22 * The full GNU General Public License is included in this distribution in the
23 * file called LICENSE.
24 *
25 * Contact Information:
26 * Intel Linux Wireless <ilw@linux.intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 *****************************************************************************/
30 #include <linux/sched.h>
31 #include <linux/wait.h>
32 #include <linux/gfp.h>
33
34 #include "iwl-prph.h"
35 #include "iwl-io.h"
36 #include "internal.h"
37 #include "iwl-op-mode.h"
38
39 /******************************************************************************
40 *
41 * RX path functions
42 *
43 ******************************************************************************/
44
45 /*
46 * Rx theory of operation
47 *
48 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
49 * each of which point to Receive Buffers to be filled by the NIC. These get
50 * used not only for Rx frames, but for any command response or notification
51 * from the NIC. The driver and NIC manage the Rx buffers by means
52 * of indexes into the circular buffer.
53 *
54 * Rx Queue Indexes
55 * The host/firmware share two index registers for managing the Rx buffers.
56 *
57 * The READ index maps to the first position that the firmware may be writing
58 * to -- the driver can read up to (but not including) this position and get
59 * good data.
60 * The READ index is managed by the firmware once the card is enabled.
61 *
62 * The WRITE index maps to the last position the driver has read from -- the
63 * position preceding WRITE is the last slot the firmware can place a packet.
64 *
65 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
66 * WRITE = READ.
67 *
68 * During initialization, the host sets up the READ queue position to the first
69 * INDEX position, and WRITE to the last (READ - 1 wrapped)
70 *
71 * When the firmware places a packet in a buffer, it will advance the READ index
72 * and fire the RX interrupt. The driver can then query the READ index and
73 * process as many packets as possible, moving the WRITE index forward as it
74 * resets the Rx queue buffers with new memory.
75 *
76 * The management in the driver is as follows:
77 * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free.
78 * When the interrupt handler is called, the request is processed.
79 * The page is either stolen - transferred to the upper layer
80 * or reused - added immediately to the iwl->rxq->rx_free list.
81 * + When the page is stolen - the driver updates the matching queue's used
82 * count, detaches the RBD and transfers it to the queue used list.
83 * When there are two used RBDs - they are transferred to the allocator empty
84 * list. Work is then scheduled for the allocator to start allocating
85 * eight buffers.
86 * When there are another 6 used RBDs - they are transferred to the allocator
87 * empty list and the driver tries to claim the pre-allocated buffers and
88 * add them to iwl->rxq->rx_free. If it fails - it continues to claim them
89 * until ready.
90 * When there are 8+ buffers in the free list - either from allocation or from
91 * 8 reused unstolen pages - restock is called to update the FW and indexes.
92 * + In order to make sure the allocator always has RBDs to use for allocation
93 * the allocator has initial pool in the size of num_queues*(8-2) - the
94 * maximum missing RBDs per allocation request (request posted with 2
95 * empty RBDs, there is no guarantee when the other 6 RBDs are supplied).
96 * The queues supplies the recycle of the rest of the RBDs.
97 * + A received packet is processed and handed to the kernel network stack,
98 * detached from the iwl->rxq. The driver 'processed' index is updated.
99 * + If there are no allocated buffers in iwl->rxq->rx_free,
100 * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
101 * If there were enough free buffers and RX_STALLED is set it is cleared.
102 *
103 *
104 * Driver sequence:
105 *
106 * iwl_rxq_alloc() Allocates rx_free
107 * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls
108 * iwl_pcie_rxq_restock.
109 * Used only during initialization.
110 * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx
111 * queue, updates firmware pointers, and updates
112 * the WRITE index.
113 * iwl_pcie_rx_allocator() Background work for allocating pages.
114 *
115 * -- enable interrupts --
116 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
117 * READ INDEX, detaching the SKB from the pool.
118 * Moves the packet buffer from queue to rx_used.
119 * Posts and claims requests to the allocator.
120 * Calls iwl_pcie_rxq_restock to refill any empty
121 * slots.
122 *
123 * RBD life-cycle:
124 *
125 * Init:
126 * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue
127 *
128 * Regular Receive interrupt:
129 * Page Stolen:
130 * rxq.queue -> rxq.rx_used -> allocator.rbd_empty ->
131 * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue
132 * Page not Stolen:
133 * rxq.queue -> rxq.rx_free -> rxq.queue
134 * ...
135 *
136 */
137
138 /*
139 * iwl_rxq_space - Return number of free slots available in queue.
140 */
iwl_rxq_space(const struct iwl_rxq * rxq)141 static int iwl_rxq_space(const struct iwl_rxq *rxq)
142 {
143 /* Make sure RX_QUEUE_SIZE is a power of 2 */
144 BUILD_BUG_ON(RX_QUEUE_SIZE & (RX_QUEUE_SIZE - 1));
145
146 /*
147 * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity
148 * between empty and completely full queues.
149 * The following is equivalent to modulo by RX_QUEUE_SIZE and is well
150 * defined for negative dividends.
151 */
152 return (rxq->read - rxq->write - 1) & (RX_QUEUE_SIZE - 1);
153 }
154
155 /*
156 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
157 */
iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)158 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
159 {
160 return cpu_to_le32((u32)(dma_addr >> 8));
161 }
162
163 /*
164 * iwl_pcie_rx_stop - stops the Rx DMA
165 */
iwl_pcie_rx_stop(struct iwl_trans * trans)166 int iwl_pcie_rx_stop(struct iwl_trans *trans)
167 {
168 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
169 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
170 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
171 }
172
173 /*
174 * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
175 */
iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans * trans)176 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans)
177 {
178 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
179 struct iwl_rxq *rxq = &trans_pcie->rxq;
180 u32 reg;
181
182 lockdep_assert_held(&rxq->lock);
183
184 /*
185 * explicitly wake up the NIC if:
186 * 1. shadow registers aren't enabled
187 * 2. there is a chance that the NIC is asleep
188 */
189 if (!trans->cfg->base_params->shadow_reg_enable &&
190 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
191 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
192
193 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
194 IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n",
195 reg);
196 iwl_set_bit(trans, CSR_GP_CNTRL,
197 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
198 rxq->need_update = true;
199 return;
200 }
201 }
202
203 rxq->write_actual = round_down(rxq->write, 8);
204 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
205 }
206
iwl_pcie_rxq_check_wrptr(struct iwl_trans * trans)207 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans)
208 {
209 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
210 struct iwl_rxq *rxq = &trans_pcie->rxq;
211
212 spin_lock(&rxq->lock);
213
214 if (!rxq->need_update)
215 goto exit_unlock;
216
217 iwl_pcie_rxq_inc_wr_ptr(trans);
218 rxq->need_update = false;
219
220 exit_unlock:
221 spin_unlock(&rxq->lock);
222 }
223
224 /*
225 * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
226 *
227 * If there are slots in the RX queue that need to be restocked,
228 * and we have free pre-allocated buffers, fill the ranks as much
229 * as we can, pulling from rx_free.
230 *
231 * This moves the 'write' index forward to catch up with 'processed', and
232 * also updates the memory address in the firmware to reference the new
233 * target buffer.
234 */
iwl_pcie_rxq_restock(struct iwl_trans * trans)235 static void iwl_pcie_rxq_restock(struct iwl_trans *trans)
236 {
237 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
238 struct iwl_rxq *rxq = &trans_pcie->rxq;
239 struct iwl_rx_mem_buffer *rxb;
240
241 /*
242 * If the device isn't enabled - not need to try to add buffers...
243 * This can happen when we stop the device and still have an interrupt
244 * pending. We stop the APM before we sync the interrupts because we
245 * have to (see comment there). On the other hand, since the APM is
246 * stopped, we cannot access the HW (in particular not prph).
247 * So don't try to restock if the APM has been already stopped.
248 */
249 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
250 return;
251
252 spin_lock(&rxq->lock);
253 while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
254 /* The overwritten rxb must be a used one */
255 rxb = rxq->queue[rxq->write];
256 BUG_ON(rxb && rxb->page);
257
258 /* Get next free Rx buffer, remove from free list */
259 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
260 list);
261 list_del(&rxb->list);
262
263 /* Point to Rx buffer via next RBD in circular buffer */
264 rxq->bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
265 rxq->queue[rxq->write] = rxb;
266 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
267 rxq->free_count--;
268 }
269 spin_unlock(&rxq->lock);
270
271 /* If we've added more space for the firmware to place data, tell it.
272 * Increment device's write pointer in multiples of 8. */
273 if (rxq->write_actual != (rxq->write & ~0x7)) {
274 spin_lock(&rxq->lock);
275 iwl_pcie_rxq_inc_wr_ptr(trans);
276 spin_unlock(&rxq->lock);
277 }
278 }
279
280 /*
281 * iwl_pcie_rx_alloc_page - allocates and returns a page.
282 *
283 */
iwl_pcie_rx_alloc_page(struct iwl_trans * trans,gfp_t priority)284 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans,
285 gfp_t priority)
286 {
287 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
288 struct iwl_rxq *rxq = &trans_pcie->rxq;
289 struct page *page;
290 gfp_t gfp_mask = priority;
291
292 if (rxq->free_count > RX_LOW_WATERMARK)
293 gfp_mask |= __GFP_NOWARN;
294
295 if (trans_pcie->rx_page_order > 0)
296 gfp_mask |= __GFP_COMP;
297
298 /* Alloc a new receive buffer */
299 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
300 if (!page) {
301 if (net_ratelimit())
302 IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n",
303 trans_pcie->rx_page_order);
304 /* Issue an error if the hardware has consumed more than half
305 * of its free buffer list and we don't have enough
306 * pre-allocated buffers.
307 ` */
308 if (rxq->free_count <= RX_LOW_WATERMARK &&
309 iwl_rxq_space(rxq) > (RX_QUEUE_SIZE / 2) &&
310 net_ratelimit())
311 IWL_CRIT(trans,
312 "Failed to alloc_pages with GFP_KERNEL. Only %u free buffers remaining.\n",
313 rxq->free_count);
314 return NULL;
315 }
316 return page;
317 }
318
319 /*
320 * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
321 *
322 * A used RBD is an Rx buffer that has been given to the stack. To use it again
323 * a page must be allocated and the RBD must point to the page. This function
324 * doesn't change the HW pointer but handles the list of pages that is used by
325 * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
326 * allocated buffers.
327 */
iwl_pcie_rxq_alloc_rbs(struct iwl_trans * trans,gfp_t priority)328 static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority)
329 {
330 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
331 struct iwl_rxq *rxq = &trans_pcie->rxq;
332 struct iwl_rx_mem_buffer *rxb;
333 struct page *page;
334
335 while (1) {
336 spin_lock(&rxq->lock);
337 if (list_empty(&rxq->rx_used)) {
338 spin_unlock(&rxq->lock);
339 return;
340 }
341 spin_unlock(&rxq->lock);
342
343 /* Alloc a new receive buffer */
344 page = iwl_pcie_rx_alloc_page(trans, priority);
345 if (!page)
346 return;
347
348 spin_lock(&rxq->lock);
349
350 if (list_empty(&rxq->rx_used)) {
351 spin_unlock(&rxq->lock);
352 __free_pages(page, trans_pcie->rx_page_order);
353 return;
354 }
355 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
356 list);
357 list_del(&rxb->list);
358 spin_unlock(&rxq->lock);
359
360 BUG_ON(rxb->page);
361 rxb->page = page;
362 /* Get physical address of the RB */
363 rxb->page_dma =
364 dma_map_page(trans->dev, page, 0,
365 PAGE_SIZE << trans_pcie->rx_page_order,
366 DMA_FROM_DEVICE);
367 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
368 rxb->page = NULL;
369 spin_lock(&rxq->lock);
370 list_add(&rxb->list, &rxq->rx_used);
371 spin_unlock(&rxq->lock);
372 __free_pages(page, trans_pcie->rx_page_order);
373 return;
374 }
375 /* dma address must be no more than 36 bits */
376 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
377 /* and also 256 byte aligned! */
378 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
379
380 spin_lock(&rxq->lock);
381
382 list_add_tail(&rxb->list, &rxq->rx_free);
383 rxq->free_count++;
384
385 spin_unlock(&rxq->lock);
386 }
387 }
388
iwl_pcie_rxq_free_rbs(struct iwl_trans * trans)389 static void iwl_pcie_rxq_free_rbs(struct iwl_trans *trans)
390 {
391 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392 struct iwl_rxq *rxq = &trans_pcie->rxq;
393 int i;
394
395 lockdep_assert_held(&rxq->lock);
396
397 for (i = 0; i < RX_QUEUE_SIZE; i++) {
398 if (!rxq->pool[i].page)
399 continue;
400 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
401 PAGE_SIZE << trans_pcie->rx_page_order,
402 DMA_FROM_DEVICE);
403 __free_pages(rxq->pool[i].page, trans_pcie->rx_page_order);
404 rxq->pool[i].page = NULL;
405 }
406 }
407
408 /*
409 * iwl_pcie_rx_replenish - Move all used buffers from rx_used to rx_free
410 *
411 * When moving to rx_free an page is allocated for the slot.
412 *
413 * Also restock the Rx queue via iwl_pcie_rxq_restock.
414 * This is called only during initialization
415 */
iwl_pcie_rx_replenish(struct iwl_trans * trans)416 static void iwl_pcie_rx_replenish(struct iwl_trans *trans)
417 {
418 iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL);
419
420 iwl_pcie_rxq_restock(trans);
421 }
422
423 /*
424 * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues
425 *
426 * Allocates for each received request 8 pages
427 * Called as a scheduled work item.
428 */
iwl_pcie_rx_allocator(struct iwl_trans * trans)429 static void iwl_pcie_rx_allocator(struct iwl_trans *trans)
430 {
431 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
432 struct iwl_rb_allocator *rba = &trans_pcie->rba;
433 struct list_head local_empty;
434 int pending = atomic_xchg(&rba->req_pending, 0);
435
436 IWL_DEBUG_RX(trans, "Pending allocation requests = %d\n", pending);
437
438 /* If we were scheduled - there is at least one request */
439 spin_lock(&rba->lock);
440 /* swap out the rba->rbd_empty to a local list */
441 list_replace_init(&rba->rbd_empty, &local_empty);
442 spin_unlock(&rba->lock);
443
444 while (pending) {
445 int i;
446 struct list_head local_allocated;
447
448 INIT_LIST_HEAD(&local_allocated);
449
450 for (i = 0; i < RX_CLAIM_REQ_ALLOC;) {
451 struct iwl_rx_mem_buffer *rxb;
452 struct page *page;
453
454 /* List should never be empty - each reused RBD is
455 * returned to the list, and initial pool covers any
456 * possible gap between the time the page is allocated
457 * to the time the RBD is added.
458 */
459 BUG_ON(list_empty(&local_empty));
460 /* Get the first rxb from the rbd list */
461 rxb = list_first_entry(&local_empty,
462 struct iwl_rx_mem_buffer, list);
463 BUG_ON(rxb->page);
464
465 /* Alloc a new receive buffer */
466 page = iwl_pcie_rx_alloc_page(trans, GFP_KERNEL);
467 if (!page)
468 continue;
469 rxb->page = page;
470
471 /* Get physical address of the RB */
472 rxb->page_dma = dma_map_page(trans->dev, page, 0,
473 PAGE_SIZE << trans_pcie->rx_page_order,
474 DMA_FROM_DEVICE);
475 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
476 rxb->page = NULL;
477 __free_pages(page, trans_pcie->rx_page_order);
478 continue;
479 }
480 /* dma address must be no more than 36 bits */
481 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
482 /* and also 256 byte aligned! */
483 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
484
485 /* move the allocated entry to the out list */
486 list_move(&rxb->list, &local_allocated);
487 i++;
488 }
489
490 pending--;
491 if (!pending) {
492 pending = atomic_xchg(&rba->req_pending, 0);
493 IWL_DEBUG_RX(trans,
494 "Pending allocation requests = %d\n",
495 pending);
496 }
497
498 spin_lock(&rba->lock);
499 /* add the allocated rbds to the allocator allocated list */
500 list_splice_tail(&local_allocated, &rba->rbd_allocated);
501 /* get more empty RBDs for current pending requests */
502 list_splice_tail_init(&rba->rbd_empty, &local_empty);
503 spin_unlock(&rba->lock);
504
505 atomic_inc(&rba->req_ready);
506 }
507
508 spin_lock(&rba->lock);
509 /* return unused rbds to the allocator empty list */
510 list_splice_tail(&local_empty, &rba->rbd_empty);
511 spin_unlock(&rba->lock);
512 }
513
514 /*
515 * iwl_pcie_rx_allocator_get - Returns the pre-allocated pages
516 .*
517 .* Called by queue when the queue posted allocation request and
518 * has freed 8 RBDs in order to restock itself.
519 */
iwl_pcie_rx_allocator_get(struct iwl_trans * trans,struct iwl_rx_mem_buffer * out[RX_CLAIM_REQ_ALLOC])520 static int iwl_pcie_rx_allocator_get(struct iwl_trans *trans,
521 struct iwl_rx_mem_buffer
522 *out[RX_CLAIM_REQ_ALLOC])
523 {
524 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
525 struct iwl_rb_allocator *rba = &trans_pcie->rba;
526 int i;
527
528 /*
529 * atomic_dec_if_positive returns req_ready - 1 for any scenario.
530 * If req_ready is 0 atomic_dec_if_positive will return -1 and this
531 * function will return -ENOMEM, as there are no ready requests.
532 * atomic_dec_if_positive will perofrm the *actual* decrement only if
533 * req_ready > 0, i.e. - there are ready requests and the function
534 * hands one request to the caller.
535 */
536 if (atomic_dec_if_positive(&rba->req_ready) < 0)
537 return -ENOMEM;
538
539 spin_lock(&rba->lock);
540 for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) {
541 /* Get next free Rx buffer, remove it from free list */
542 out[i] = list_first_entry(&rba->rbd_allocated,
543 struct iwl_rx_mem_buffer, list);
544 list_del(&out[i]->list);
545 }
546 spin_unlock(&rba->lock);
547
548 return 0;
549 }
550
iwl_pcie_rx_allocator_work(struct work_struct * data)551 static void iwl_pcie_rx_allocator_work(struct work_struct *data)
552 {
553 struct iwl_rb_allocator *rba_p =
554 container_of(data, struct iwl_rb_allocator, rx_alloc);
555 struct iwl_trans_pcie *trans_pcie =
556 container_of(rba_p, struct iwl_trans_pcie, rba);
557
558 iwl_pcie_rx_allocator(trans_pcie->trans);
559 }
560
iwl_pcie_rx_alloc(struct iwl_trans * trans)561 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
562 {
563 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
564 struct iwl_rxq *rxq = &trans_pcie->rxq;
565 struct iwl_rb_allocator *rba = &trans_pcie->rba;
566 struct device *dev = trans->dev;
567
568 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
569
570 spin_lock_init(&rxq->lock);
571 spin_lock_init(&rba->lock);
572
573 if (WARN_ON(rxq->bd || rxq->rb_stts))
574 return -EINVAL;
575
576 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
577 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
578 &rxq->bd_dma, GFP_KERNEL);
579 if (!rxq->bd)
580 goto err_bd;
581
582 /*Allocate the driver's pointer to receive buffer status */
583 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
584 &rxq->rb_stts_dma, GFP_KERNEL);
585 if (!rxq->rb_stts)
586 goto err_rb_stts;
587
588 return 0;
589
590 err_rb_stts:
591 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
592 rxq->bd, rxq->bd_dma);
593 rxq->bd_dma = 0;
594 rxq->bd = NULL;
595 err_bd:
596 return -ENOMEM;
597 }
598
iwl_pcie_rx_hw_init(struct iwl_trans * trans,struct iwl_rxq * rxq)599 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
600 {
601 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
602 u32 rb_size;
603 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
604
605 if (trans_pcie->rx_buf_size_8k)
606 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
607 else
608 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
609
610 /* Stop Rx DMA */
611 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
612 /* reset and flush pointers */
613 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
614 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
615 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
616
617 /* Reset driver's Rx queue write index */
618 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
619
620 /* Tell device where to find RBD circular buffer in DRAM */
621 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
622 (u32)(rxq->bd_dma >> 8));
623
624 /* Tell device where in DRAM to update its Rx status */
625 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
626 rxq->rb_stts_dma >> 4);
627
628 /* Enable Rx DMA
629 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
630 * the credit mechanism in 5000 HW RX FIFO
631 * Direct rx interrupts to hosts
632 * Rx buffer size 4 or 8k
633 * RB timeout 0x10
634 * 256 RBDs
635 */
636 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
637 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
638 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
639 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
640 rb_size|
641 (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
642 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
643
644 /* Set interrupt coalescing timer to default (2048 usecs) */
645 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
646
647 /* W/A for interrupt coalescing bug in 7260 and 3160 */
648 if (trans->cfg->host_interrupt_operation_mode)
649 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);
650 }
651
iwl_pcie_rx_init_rxb_lists(struct iwl_rxq * rxq)652 static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
653 {
654 int i;
655
656 lockdep_assert_held(&rxq->lock);
657
658 INIT_LIST_HEAD(&rxq->rx_free);
659 INIT_LIST_HEAD(&rxq->rx_used);
660 rxq->free_count = 0;
661 rxq->used_count = 0;
662
663 for (i = 0; i < RX_QUEUE_SIZE; i++)
664 list_add(&rxq->pool[i].list, &rxq->rx_used);
665 }
666
iwl_pcie_rx_init_rba(struct iwl_rb_allocator * rba)667 static void iwl_pcie_rx_init_rba(struct iwl_rb_allocator *rba)
668 {
669 int i;
670
671 lockdep_assert_held(&rba->lock);
672
673 INIT_LIST_HEAD(&rba->rbd_allocated);
674 INIT_LIST_HEAD(&rba->rbd_empty);
675
676 for (i = 0; i < RX_POOL_SIZE; i++)
677 list_add(&rba->pool[i].list, &rba->rbd_empty);
678 }
679
iwl_pcie_rx_free_rba(struct iwl_trans * trans)680 static void iwl_pcie_rx_free_rba(struct iwl_trans *trans)
681 {
682 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
683 struct iwl_rb_allocator *rba = &trans_pcie->rba;
684 int i;
685
686 lockdep_assert_held(&rba->lock);
687
688 for (i = 0; i < RX_POOL_SIZE; i++) {
689 if (!rba->pool[i].page)
690 continue;
691 dma_unmap_page(trans->dev, rba->pool[i].page_dma,
692 PAGE_SIZE << trans_pcie->rx_page_order,
693 DMA_FROM_DEVICE);
694 __free_pages(rba->pool[i].page, trans_pcie->rx_page_order);
695 rba->pool[i].page = NULL;
696 }
697 }
698
iwl_pcie_rx_init(struct iwl_trans * trans)699 int iwl_pcie_rx_init(struct iwl_trans *trans)
700 {
701 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
702 struct iwl_rxq *rxq = &trans_pcie->rxq;
703 struct iwl_rb_allocator *rba = &trans_pcie->rba;
704 int i, err;
705
706 if (!rxq->bd) {
707 err = iwl_pcie_rx_alloc(trans);
708 if (err)
709 return err;
710 }
711 if (!rba->alloc_wq) {
712 rba->alloc_wq = alloc_workqueue("rb_allocator",
713 WQ_HIGHPRI | WQ_UNBOUND, 1);
714 if (!rba->alloc_wq)
715 return -ENOMEM;
716 }
717
718 INIT_WORK(&rba->rx_alloc, iwl_pcie_rx_allocator_work);
719
720 cancel_work_sync(&rba->rx_alloc);
721
722 spin_lock(&rba->lock);
723 atomic_set(&rba->req_pending, 0);
724 atomic_set(&rba->req_ready, 0);
725 /* free all first - we might be reconfigured for a different size */
726 iwl_pcie_rx_free_rba(trans);
727 iwl_pcie_rx_init_rba(rba);
728 spin_unlock(&rba->lock);
729
730 spin_lock(&rxq->lock);
731
732 /* free all first - we might be reconfigured for a different size */
733 iwl_pcie_rxq_free_rbs(trans);
734 iwl_pcie_rx_init_rxb_lists(rxq);
735
736 for (i = 0; i < RX_QUEUE_SIZE; i++)
737 rxq->queue[i] = NULL;
738
739 /* Set us so that we have processed and used all buffers, but have
740 * not restocked the Rx queue with fresh buffers */
741 rxq->read = rxq->write = 0;
742 rxq->write_actual = 0;
743 memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
744 spin_unlock(&rxq->lock);
745
746 iwl_pcie_rx_replenish(trans);
747
748 iwl_pcie_rx_hw_init(trans, rxq);
749
750 spin_lock(&rxq->lock);
751 iwl_pcie_rxq_inc_wr_ptr(trans);
752 spin_unlock(&rxq->lock);
753
754 return 0;
755 }
756
iwl_pcie_rx_free(struct iwl_trans * trans)757 void iwl_pcie_rx_free(struct iwl_trans *trans)
758 {
759 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
760 struct iwl_rxq *rxq = &trans_pcie->rxq;
761 struct iwl_rb_allocator *rba = &trans_pcie->rba;
762
763 /*if rxq->bd is NULL, it means that nothing has been allocated,
764 * exit now */
765 if (!rxq->bd) {
766 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
767 return;
768 }
769
770 cancel_work_sync(&rba->rx_alloc);
771 if (rba->alloc_wq) {
772 destroy_workqueue(rba->alloc_wq);
773 rba->alloc_wq = NULL;
774 }
775
776 spin_lock(&rba->lock);
777 iwl_pcie_rx_free_rba(trans);
778 spin_unlock(&rba->lock);
779
780 spin_lock(&rxq->lock);
781 iwl_pcie_rxq_free_rbs(trans);
782 spin_unlock(&rxq->lock);
783
784 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
785 rxq->bd, rxq->bd_dma);
786 rxq->bd_dma = 0;
787 rxq->bd = NULL;
788
789 if (rxq->rb_stts)
790 dma_free_coherent(trans->dev,
791 sizeof(struct iwl_rb_status),
792 rxq->rb_stts, rxq->rb_stts_dma);
793 else
794 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
795 rxq->rb_stts_dma = 0;
796 rxq->rb_stts = NULL;
797 }
798
799 /*
800 * iwl_pcie_rx_reuse_rbd - Recycle used RBDs
801 *
802 * Called when a RBD can be reused. The RBD is transferred to the allocator.
803 * When there are 2 empty RBDs - a request for allocation is posted
804 */
iwl_pcie_rx_reuse_rbd(struct iwl_trans * trans,struct iwl_rx_mem_buffer * rxb,struct iwl_rxq * rxq,bool emergency)805 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans,
806 struct iwl_rx_mem_buffer *rxb,
807 struct iwl_rxq *rxq, bool emergency)
808 {
809 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
810 struct iwl_rb_allocator *rba = &trans_pcie->rba;
811
812 /* Move the RBD to the used list, will be moved to allocator in batches
813 * before claiming or posting a request*/
814 list_add_tail(&rxb->list, &rxq->rx_used);
815
816 if (unlikely(emergency))
817 return;
818
819 /* Count the allocator owned RBDs */
820 rxq->used_count++;
821
822 /* If we have RX_POST_REQ_ALLOC new released rx buffers -
823 * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is
824 * used for the case we failed to claim RX_CLAIM_REQ_ALLOC,
825 * after but we still need to post another request.
826 */
827 if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) {
828 /* Move the 2 RBDs to the allocator ownership.
829 Allocator has another 6 from pool for the request completion*/
830 spin_lock(&rba->lock);
831 list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty);
832 spin_unlock(&rba->lock);
833
834 atomic_inc(&rba->req_pending);
835 queue_work(rba->alloc_wq, &rba->rx_alloc);
836 }
837 }
838
iwl_pcie_rx_handle_rb(struct iwl_trans * trans,struct iwl_rx_mem_buffer * rxb,bool emergency)839 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
840 struct iwl_rx_mem_buffer *rxb,
841 bool emergency)
842 {
843 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
844 struct iwl_rxq *rxq = &trans_pcie->rxq;
845 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
846 bool page_stolen = false;
847 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
848 u32 offset = 0;
849
850 if (WARN_ON(!rxb))
851 return;
852
853 dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
854
855 while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
856 struct iwl_rx_packet *pkt;
857 u16 sequence;
858 bool reclaim;
859 int index, cmd_index, len;
860 struct iwl_rx_cmd_buffer rxcb = {
861 ._offset = offset,
862 ._rx_page_order = trans_pcie->rx_page_order,
863 ._page = rxb->page,
864 ._page_stolen = false,
865 .truesize = max_len,
866 };
867
868 pkt = rxb_addr(&rxcb);
869
870 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID))
871 break;
872
873 IWL_DEBUG_RX(trans,
874 "cmd at offset %d: %s (0x%.2x, seq 0x%x)\n",
875 rxcb._offset,
876 get_cmd_string(trans_pcie, pkt->hdr.cmd),
877 pkt->hdr.cmd, le16_to_cpu(pkt->hdr.sequence));
878
879 len = iwl_rx_packet_len(pkt);
880 len += sizeof(u32); /* account for status word */
881 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
882 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
883
884 /* Reclaim a command buffer only if this packet is a response
885 * to a (driver-originated) command.
886 * If the packet (e.g. Rx frame) originated from uCode,
887 * there is no command buffer to reclaim.
888 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
889 * but apparently a few don't get set; catch them here. */
890 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
891 if (reclaim) {
892 int i;
893
894 for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
895 if (trans_pcie->no_reclaim_cmds[i] ==
896 pkt->hdr.cmd) {
897 reclaim = false;
898 break;
899 }
900 }
901 }
902
903 sequence = le16_to_cpu(pkt->hdr.sequence);
904 index = SEQ_TO_INDEX(sequence);
905 cmd_index = get_cmd_index(&txq->q, index);
906
907 iwl_op_mode_rx(trans->op_mode, &trans_pcie->napi, &rxcb);
908
909 if (reclaim) {
910 kzfree(txq->entries[cmd_index].free_buf);
911 txq->entries[cmd_index].free_buf = NULL;
912 }
913
914 /*
915 * After here, we should always check rxcb._page_stolen,
916 * if it is true then one of the handlers took the page.
917 */
918
919 if (reclaim) {
920 /* Invoke any callbacks, transfer the buffer to caller,
921 * and fire off the (possibly) blocking
922 * iwl_trans_send_cmd()
923 * as we reclaim the driver command queue */
924 if (!rxcb._page_stolen)
925 iwl_pcie_hcmd_complete(trans, &rxcb);
926 else
927 IWL_WARN(trans, "Claim null rxb?\n");
928 }
929
930 page_stolen |= rxcb._page_stolen;
931 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
932 }
933
934 /* page was stolen from us -- free our reference */
935 if (page_stolen) {
936 __free_pages(rxb->page, trans_pcie->rx_page_order);
937 rxb->page = NULL;
938 }
939
940 /* Reuse the page if possible. For notification packets and
941 * SKBs that fail to Rx correctly, add them back into the
942 * rx_free list for reuse later. */
943 if (rxb->page != NULL) {
944 rxb->page_dma =
945 dma_map_page(trans->dev, rxb->page, 0,
946 PAGE_SIZE << trans_pcie->rx_page_order,
947 DMA_FROM_DEVICE);
948 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
949 /*
950 * free the page(s) as well to not break
951 * the invariant that the items on the used
952 * list have no page(s)
953 */
954 __free_pages(rxb->page, trans_pcie->rx_page_order);
955 rxb->page = NULL;
956 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
957 } else {
958 list_add_tail(&rxb->list, &rxq->rx_free);
959 rxq->free_count++;
960 }
961 } else
962 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
963 }
964
965 /*
966 * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
967 */
iwl_pcie_rx_handle(struct iwl_trans * trans)968 static void iwl_pcie_rx_handle(struct iwl_trans *trans)
969 {
970 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
971 struct iwl_rxq *rxq = &trans_pcie->rxq;
972 u32 r, i, j, count = 0;
973 bool emergency = false;
974
975 restart:
976 spin_lock(&rxq->lock);
977 /* uCode's read index (stored in shared DRAM) indicates the last Rx
978 * buffer that the driver may process (last buffer filled by ucode). */
979 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
980 i = rxq->read;
981
982 /* Rx interrupt, but nothing sent from uCode */
983 if (i == r)
984 IWL_DEBUG_RX(trans, "HW = SW = %d\n", r);
985
986 while (i != r) {
987 struct iwl_rx_mem_buffer *rxb;
988
989 if (unlikely(rxq->used_count == RX_QUEUE_SIZE / 2))
990 emergency = true;
991
992 rxb = rxq->queue[i];
993 rxq->queue[i] = NULL;
994
995 IWL_DEBUG_RX(trans, "rxbuf: HW = %d, SW = %d (%p)\n",
996 r, i, rxb);
997 iwl_pcie_rx_handle_rb(trans, rxb, emergency);
998
999 i = (i + 1) & RX_QUEUE_MASK;
1000
1001 /* If we have RX_CLAIM_REQ_ALLOC released rx buffers -
1002 * try to claim the pre-allocated buffers from the allocator */
1003 if (rxq->used_count >= RX_CLAIM_REQ_ALLOC) {
1004 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1005 struct iwl_rx_mem_buffer *out[RX_CLAIM_REQ_ALLOC];
1006
1007 if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 &&
1008 !emergency) {
1009 /* Add the remaining 6 empty RBDs
1010 * for allocator use
1011 */
1012 spin_lock(&rba->lock);
1013 list_splice_tail_init(&rxq->rx_used,
1014 &rba->rbd_empty);
1015 spin_unlock(&rba->lock);
1016 }
1017
1018 /* If not ready - continue, will try to reclaim later.
1019 * No need to reschedule work - allocator exits only on
1020 * success */
1021 if (!iwl_pcie_rx_allocator_get(trans, out)) {
1022 /* If success - then RX_CLAIM_REQ_ALLOC
1023 * buffers were retrieved and should be added
1024 * to free list */
1025 rxq->used_count -= RX_CLAIM_REQ_ALLOC;
1026 for (j = 0; j < RX_CLAIM_REQ_ALLOC; j++) {
1027 list_add_tail(&out[j]->list,
1028 &rxq->rx_free);
1029 rxq->free_count++;
1030 }
1031 }
1032 }
1033 if (emergency) {
1034 count++;
1035 if (count == 8) {
1036 count = 0;
1037 if (rxq->used_count < RX_QUEUE_SIZE / 3)
1038 emergency = false;
1039 spin_unlock(&rxq->lock);
1040 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC);
1041 spin_lock(&rxq->lock);
1042 }
1043 }
1044 /* handle restock for three cases, can be all of them at once:
1045 * - we just pulled buffers from the allocator
1046 * - we have 8+ unstolen pages accumulated
1047 * - we are in emergency and allocated buffers
1048 */
1049 if (rxq->free_count >= RX_CLAIM_REQ_ALLOC) {
1050 rxq->read = i;
1051 spin_unlock(&rxq->lock);
1052 iwl_pcie_rxq_restock(trans);
1053 goto restart;
1054 }
1055 }
1056
1057 /* Backtrack one entry */
1058 rxq->read = i;
1059 spin_unlock(&rxq->lock);
1060
1061 /*
1062 * handle a case where in emergency there are some unallocated RBDs.
1063 * those RBDs are in the used list, but are not tracked by the queue's
1064 * used_count which counts allocator owned RBDs.
1065 * unallocated emergency RBDs must be allocated on exit, otherwise
1066 * when called again the function may not be in emergency mode and
1067 * they will be handed to the allocator with no tracking in the RBD
1068 * allocator counters, which will lead to them never being claimed back
1069 * by the queue.
1070 * by allocating them here, they are now in the queue free list, and
1071 * will be restocked by the next call of iwl_pcie_rxq_restock.
1072 */
1073 if (unlikely(emergency && count))
1074 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC);
1075
1076 if (trans_pcie->napi.poll)
1077 napi_gro_flush(&trans_pcie->napi, false);
1078 }
1079
1080 /*
1081 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
1082 */
iwl_pcie_irq_handle_error(struct iwl_trans * trans)1083 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
1084 {
1085 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1086 int i;
1087
1088 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
1089 if (trans->cfg->internal_wimax_coex &&
1090 !trans->cfg->apmg_not_supported &&
1091 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
1092 APMS_CLK_VAL_MRB_FUNC_MODE) ||
1093 (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
1094 APMG_PS_CTRL_VAL_RESET_REQ))) {
1095 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1096 iwl_op_mode_wimax_active(trans->op_mode);
1097 wake_up(&trans_pcie->wait_command_queue);
1098 return;
1099 }
1100
1101 iwl_pcie_dump_csr(trans);
1102 iwl_dump_fh(trans, NULL);
1103
1104 local_bh_disable();
1105 /* The STATUS_FW_ERROR bit is set in this function. This must happen
1106 * before we wake up the command caller, to ensure a proper cleanup. */
1107 iwl_trans_fw_error(trans);
1108 local_bh_enable();
1109
1110 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++)
1111 del_timer(&trans_pcie->txq[i].stuck_timer);
1112
1113 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1114 wake_up(&trans_pcie->wait_command_queue);
1115 }
1116
iwl_pcie_int_cause_non_ict(struct iwl_trans * trans)1117 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans)
1118 {
1119 u32 inta;
1120
1121 lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock);
1122
1123 trace_iwlwifi_dev_irq(trans->dev);
1124
1125 /* Discover which interrupts are active/pending */
1126 inta = iwl_read32(trans, CSR_INT);
1127
1128 /* the thread will service interrupts and re-enable them */
1129 return inta;
1130 }
1131
1132 /* a device (PCI-E) page is 4096 bytes long */
1133 #define ICT_SHIFT 12
1134 #define ICT_SIZE (1 << ICT_SHIFT)
1135 #define ICT_COUNT (ICT_SIZE / sizeof(u32))
1136
1137 /* interrupt handler using ict table, with this interrupt driver will
1138 * stop using INTA register to get device's interrupt, reading this register
1139 * is expensive, device will write interrupts in ICT dram table, increment
1140 * index then will fire interrupt to driver, driver will OR all ICT table
1141 * entries from current index up to table entry with 0 value. the result is
1142 * the interrupt we need to service, driver will set the entries back to 0 and
1143 * set index.
1144 */
iwl_pcie_int_cause_ict(struct iwl_trans * trans)1145 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans)
1146 {
1147 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1148 u32 inta;
1149 u32 val = 0;
1150 u32 read;
1151
1152 trace_iwlwifi_dev_irq(trans->dev);
1153
1154 /* Ignore interrupt if there's nothing in NIC to service.
1155 * This may be due to IRQ shared with another device,
1156 * or due to sporadic interrupts thrown from our NIC. */
1157 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1158 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1159 if (!read)
1160 return 0;
1161
1162 /*
1163 * Collect all entries up to the first 0, starting from ict_index;
1164 * note we already read at ict_index.
1165 */
1166 do {
1167 val |= read;
1168 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1169 trans_pcie->ict_index, read);
1170 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1171 trans_pcie->ict_index =
1172 ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1));
1173
1174 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1175 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1176 read);
1177 } while (read);
1178
1179 /* We should not get this value, just ignore it. */
1180 if (val == 0xffffffff)
1181 val = 0;
1182
1183 /*
1184 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1185 * (bit 15 before shifting it to 31) to clear when using interrupt
1186 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1187 * so we use them to decide on the real state of the Rx bit.
1188 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1189 */
1190 if (val & 0xC0000)
1191 val |= 0x8000;
1192
1193 inta = (0xff & val) | ((0xff00 & val) << 16);
1194 return inta;
1195 }
1196
iwl_pcie_irq_handler(int irq,void * dev_id)1197 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
1198 {
1199 struct iwl_trans *trans = dev_id;
1200 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1201 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1202 u32 inta = 0;
1203 u32 handled = 0;
1204
1205 lock_map_acquire(&trans->sync_cmd_lockdep_map);
1206
1207 spin_lock(&trans_pcie->irq_lock);
1208
1209 /* dram interrupt table not set yet,
1210 * use legacy interrupt.
1211 */
1212 if (likely(trans_pcie->use_ict))
1213 inta = iwl_pcie_int_cause_ict(trans);
1214 else
1215 inta = iwl_pcie_int_cause_non_ict(trans);
1216
1217 if (iwl_have_debug_level(IWL_DL_ISR)) {
1218 IWL_DEBUG_ISR(trans,
1219 "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n",
1220 inta, trans_pcie->inta_mask,
1221 iwl_read32(trans, CSR_INT_MASK),
1222 iwl_read32(trans, CSR_FH_INT_STATUS));
1223 if (inta & (~trans_pcie->inta_mask))
1224 IWL_DEBUG_ISR(trans,
1225 "We got a masked interrupt (0x%08x)\n",
1226 inta & (~trans_pcie->inta_mask));
1227 }
1228
1229 inta &= trans_pcie->inta_mask;
1230
1231 /*
1232 * Ignore interrupt if there's nothing in NIC to service.
1233 * This may be due to IRQ shared with another device,
1234 * or due to sporadic interrupts thrown from our NIC.
1235 */
1236 if (unlikely(!inta)) {
1237 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1238 /*
1239 * Re-enable interrupts here since we don't
1240 * have anything to service
1241 */
1242 if (test_bit(STATUS_INT_ENABLED, &trans->status))
1243 iwl_enable_interrupts(trans);
1244 spin_unlock(&trans_pcie->irq_lock);
1245 lock_map_release(&trans->sync_cmd_lockdep_map);
1246 return IRQ_NONE;
1247 }
1248
1249 if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1250 /*
1251 * Hardware disappeared. It might have
1252 * already raised an interrupt.
1253 */
1254 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1255 spin_unlock(&trans_pcie->irq_lock);
1256 goto out;
1257 }
1258
1259 /* Ack/clear/reset pending uCode interrupts.
1260 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1261 */
1262 /* There is a hardware bug in the interrupt mask function that some
1263 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1264 * they are disabled in the CSR_INT_MASK register. Furthermore the
1265 * ICT interrupt handling mechanism has another bug that might cause
1266 * these unmasked interrupts fail to be detected. We workaround the
1267 * hardware bugs here by ACKing all the possible interrupts so that
1268 * interrupt coalescing can still be achieved.
1269 */
1270 iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);
1271
1272 if (iwl_have_debug_level(IWL_DL_ISR))
1273 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
1274 inta, iwl_read32(trans, CSR_INT_MASK));
1275
1276 spin_unlock(&trans_pcie->irq_lock);
1277
1278 /* Now service all interrupt bits discovered above. */
1279 if (inta & CSR_INT_BIT_HW_ERR) {
1280 IWL_ERR(trans, "Hardware error detected. Restarting.\n");
1281
1282 /* Tell the device to stop sending interrupts */
1283 iwl_disable_interrupts(trans);
1284
1285 isr_stats->hw++;
1286 iwl_pcie_irq_handle_error(trans);
1287
1288 handled |= CSR_INT_BIT_HW_ERR;
1289
1290 goto out;
1291 }
1292
1293 if (iwl_have_debug_level(IWL_DL_ISR)) {
1294 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1295 if (inta & CSR_INT_BIT_SCD) {
1296 IWL_DEBUG_ISR(trans,
1297 "Scheduler finished to transmit the frame/frames.\n");
1298 isr_stats->sch++;
1299 }
1300
1301 /* Alive notification via Rx interrupt will do the real work */
1302 if (inta & CSR_INT_BIT_ALIVE) {
1303 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1304 isr_stats->alive++;
1305 }
1306 }
1307
1308 /* Safely ignore these bits for debug checks below */
1309 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1310
1311 /* HW RF KILL switch toggled */
1312 if (inta & CSR_INT_BIT_RF_KILL) {
1313 bool hw_rfkill;
1314
1315 hw_rfkill = iwl_is_rfkill_set(trans);
1316 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1317 hw_rfkill ? "disable radio" : "enable radio");
1318
1319 isr_stats->rfkill++;
1320
1321 mutex_lock(&trans_pcie->mutex);
1322 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1323 mutex_unlock(&trans_pcie->mutex);
1324 if (hw_rfkill) {
1325 set_bit(STATUS_RFKILL, &trans->status);
1326 if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE,
1327 &trans->status))
1328 IWL_DEBUG_RF_KILL(trans,
1329 "Rfkill while SYNC HCMD in flight\n");
1330 wake_up(&trans_pcie->wait_command_queue);
1331 } else {
1332 clear_bit(STATUS_RFKILL, &trans->status);
1333 }
1334
1335 handled |= CSR_INT_BIT_RF_KILL;
1336 }
1337
1338 /* Chip got too hot and stopped itself */
1339 if (inta & CSR_INT_BIT_CT_KILL) {
1340 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1341 isr_stats->ctkill++;
1342 handled |= CSR_INT_BIT_CT_KILL;
1343 }
1344
1345 /* Error detected by uCode */
1346 if (inta & CSR_INT_BIT_SW_ERR) {
1347 IWL_ERR(trans, "Microcode SW error detected. "
1348 " Restarting 0x%X.\n", inta);
1349 isr_stats->sw++;
1350 iwl_pcie_irq_handle_error(trans);
1351 handled |= CSR_INT_BIT_SW_ERR;
1352 }
1353
1354 /* uCode wakes up after power-down sleep */
1355 if (inta & CSR_INT_BIT_WAKEUP) {
1356 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1357 iwl_pcie_rxq_check_wrptr(trans);
1358 iwl_pcie_txq_check_wrptrs(trans);
1359
1360 isr_stats->wakeup++;
1361
1362 handled |= CSR_INT_BIT_WAKEUP;
1363 }
1364
1365 /* All uCode command responses, including Tx command responses,
1366 * Rx "responses" (frame-received notification), and other
1367 * notifications from uCode come through here*/
1368 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1369 CSR_INT_BIT_RX_PERIODIC)) {
1370 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1371 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1372 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1373 iwl_write32(trans, CSR_FH_INT_STATUS,
1374 CSR_FH_INT_RX_MASK);
1375 }
1376 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1377 handled |= CSR_INT_BIT_RX_PERIODIC;
1378 iwl_write32(trans,
1379 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1380 }
1381 /* Sending RX interrupt require many steps to be done in the
1382 * the device:
1383 * 1- write interrupt to current index in ICT table.
1384 * 2- dma RX frame.
1385 * 3- update RX shared data to indicate last write index.
1386 * 4- send interrupt.
1387 * This could lead to RX race, driver could receive RX interrupt
1388 * but the shared data changes does not reflect this;
1389 * periodic interrupt will detect any dangling Rx activity.
1390 */
1391
1392 /* Disable periodic interrupt; we use it as just a one-shot. */
1393 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1394 CSR_INT_PERIODIC_DIS);
1395
1396 /*
1397 * Enable periodic interrupt in 8 msec only if we received
1398 * real RX interrupt (instead of just periodic int), to catch
1399 * any dangling Rx interrupt. If it was just the periodic
1400 * interrupt, there was no dangling Rx activity, and no need
1401 * to extend the periodic interrupt; one-shot is enough.
1402 */
1403 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1404 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1405 CSR_INT_PERIODIC_ENA);
1406
1407 isr_stats->rx++;
1408
1409 local_bh_disable();
1410 iwl_pcie_rx_handle(trans);
1411 local_bh_enable();
1412 }
1413
1414 /* This "Tx" DMA channel is used only for loading uCode */
1415 if (inta & CSR_INT_BIT_FH_TX) {
1416 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1417 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1418 isr_stats->tx++;
1419 handled |= CSR_INT_BIT_FH_TX;
1420 /* Wake up uCode load routine, now that load is complete */
1421 trans_pcie->ucode_write_complete = true;
1422 wake_up(&trans_pcie->ucode_write_waitq);
1423 }
1424
1425 if (inta & ~handled) {
1426 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1427 isr_stats->unhandled++;
1428 }
1429
1430 if (inta & ~(trans_pcie->inta_mask)) {
1431 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1432 inta & ~trans_pcie->inta_mask);
1433 }
1434
1435 /* Re-enable all interrupts */
1436 /* only Re-enable if disabled by irq */
1437 if (test_bit(STATUS_INT_ENABLED, &trans->status))
1438 iwl_enable_interrupts(trans);
1439 /* Re-enable RF_KILL if it occurred */
1440 else if (handled & CSR_INT_BIT_RF_KILL)
1441 iwl_enable_rfkill_int(trans);
1442
1443 out:
1444 lock_map_release(&trans->sync_cmd_lockdep_map);
1445 return IRQ_HANDLED;
1446 }
1447
1448 /******************************************************************************
1449 *
1450 * ICT functions
1451 *
1452 ******************************************************************************/
1453
1454 /* Free dram table */
iwl_pcie_free_ict(struct iwl_trans * trans)1455 void iwl_pcie_free_ict(struct iwl_trans *trans)
1456 {
1457 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1458
1459 if (trans_pcie->ict_tbl) {
1460 dma_free_coherent(trans->dev, ICT_SIZE,
1461 trans_pcie->ict_tbl,
1462 trans_pcie->ict_tbl_dma);
1463 trans_pcie->ict_tbl = NULL;
1464 trans_pcie->ict_tbl_dma = 0;
1465 }
1466 }
1467
1468 /*
1469 * allocate dram shared table, it is an aligned memory
1470 * block of ICT_SIZE.
1471 * also reset all data related to ICT table interrupt.
1472 */
iwl_pcie_alloc_ict(struct iwl_trans * trans)1473 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
1474 {
1475 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1476
1477 trans_pcie->ict_tbl =
1478 dma_zalloc_coherent(trans->dev, ICT_SIZE,
1479 &trans_pcie->ict_tbl_dma,
1480 GFP_KERNEL);
1481 if (!trans_pcie->ict_tbl)
1482 return -ENOMEM;
1483
1484 /* just an API sanity check ... it is guaranteed to be aligned */
1485 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1486 iwl_pcie_free_ict(trans);
1487 return -EINVAL;
1488 }
1489
1490 IWL_DEBUG_ISR(trans, "ict dma addr %Lx ict vir addr %p\n",
1491 (unsigned long long)trans_pcie->ict_tbl_dma,
1492 trans_pcie->ict_tbl);
1493
1494 return 0;
1495 }
1496
1497 /* Device is going up inform it about using ICT interrupt table,
1498 * also we need to tell the driver to start using ICT interrupt.
1499 */
iwl_pcie_reset_ict(struct iwl_trans * trans)1500 void iwl_pcie_reset_ict(struct iwl_trans *trans)
1501 {
1502 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1503 u32 val;
1504
1505 if (!trans_pcie->ict_tbl)
1506 return;
1507
1508 spin_lock(&trans_pcie->irq_lock);
1509 iwl_disable_interrupts(trans);
1510
1511 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1512
1513 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1514
1515 val |= CSR_DRAM_INT_TBL_ENABLE |
1516 CSR_DRAM_INIT_TBL_WRAP_CHECK |
1517 CSR_DRAM_INIT_TBL_WRITE_POINTER;
1518
1519 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1520
1521 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1522 trans_pcie->use_ict = true;
1523 trans_pcie->ict_index = 0;
1524 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1525 iwl_enable_interrupts(trans);
1526 spin_unlock(&trans_pcie->irq_lock);
1527 }
1528
1529 /* Device is going down disable ict interrupt usage */
iwl_pcie_disable_ict(struct iwl_trans * trans)1530 void iwl_pcie_disable_ict(struct iwl_trans *trans)
1531 {
1532 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1533
1534 spin_lock(&trans_pcie->irq_lock);
1535 trans_pcie->use_ict = false;
1536 spin_unlock(&trans_pcie->irq_lock);
1537 }
1538
iwl_pcie_isr(int irq,void * data)1539 irqreturn_t iwl_pcie_isr(int irq, void *data)
1540 {
1541 struct iwl_trans *trans = data;
1542
1543 if (!trans)
1544 return IRQ_NONE;
1545
1546 /* Disable (but don't clear!) interrupts here to avoid
1547 * back-to-back ISRs and sporadic interrupts from our NIC.
1548 * If we have something to service, the tasklet will re-enable ints.
1549 * If we *don't* have something, we'll re-enable before leaving here.
1550 */
1551 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1552
1553 return IRQ_WAKE_THREAD;
1554 }
1555