1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: Instruction/Exception emulation
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 */
11
12 #include <linux/errno.h>
13 #include <linux/err.h>
14 #include <linux/ktime.h>
15 #include <linux/kvm_host.h>
16 #include <linux/module.h>
17 #include <linux/vmalloc.h>
18 #include <linux/fs.h>
19 #include <linux/bootmem.h>
20 #include <linux/random.h>
21 #include <asm/page.h>
22 #include <asm/cacheflush.h>
23 #include <asm/cpu-info.h>
24 #include <asm/mmu_context.h>
25 #include <asm/tlbflush.h>
26 #include <asm/inst.h>
27
28 #undef CONFIG_MIPS_MT
29 #include <asm/r4kcache.h>
30 #define CONFIG_MIPS_MT
31
32 #include "opcode.h"
33 #include "interrupt.h"
34 #include "commpage.h"
35
36 #include "trace.h"
37
38 /*
39 * Compute the return address and do emulate branch simulation, if required.
40 * This function should be called only in branch delay slot active.
41 */
kvm_compute_return_epc(struct kvm_vcpu * vcpu,unsigned long instpc)42 unsigned long kvm_compute_return_epc(struct kvm_vcpu *vcpu,
43 unsigned long instpc)
44 {
45 unsigned int dspcontrol;
46 union mips_instruction insn;
47 struct kvm_vcpu_arch *arch = &vcpu->arch;
48 long epc = instpc;
49 long nextpc = KVM_INVALID_INST;
50
51 if (epc & 3)
52 goto unaligned;
53
54 /* Read the instruction */
55 insn.word = kvm_get_inst((uint32_t *) epc, vcpu);
56
57 if (insn.word == KVM_INVALID_INST)
58 return KVM_INVALID_INST;
59
60 switch (insn.i_format.opcode) {
61 /* jr and jalr are in r_format format. */
62 case spec_op:
63 switch (insn.r_format.func) {
64 case jalr_op:
65 arch->gprs[insn.r_format.rd] = epc + 8;
66 /* Fall through */
67 case jr_op:
68 nextpc = arch->gprs[insn.r_format.rs];
69 break;
70 }
71 break;
72
73 /*
74 * This group contains:
75 * bltz_op, bgez_op, bltzl_op, bgezl_op,
76 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
77 */
78 case bcond_op:
79 switch (insn.i_format.rt) {
80 case bltz_op:
81 case bltzl_op:
82 if ((long)arch->gprs[insn.i_format.rs] < 0)
83 epc = epc + 4 + (insn.i_format.simmediate << 2);
84 else
85 epc += 8;
86 nextpc = epc;
87 break;
88
89 case bgez_op:
90 case bgezl_op:
91 if ((long)arch->gprs[insn.i_format.rs] >= 0)
92 epc = epc + 4 + (insn.i_format.simmediate << 2);
93 else
94 epc += 8;
95 nextpc = epc;
96 break;
97
98 case bltzal_op:
99 case bltzall_op:
100 arch->gprs[31] = epc + 8;
101 if ((long)arch->gprs[insn.i_format.rs] < 0)
102 epc = epc + 4 + (insn.i_format.simmediate << 2);
103 else
104 epc += 8;
105 nextpc = epc;
106 break;
107
108 case bgezal_op:
109 case bgezall_op:
110 arch->gprs[31] = epc + 8;
111 if ((long)arch->gprs[insn.i_format.rs] >= 0)
112 epc = epc + 4 + (insn.i_format.simmediate << 2);
113 else
114 epc += 8;
115 nextpc = epc;
116 break;
117 case bposge32_op:
118 if (!cpu_has_dsp)
119 goto sigill;
120
121 dspcontrol = rddsp(0x01);
122
123 if (dspcontrol >= 32)
124 epc = epc + 4 + (insn.i_format.simmediate << 2);
125 else
126 epc += 8;
127 nextpc = epc;
128 break;
129 }
130 break;
131
132 /* These are unconditional and in j_format. */
133 case jal_op:
134 arch->gprs[31] = instpc + 8;
135 case j_op:
136 epc += 4;
137 epc >>= 28;
138 epc <<= 28;
139 epc |= (insn.j_format.target << 2);
140 nextpc = epc;
141 break;
142
143 /* These are conditional and in i_format. */
144 case beq_op:
145 case beql_op:
146 if (arch->gprs[insn.i_format.rs] ==
147 arch->gprs[insn.i_format.rt])
148 epc = epc + 4 + (insn.i_format.simmediate << 2);
149 else
150 epc += 8;
151 nextpc = epc;
152 break;
153
154 case bne_op:
155 case bnel_op:
156 if (arch->gprs[insn.i_format.rs] !=
157 arch->gprs[insn.i_format.rt])
158 epc = epc + 4 + (insn.i_format.simmediate << 2);
159 else
160 epc += 8;
161 nextpc = epc;
162 break;
163
164 case blez_op: /* not really i_format */
165 case blezl_op:
166 /* rt field assumed to be zero */
167 if ((long)arch->gprs[insn.i_format.rs] <= 0)
168 epc = epc + 4 + (insn.i_format.simmediate << 2);
169 else
170 epc += 8;
171 nextpc = epc;
172 break;
173
174 case bgtz_op:
175 case bgtzl_op:
176 /* rt field assumed to be zero */
177 if ((long)arch->gprs[insn.i_format.rs] > 0)
178 epc = epc + 4 + (insn.i_format.simmediate << 2);
179 else
180 epc += 8;
181 nextpc = epc;
182 break;
183
184 /* And now the FPA/cp1 branch instructions. */
185 case cop1_op:
186 kvm_err("%s: unsupported cop1_op\n", __func__);
187 break;
188 }
189
190 return nextpc;
191
192 unaligned:
193 kvm_err("%s: unaligned epc\n", __func__);
194 return nextpc;
195
196 sigill:
197 kvm_err("%s: DSP branch but not DSP ASE\n", __func__);
198 return nextpc;
199 }
200
update_pc(struct kvm_vcpu * vcpu,uint32_t cause)201 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause)
202 {
203 unsigned long branch_pc;
204 enum emulation_result er = EMULATE_DONE;
205
206 if (cause & CAUSEF_BD) {
207 branch_pc = kvm_compute_return_epc(vcpu, vcpu->arch.pc);
208 if (branch_pc == KVM_INVALID_INST) {
209 er = EMULATE_FAIL;
210 } else {
211 vcpu->arch.pc = branch_pc;
212 kvm_debug("BD update_pc(): New PC: %#lx\n",
213 vcpu->arch.pc);
214 }
215 } else
216 vcpu->arch.pc += 4;
217
218 kvm_debug("update_pc(): New PC: %#lx\n", vcpu->arch.pc);
219
220 return er;
221 }
222
223 /**
224 * kvm_mips_count_disabled() - Find whether the CP0_Count timer is disabled.
225 * @vcpu: Virtual CPU.
226 *
227 * Returns: 1 if the CP0_Count timer is disabled by either the guest
228 * CP0_Cause.DC bit or the count_ctl.DC bit.
229 * 0 otherwise (in which case CP0_Count timer is running).
230 */
kvm_mips_count_disabled(struct kvm_vcpu * vcpu)231 static inline int kvm_mips_count_disabled(struct kvm_vcpu *vcpu)
232 {
233 struct mips_coproc *cop0 = vcpu->arch.cop0;
234
235 return (vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) ||
236 (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC);
237 }
238
239 /**
240 * kvm_mips_ktime_to_count() - Scale ktime_t to a 32-bit count.
241 *
242 * Caches the dynamic nanosecond bias in vcpu->arch.count_dyn_bias.
243 *
244 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
245 */
kvm_mips_ktime_to_count(struct kvm_vcpu * vcpu,ktime_t now)246 static uint32_t kvm_mips_ktime_to_count(struct kvm_vcpu *vcpu, ktime_t now)
247 {
248 s64 now_ns, periods;
249 u64 delta;
250
251 now_ns = ktime_to_ns(now);
252 delta = now_ns + vcpu->arch.count_dyn_bias;
253
254 if (delta >= vcpu->arch.count_period) {
255 /* If delta is out of safe range the bias needs adjusting */
256 periods = div64_s64(now_ns, vcpu->arch.count_period);
257 vcpu->arch.count_dyn_bias = -periods * vcpu->arch.count_period;
258 /* Recalculate delta with new bias */
259 delta = now_ns + vcpu->arch.count_dyn_bias;
260 }
261
262 /*
263 * We've ensured that:
264 * delta < count_period
265 *
266 * Therefore the intermediate delta*count_hz will never overflow since
267 * at the boundary condition:
268 * delta = count_period
269 * delta = NSEC_PER_SEC * 2^32 / count_hz
270 * delta * count_hz = NSEC_PER_SEC * 2^32
271 */
272 return div_u64(delta * vcpu->arch.count_hz, NSEC_PER_SEC);
273 }
274
275 /**
276 * kvm_mips_count_time() - Get effective current time.
277 * @vcpu: Virtual CPU.
278 *
279 * Get effective monotonic ktime. This is usually a straightforward ktime_get(),
280 * except when the master disable bit is set in count_ctl, in which case it is
281 * count_resume, i.e. the time that the count was disabled.
282 *
283 * Returns: Effective monotonic ktime for CP0_Count.
284 */
kvm_mips_count_time(struct kvm_vcpu * vcpu)285 static inline ktime_t kvm_mips_count_time(struct kvm_vcpu *vcpu)
286 {
287 if (unlikely(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC))
288 return vcpu->arch.count_resume;
289
290 return ktime_get();
291 }
292
293 /**
294 * kvm_mips_read_count_running() - Read the current count value as if running.
295 * @vcpu: Virtual CPU.
296 * @now: Kernel time to read CP0_Count at.
297 *
298 * Returns the current guest CP0_Count register at time @now and handles if the
299 * timer interrupt is pending and hasn't been handled yet.
300 *
301 * Returns: The current value of the guest CP0_Count register.
302 */
kvm_mips_read_count_running(struct kvm_vcpu * vcpu,ktime_t now)303 static uint32_t kvm_mips_read_count_running(struct kvm_vcpu *vcpu, ktime_t now)
304 {
305 struct mips_coproc *cop0 = vcpu->arch.cop0;
306 ktime_t expires, threshold;
307 uint32_t count, compare;
308 int running;
309
310 /* Calculate the biased and scaled guest CP0_Count */
311 count = vcpu->arch.count_bias + kvm_mips_ktime_to_count(vcpu, now);
312 compare = kvm_read_c0_guest_compare(cop0);
313
314 /*
315 * Find whether CP0_Count has reached the closest timer interrupt. If
316 * not, we shouldn't inject it.
317 */
318 if ((int32_t)(count - compare) < 0)
319 return count;
320
321 /*
322 * The CP0_Count we're going to return has already reached the closest
323 * timer interrupt. Quickly check if it really is a new interrupt by
324 * looking at whether the interval until the hrtimer expiry time is
325 * less than 1/4 of the timer period.
326 */
327 expires = hrtimer_get_expires(&vcpu->arch.comparecount_timer);
328 threshold = ktime_add_ns(now, vcpu->arch.count_period / 4);
329 if (ktime_before(expires, threshold)) {
330 /*
331 * Cancel it while we handle it so there's no chance of
332 * interference with the timeout handler.
333 */
334 running = hrtimer_cancel(&vcpu->arch.comparecount_timer);
335
336 /* Nothing should be waiting on the timeout */
337 kvm_mips_callbacks->queue_timer_int(vcpu);
338
339 /*
340 * Restart the timer if it was running based on the expiry time
341 * we read, so that we don't push it back 2 periods.
342 */
343 if (running) {
344 expires = ktime_add_ns(expires,
345 vcpu->arch.count_period);
346 hrtimer_start(&vcpu->arch.comparecount_timer, expires,
347 HRTIMER_MODE_ABS);
348 }
349 }
350
351 return count;
352 }
353
354 /**
355 * kvm_mips_read_count() - Read the current count value.
356 * @vcpu: Virtual CPU.
357 *
358 * Read the current guest CP0_Count value, taking into account whether the timer
359 * is stopped.
360 *
361 * Returns: The current guest CP0_Count value.
362 */
kvm_mips_read_count(struct kvm_vcpu * vcpu)363 uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu)
364 {
365 struct mips_coproc *cop0 = vcpu->arch.cop0;
366
367 /* If count disabled just read static copy of count */
368 if (kvm_mips_count_disabled(vcpu))
369 return kvm_read_c0_guest_count(cop0);
370
371 return kvm_mips_read_count_running(vcpu, ktime_get());
372 }
373
374 /**
375 * kvm_mips_freeze_hrtimer() - Safely stop the hrtimer.
376 * @vcpu: Virtual CPU.
377 * @count: Output pointer for CP0_Count value at point of freeze.
378 *
379 * Freeze the hrtimer safely and return both the ktime and the CP0_Count value
380 * at the point it was frozen. It is guaranteed that any pending interrupts at
381 * the point it was frozen are handled, and none after that point.
382 *
383 * This is useful where the time/CP0_Count is needed in the calculation of the
384 * new parameters.
385 *
386 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
387 *
388 * Returns: The ktime at the point of freeze.
389 */
kvm_mips_freeze_hrtimer(struct kvm_vcpu * vcpu,uint32_t * count)390 static ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu,
391 uint32_t *count)
392 {
393 ktime_t now;
394
395 /* stop hrtimer before finding time */
396 hrtimer_cancel(&vcpu->arch.comparecount_timer);
397 now = ktime_get();
398
399 /* find count at this point and handle pending hrtimer */
400 *count = kvm_mips_read_count_running(vcpu, now);
401
402 return now;
403 }
404
405 /**
406 * kvm_mips_resume_hrtimer() - Resume hrtimer, updating expiry.
407 * @vcpu: Virtual CPU.
408 * @now: ktime at point of resume.
409 * @count: CP0_Count at point of resume.
410 *
411 * Resumes the timer and updates the timer expiry based on @now and @count.
412 * This can be used in conjunction with kvm_mips_freeze_timer() when timer
413 * parameters need to be changed.
414 *
415 * It is guaranteed that a timer interrupt immediately after resume will be
416 * handled, but not if CP_Compare is exactly at @count. That case is already
417 * handled by kvm_mips_freeze_timer().
418 *
419 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
420 */
kvm_mips_resume_hrtimer(struct kvm_vcpu * vcpu,ktime_t now,uint32_t count)421 static void kvm_mips_resume_hrtimer(struct kvm_vcpu *vcpu,
422 ktime_t now, uint32_t count)
423 {
424 struct mips_coproc *cop0 = vcpu->arch.cop0;
425 uint32_t compare;
426 u64 delta;
427 ktime_t expire;
428
429 /* Calculate timeout (wrap 0 to 2^32) */
430 compare = kvm_read_c0_guest_compare(cop0);
431 delta = (u64)(uint32_t)(compare - count - 1) + 1;
432 delta = div_u64(delta * NSEC_PER_SEC, vcpu->arch.count_hz);
433 expire = ktime_add_ns(now, delta);
434
435 /* Update hrtimer to use new timeout */
436 hrtimer_cancel(&vcpu->arch.comparecount_timer);
437 hrtimer_start(&vcpu->arch.comparecount_timer, expire, HRTIMER_MODE_ABS);
438 }
439
440 /**
441 * kvm_mips_write_count() - Modify the count and update timer.
442 * @vcpu: Virtual CPU.
443 * @count: Guest CP0_Count value to set.
444 *
445 * Sets the CP0_Count value and updates the timer accordingly.
446 */
kvm_mips_write_count(struct kvm_vcpu * vcpu,uint32_t count)447 void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count)
448 {
449 struct mips_coproc *cop0 = vcpu->arch.cop0;
450 ktime_t now;
451
452 /* Calculate bias */
453 now = kvm_mips_count_time(vcpu);
454 vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now);
455
456 if (kvm_mips_count_disabled(vcpu))
457 /* The timer's disabled, adjust the static count */
458 kvm_write_c0_guest_count(cop0, count);
459 else
460 /* Update timeout */
461 kvm_mips_resume_hrtimer(vcpu, now, count);
462 }
463
464 /**
465 * kvm_mips_init_count() - Initialise timer.
466 * @vcpu: Virtual CPU.
467 *
468 * Initialise the timer to a sensible frequency, namely 100MHz, zero it, and set
469 * it going if it's enabled.
470 */
kvm_mips_init_count(struct kvm_vcpu * vcpu)471 void kvm_mips_init_count(struct kvm_vcpu *vcpu)
472 {
473 /* 100 MHz */
474 vcpu->arch.count_hz = 100*1000*1000;
475 vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32,
476 vcpu->arch.count_hz);
477 vcpu->arch.count_dyn_bias = 0;
478
479 /* Starting at 0 */
480 kvm_mips_write_count(vcpu, 0);
481 }
482
483 /**
484 * kvm_mips_set_count_hz() - Update the frequency of the timer.
485 * @vcpu: Virtual CPU.
486 * @count_hz: Frequency of CP0_Count timer in Hz.
487 *
488 * Change the frequency of the CP0_Count timer. This is done atomically so that
489 * CP0_Count is continuous and no timer interrupt is lost.
490 *
491 * Returns: -EINVAL if @count_hz is out of range.
492 * 0 on success.
493 */
kvm_mips_set_count_hz(struct kvm_vcpu * vcpu,s64 count_hz)494 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz)
495 {
496 struct mips_coproc *cop0 = vcpu->arch.cop0;
497 int dc;
498 ktime_t now;
499 u32 count;
500
501 /* ensure the frequency is in a sensible range... */
502 if (count_hz <= 0 || count_hz > NSEC_PER_SEC)
503 return -EINVAL;
504 /* ... and has actually changed */
505 if (vcpu->arch.count_hz == count_hz)
506 return 0;
507
508 /* Safely freeze timer so we can keep it continuous */
509 dc = kvm_mips_count_disabled(vcpu);
510 if (dc) {
511 now = kvm_mips_count_time(vcpu);
512 count = kvm_read_c0_guest_count(cop0);
513 } else {
514 now = kvm_mips_freeze_hrtimer(vcpu, &count);
515 }
516
517 /* Update the frequency */
518 vcpu->arch.count_hz = count_hz;
519 vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, count_hz);
520 vcpu->arch.count_dyn_bias = 0;
521
522 /* Calculate adjusted bias so dynamic count is unchanged */
523 vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now);
524
525 /* Update and resume hrtimer */
526 if (!dc)
527 kvm_mips_resume_hrtimer(vcpu, now, count);
528 return 0;
529 }
530
531 /**
532 * kvm_mips_write_compare() - Modify compare and update timer.
533 * @vcpu: Virtual CPU.
534 * @compare: New CP0_Compare value.
535 * @ack: Whether to acknowledge timer interrupt.
536 *
537 * Update CP0_Compare to a new value and update the timeout.
538 * If @ack, atomically acknowledge any pending timer interrupt, otherwise ensure
539 * any pending timer interrupt is preserved.
540 */
kvm_mips_write_compare(struct kvm_vcpu * vcpu,uint32_t compare,bool ack)541 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare, bool ack)
542 {
543 struct mips_coproc *cop0 = vcpu->arch.cop0;
544 int dc;
545 u32 old_compare = kvm_read_c0_guest_compare(cop0);
546 ktime_t now;
547 uint32_t count;
548
549 /* if unchanged, must just be an ack */
550 if (old_compare == compare) {
551 if (!ack)
552 return;
553 kvm_mips_callbacks->dequeue_timer_int(vcpu);
554 kvm_write_c0_guest_compare(cop0, compare);
555 return;
556 }
557
558 /* freeze_hrtimer() takes care of timer interrupts <= count */
559 dc = kvm_mips_count_disabled(vcpu);
560 if (!dc)
561 now = kvm_mips_freeze_hrtimer(vcpu, &count);
562
563 if (ack)
564 kvm_mips_callbacks->dequeue_timer_int(vcpu);
565
566 kvm_write_c0_guest_compare(cop0, compare);
567
568 /* resume_hrtimer() takes care of timer interrupts > count */
569 if (!dc)
570 kvm_mips_resume_hrtimer(vcpu, now, count);
571 }
572
573 /**
574 * kvm_mips_count_disable() - Disable count.
575 * @vcpu: Virtual CPU.
576 *
577 * Disable the CP0_Count timer. A timer interrupt on or before the final stop
578 * time will be handled but not after.
579 *
580 * Assumes CP0_Count was previously enabled but now Guest.CP0_Cause.DC or
581 * count_ctl.DC has been set (count disabled).
582 *
583 * Returns: The time that the timer was stopped.
584 */
kvm_mips_count_disable(struct kvm_vcpu * vcpu)585 static ktime_t kvm_mips_count_disable(struct kvm_vcpu *vcpu)
586 {
587 struct mips_coproc *cop0 = vcpu->arch.cop0;
588 uint32_t count;
589 ktime_t now;
590
591 /* Stop hrtimer */
592 hrtimer_cancel(&vcpu->arch.comparecount_timer);
593
594 /* Set the static count from the dynamic count, handling pending TI */
595 now = ktime_get();
596 count = kvm_mips_read_count_running(vcpu, now);
597 kvm_write_c0_guest_count(cop0, count);
598
599 return now;
600 }
601
602 /**
603 * kvm_mips_count_disable_cause() - Disable count using CP0_Cause.DC.
604 * @vcpu: Virtual CPU.
605 *
606 * Disable the CP0_Count timer and set CP0_Cause.DC. A timer interrupt on or
607 * before the final stop time will be handled if the timer isn't disabled by
608 * count_ctl.DC, but not after.
609 *
610 * Assumes CP0_Cause.DC is clear (count enabled).
611 */
kvm_mips_count_disable_cause(struct kvm_vcpu * vcpu)612 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu)
613 {
614 struct mips_coproc *cop0 = vcpu->arch.cop0;
615
616 kvm_set_c0_guest_cause(cop0, CAUSEF_DC);
617 if (!(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC))
618 kvm_mips_count_disable(vcpu);
619 }
620
621 /**
622 * kvm_mips_count_enable_cause() - Enable count using CP0_Cause.DC.
623 * @vcpu: Virtual CPU.
624 *
625 * Enable the CP0_Count timer and clear CP0_Cause.DC. A timer interrupt after
626 * the start time will be handled if the timer isn't disabled by count_ctl.DC,
627 * potentially before even returning, so the caller should be careful with
628 * ordering of CP0_Cause modifications so as not to lose it.
629 *
630 * Assumes CP0_Cause.DC is set (count disabled).
631 */
kvm_mips_count_enable_cause(struct kvm_vcpu * vcpu)632 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu)
633 {
634 struct mips_coproc *cop0 = vcpu->arch.cop0;
635 uint32_t count;
636
637 kvm_clear_c0_guest_cause(cop0, CAUSEF_DC);
638
639 /*
640 * Set the dynamic count to match the static count.
641 * This starts the hrtimer if count_ctl.DC allows it.
642 * Otherwise it conveniently updates the biases.
643 */
644 count = kvm_read_c0_guest_count(cop0);
645 kvm_mips_write_count(vcpu, count);
646 }
647
648 /**
649 * kvm_mips_set_count_ctl() - Update the count control KVM register.
650 * @vcpu: Virtual CPU.
651 * @count_ctl: Count control register new value.
652 *
653 * Set the count control KVM register. The timer is updated accordingly.
654 *
655 * Returns: -EINVAL if reserved bits are set.
656 * 0 on success.
657 */
kvm_mips_set_count_ctl(struct kvm_vcpu * vcpu,s64 count_ctl)658 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl)
659 {
660 struct mips_coproc *cop0 = vcpu->arch.cop0;
661 s64 changed = count_ctl ^ vcpu->arch.count_ctl;
662 s64 delta;
663 ktime_t expire, now;
664 uint32_t count, compare;
665
666 /* Only allow defined bits to be changed */
667 if (changed & ~(s64)(KVM_REG_MIPS_COUNT_CTL_DC))
668 return -EINVAL;
669
670 /* Apply new value */
671 vcpu->arch.count_ctl = count_ctl;
672
673 /* Master CP0_Count disable */
674 if (changed & KVM_REG_MIPS_COUNT_CTL_DC) {
675 /* Is CP0_Cause.DC already disabling CP0_Count? */
676 if (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC) {
677 if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)
678 /* Just record the current time */
679 vcpu->arch.count_resume = ktime_get();
680 } else if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) {
681 /* disable timer and record current time */
682 vcpu->arch.count_resume = kvm_mips_count_disable(vcpu);
683 } else {
684 /*
685 * Calculate timeout relative to static count at resume
686 * time (wrap 0 to 2^32).
687 */
688 count = kvm_read_c0_guest_count(cop0);
689 compare = kvm_read_c0_guest_compare(cop0);
690 delta = (u64)(uint32_t)(compare - count - 1) + 1;
691 delta = div_u64(delta * NSEC_PER_SEC,
692 vcpu->arch.count_hz);
693 expire = ktime_add_ns(vcpu->arch.count_resume, delta);
694
695 /* Handle pending interrupt */
696 now = ktime_get();
697 if (ktime_compare(now, expire) >= 0)
698 /* Nothing should be waiting on the timeout */
699 kvm_mips_callbacks->queue_timer_int(vcpu);
700
701 /* Resume hrtimer without changing bias */
702 count = kvm_mips_read_count_running(vcpu, now);
703 kvm_mips_resume_hrtimer(vcpu, now, count);
704 }
705 }
706
707 return 0;
708 }
709
710 /**
711 * kvm_mips_set_count_resume() - Update the count resume KVM register.
712 * @vcpu: Virtual CPU.
713 * @count_resume: Count resume register new value.
714 *
715 * Set the count resume KVM register.
716 *
717 * Returns: -EINVAL if out of valid range (0..now).
718 * 0 on success.
719 */
kvm_mips_set_count_resume(struct kvm_vcpu * vcpu,s64 count_resume)720 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume)
721 {
722 /*
723 * It doesn't make sense for the resume time to be in the future, as it
724 * would be possible for the next interrupt to be more than a full
725 * period in the future.
726 */
727 if (count_resume < 0 || count_resume > ktime_to_ns(ktime_get()))
728 return -EINVAL;
729
730 vcpu->arch.count_resume = ns_to_ktime(count_resume);
731 return 0;
732 }
733
734 /**
735 * kvm_mips_count_timeout() - Push timer forward on timeout.
736 * @vcpu: Virtual CPU.
737 *
738 * Handle an hrtimer event by push the hrtimer forward a period.
739 *
740 * Returns: The hrtimer_restart value to return to the hrtimer subsystem.
741 */
kvm_mips_count_timeout(struct kvm_vcpu * vcpu)742 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu)
743 {
744 /* Add the Count period to the current expiry time */
745 hrtimer_add_expires_ns(&vcpu->arch.comparecount_timer,
746 vcpu->arch.count_period);
747 return HRTIMER_RESTART;
748 }
749
kvm_mips_emul_eret(struct kvm_vcpu * vcpu)750 enum emulation_result kvm_mips_emul_eret(struct kvm_vcpu *vcpu)
751 {
752 struct mips_coproc *cop0 = vcpu->arch.cop0;
753 enum emulation_result er = EMULATE_DONE;
754
755 if (kvm_read_c0_guest_status(cop0) & ST0_ERL) {
756 kvm_clear_c0_guest_status(cop0, ST0_ERL);
757 vcpu->arch.pc = kvm_read_c0_guest_errorepc(cop0);
758 } else if (kvm_read_c0_guest_status(cop0) & ST0_EXL) {
759 kvm_debug("[%#lx] ERET to %#lx\n", vcpu->arch.pc,
760 kvm_read_c0_guest_epc(cop0));
761 kvm_clear_c0_guest_status(cop0, ST0_EXL);
762 vcpu->arch.pc = kvm_read_c0_guest_epc(cop0);
763
764 } else {
765 kvm_err("[%#lx] ERET when MIPS_SR_EXL|MIPS_SR_ERL == 0\n",
766 vcpu->arch.pc);
767 er = EMULATE_FAIL;
768 }
769
770 return er;
771 }
772
kvm_mips_emul_wait(struct kvm_vcpu * vcpu)773 enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu)
774 {
775 kvm_debug("[%#lx] !!!WAIT!!! (%#lx)\n", vcpu->arch.pc,
776 vcpu->arch.pending_exceptions);
777
778 ++vcpu->stat.wait_exits;
779 trace_kvm_exit(vcpu, WAIT_EXITS);
780 if (!vcpu->arch.pending_exceptions) {
781 vcpu->arch.wait = 1;
782 kvm_vcpu_block(vcpu);
783
784 /*
785 * We we are runnable, then definitely go off to user space to
786 * check if any I/O interrupts are pending.
787 */
788 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
789 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
790 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
791 }
792 }
793
794 return EMULATE_DONE;
795 }
796
797 /*
798 * XXXKYMA: Linux doesn't seem to use TLBR, return EMULATE_FAIL for now so that
799 * we can catch this, if things ever change
800 */
kvm_mips_emul_tlbr(struct kvm_vcpu * vcpu)801 enum emulation_result kvm_mips_emul_tlbr(struct kvm_vcpu *vcpu)
802 {
803 struct mips_coproc *cop0 = vcpu->arch.cop0;
804 uint32_t pc = vcpu->arch.pc;
805
806 kvm_err("[%#x] COP0_TLBR [%ld]\n", pc, kvm_read_c0_guest_index(cop0));
807 return EMULATE_FAIL;
808 }
809
810 /**
811 * kvm_mips_invalidate_guest_tlb() - Indicates a change in guest MMU map.
812 * @vcpu: VCPU with changed mappings.
813 * @tlb: TLB entry being removed.
814 *
815 * This is called to indicate a single change in guest MMU mappings, so that we
816 * can arrange TLB flushes on this and other CPUs.
817 */
kvm_mips_invalidate_guest_tlb(struct kvm_vcpu * vcpu,struct kvm_mips_tlb * tlb)818 static void kvm_mips_invalidate_guest_tlb(struct kvm_vcpu *vcpu,
819 struct kvm_mips_tlb *tlb)
820 {
821 int cpu, i;
822 bool user;
823
824 /* No need to flush for entries which are already invalid */
825 if (!((tlb->tlb_lo0 | tlb->tlb_lo1) & MIPS3_PG_V))
826 return;
827 /* User address space doesn't need flushing for KSeg2/3 changes */
828 user = tlb->tlb_hi < KVM_GUEST_KSEG0;
829
830 preempt_disable();
831
832 /*
833 * Probe the shadow host TLB for the entry being overwritten, if one
834 * matches, invalidate it
835 */
836 kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi);
837
838 /* Invalidate the whole ASID on other CPUs */
839 cpu = smp_processor_id();
840 for_each_possible_cpu(i) {
841 if (i == cpu)
842 continue;
843 if (user)
844 vcpu->arch.guest_user_asid[i] = 0;
845 vcpu->arch.guest_kernel_asid[i] = 0;
846 }
847
848 preempt_enable();
849 }
850
851 /* Write Guest TLB Entry @ Index */
kvm_mips_emul_tlbwi(struct kvm_vcpu * vcpu)852 enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu)
853 {
854 struct mips_coproc *cop0 = vcpu->arch.cop0;
855 int index = kvm_read_c0_guest_index(cop0);
856 struct kvm_mips_tlb *tlb = NULL;
857 uint32_t pc = vcpu->arch.pc;
858
859 if (index < 0 || index >= KVM_MIPS_GUEST_TLB_SIZE) {
860 kvm_debug("%s: illegal index: %d\n", __func__, index);
861 kvm_debug("[%#x] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
862 pc, index, kvm_read_c0_guest_entryhi(cop0),
863 kvm_read_c0_guest_entrylo0(cop0),
864 kvm_read_c0_guest_entrylo1(cop0),
865 kvm_read_c0_guest_pagemask(cop0));
866 index = (index & ~0x80000000) % KVM_MIPS_GUEST_TLB_SIZE;
867 }
868
869 tlb = &vcpu->arch.guest_tlb[index];
870
871 kvm_mips_invalidate_guest_tlb(vcpu, tlb);
872
873 tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
874 tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
875 tlb->tlb_lo0 = kvm_read_c0_guest_entrylo0(cop0);
876 tlb->tlb_lo1 = kvm_read_c0_guest_entrylo1(cop0);
877
878 kvm_debug("[%#x] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
879 pc, index, kvm_read_c0_guest_entryhi(cop0),
880 kvm_read_c0_guest_entrylo0(cop0),
881 kvm_read_c0_guest_entrylo1(cop0),
882 kvm_read_c0_guest_pagemask(cop0));
883
884 return EMULATE_DONE;
885 }
886
887 /* Write Guest TLB Entry @ Random Index */
kvm_mips_emul_tlbwr(struct kvm_vcpu * vcpu)888 enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu)
889 {
890 struct mips_coproc *cop0 = vcpu->arch.cop0;
891 struct kvm_mips_tlb *tlb = NULL;
892 uint32_t pc = vcpu->arch.pc;
893 int index;
894
895 get_random_bytes(&index, sizeof(index));
896 index &= (KVM_MIPS_GUEST_TLB_SIZE - 1);
897
898 tlb = &vcpu->arch.guest_tlb[index];
899
900 kvm_mips_invalidate_guest_tlb(vcpu, tlb);
901
902 tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
903 tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
904 tlb->tlb_lo0 = kvm_read_c0_guest_entrylo0(cop0);
905 tlb->tlb_lo1 = kvm_read_c0_guest_entrylo1(cop0);
906
907 kvm_debug("[%#x] COP0_TLBWR[%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx)\n",
908 pc, index, kvm_read_c0_guest_entryhi(cop0),
909 kvm_read_c0_guest_entrylo0(cop0),
910 kvm_read_c0_guest_entrylo1(cop0));
911
912 return EMULATE_DONE;
913 }
914
kvm_mips_emul_tlbp(struct kvm_vcpu * vcpu)915 enum emulation_result kvm_mips_emul_tlbp(struct kvm_vcpu *vcpu)
916 {
917 struct mips_coproc *cop0 = vcpu->arch.cop0;
918 long entryhi = kvm_read_c0_guest_entryhi(cop0);
919 uint32_t pc = vcpu->arch.pc;
920 int index = -1;
921
922 index = kvm_mips_guest_tlb_lookup(vcpu, entryhi);
923
924 kvm_write_c0_guest_index(cop0, index);
925
926 kvm_debug("[%#x] COP0_TLBP (entryhi: %#lx), index: %d\n", pc, entryhi,
927 index);
928
929 return EMULATE_DONE;
930 }
931
932 /**
933 * kvm_mips_config1_wrmask() - Find mask of writable bits in guest Config1
934 * @vcpu: Virtual CPU.
935 *
936 * Finds the mask of bits which are writable in the guest's Config1 CP0
937 * register, by userland (currently read-only to the guest).
938 */
kvm_mips_config1_wrmask(struct kvm_vcpu * vcpu)939 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu)
940 {
941 unsigned int mask = 0;
942
943 /* Permit FPU to be present if FPU is supported */
944 if (kvm_mips_guest_can_have_fpu(&vcpu->arch))
945 mask |= MIPS_CONF1_FP;
946
947 return mask;
948 }
949
950 /**
951 * kvm_mips_config3_wrmask() - Find mask of writable bits in guest Config3
952 * @vcpu: Virtual CPU.
953 *
954 * Finds the mask of bits which are writable in the guest's Config3 CP0
955 * register, by userland (currently read-only to the guest).
956 */
kvm_mips_config3_wrmask(struct kvm_vcpu * vcpu)957 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu)
958 {
959 /* Config4 is optional */
960 unsigned int mask = MIPS_CONF_M;
961
962 /* Permit MSA to be present if MSA is supported */
963 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
964 mask |= MIPS_CONF3_MSA;
965
966 return mask;
967 }
968
969 /**
970 * kvm_mips_config4_wrmask() - Find mask of writable bits in guest Config4
971 * @vcpu: Virtual CPU.
972 *
973 * Finds the mask of bits which are writable in the guest's Config4 CP0
974 * register, by userland (currently read-only to the guest).
975 */
kvm_mips_config4_wrmask(struct kvm_vcpu * vcpu)976 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu)
977 {
978 /* Config5 is optional */
979 return MIPS_CONF_M;
980 }
981
982 /**
983 * kvm_mips_config5_wrmask() - Find mask of writable bits in guest Config5
984 * @vcpu: Virtual CPU.
985 *
986 * Finds the mask of bits which are writable in the guest's Config5 CP0
987 * register, by the guest itself.
988 */
kvm_mips_config5_wrmask(struct kvm_vcpu * vcpu)989 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu)
990 {
991 unsigned int mask = 0;
992
993 /* Permit MSAEn changes if MSA supported and enabled */
994 if (kvm_mips_guest_has_msa(&vcpu->arch))
995 mask |= MIPS_CONF5_MSAEN;
996
997 /*
998 * Permit guest FPU mode changes if FPU is enabled and the relevant
999 * feature exists according to FIR register.
1000 */
1001 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1002 if (cpu_has_fre)
1003 mask |= MIPS_CONF5_FRE;
1004 /* We don't support UFR or UFE */
1005 }
1006
1007 return mask;
1008 }
1009
kvm_mips_emulate_CP0(uint32_t inst,uint32_t * opc,uint32_t cause,struct kvm_run * run,struct kvm_vcpu * vcpu)1010 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst, uint32_t *opc,
1011 uint32_t cause, struct kvm_run *run,
1012 struct kvm_vcpu *vcpu)
1013 {
1014 struct mips_coproc *cop0 = vcpu->arch.cop0;
1015 enum emulation_result er = EMULATE_DONE;
1016 int32_t rt, rd, copz, sel, co_bit, op;
1017 uint32_t pc = vcpu->arch.pc;
1018 unsigned long curr_pc;
1019 int cpu, i;
1020
1021 /*
1022 * Update PC and hold onto current PC in case there is
1023 * an error and we want to rollback the PC
1024 */
1025 curr_pc = vcpu->arch.pc;
1026 er = update_pc(vcpu, cause);
1027 if (er == EMULATE_FAIL)
1028 return er;
1029
1030 copz = (inst >> 21) & 0x1f;
1031 rt = (inst >> 16) & 0x1f;
1032 rd = (inst >> 11) & 0x1f;
1033 sel = inst & 0x7;
1034 co_bit = (inst >> 25) & 1;
1035
1036 if (co_bit) {
1037 op = (inst) & 0xff;
1038
1039 switch (op) {
1040 case tlbr_op: /* Read indexed TLB entry */
1041 er = kvm_mips_emul_tlbr(vcpu);
1042 break;
1043 case tlbwi_op: /* Write indexed */
1044 er = kvm_mips_emul_tlbwi(vcpu);
1045 break;
1046 case tlbwr_op: /* Write random */
1047 er = kvm_mips_emul_tlbwr(vcpu);
1048 break;
1049 case tlbp_op: /* TLB Probe */
1050 er = kvm_mips_emul_tlbp(vcpu);
1051 break;
1052 case rfe_op:
1053 kvm_err("!!!COP0_RFE!!!\n");
1054 break;
1055 case eret_op:
1056 er = kvm_mips_emul_eret(vcpu);
1057 goto dont_update_pc;
1058 break;
1059 case wait_op:
1060 er = kvm_mips_emul_wait(vcpu);
1061 break;
1062 }
1063 } else {
1064 switch (copz) {
1065 case mfc_op:
1066 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
1067 cop0->stat[rd][sel]++;
1068 #endif
1069 /* Get reg */
1070 if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {
1071 vcpu->arch.gprs[rt] = kvm_mips_read_count(vcpu);
1072 } else if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) {
1073 vcpu->arch.gprs[rt] = 0x0;
1074 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1075 kvm_mips_trans_mfc0(inst, opc, vcpu);
1076 #endif
1077 } else {
1078 vcpu->arch.gprs[rt] = cop0->reg[rd][sel];
1079
1080 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1081 kvm_mips_trans_mfc0(inst, opc, vcpu);
1082 #endif
1083 }
1084
1085 kvm_debug
1086 ("[%#x] MFCz[%d][%d], vcpu->arch.gprs[%d]: %#lx\n",
1087 pc, rd, sel, rt, vcpu->arch.gprs[rt]);
1088
1089 break;
1090
1091 case dmfc_op:
1092 vcpu->arch.gprs[rt] = cop0->reg[rd][sel];
1093 break;
1094
1095 case mtc_op:
1096 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
1097 cop0->stat[rd][sel]++;
1098 #endif
1099 if ((rd == MIPS_CP0_TLB_INDEX)
1100 && (vcpu->arch.gprs[rt] >=
1101 KVM_MIPS_GUEST_TLB_SIZE)) {
1102 kvm_err("Invalid TLB Index: %ld",
1103 vcpu->arch.gprs[rt]);
1104 er = EMULATE_FAIL;
1105 break;
1106 }
1107 #define C0_EBASE_CORE_MASK 0xff
1108 if ((rd == MIPS_CP0_PRID) && (sel == 1)) {
1109 /* Preserve CORE number */
1110 kvm_change_c0_guest_ebase(cop0,
1111 ~(C0_EBASE_CORE_MASK),
1112 vcpu->arch.gprs[rt]);
1113 kvm_err("MTCz, cop0->reg[EBASE]: %#lx\n",
1114 kvm_read_c0_guest_ebase(cop0));
1115 } else if (rd == MIPS_CP0_TLB_HI && sel == 0) {
1116 uint32_t nasid =
1117 vcpu->arch.gprs[rt] & ASID_MASK;
1118 if ((KSEGX(vcpu->arch.gprs[rt]) != CKSEG0) &&
1119 ((kvm_read_c0_guest_entryhi(cop0) &
1120 ASID_MASK) != nasid)) {
1121 kvm_debug("MTCz, change ASID from %#lx to %#lx\n",
1122 kvm_read_c0_guest_entryhi(cop0)
1123 & ASID_MASK,
1124 vcpu->arch.gprs[rt]
1125 & ASID_MASK);
1126
1127 preempt_disable();
1128 /* Blow away the shadow host TLBs */
1129 kvm_mips_flush_host_tlb(1);
1130 cpu = smp_processor_id();
1131 for_each_possible_cpu(i)
1132 if (i != cpu) {
1133 vcpu->arch.guest_user_asid[i] = 0;
1134 vcpu->arch.guest_kernel_asid[i] = 0;
1135 }
1136 preempt_enable();
1137 }
1138 kvm_write_c0_guest_entryhi(cop0,
1139 vcpu->arch.gprs[rt]);
1140 }
1141 /* Are we writing to COUNT */
1142 else if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {
1143 kvm_mips_write_count(vcpu, vcpu->arch.gprs[rt]);
1144 goto done;
1145 } else if ((rd == MIPS_CP0_COMPARE) && (sel == 0)) {
1146 kvm_debug("[%#x] MTCz, COMPARE %#lx <- %#lx\n",
1147 pc, kvm_read_c0_guest_compare(cop0),
1148 vcpu->arch.gprs[rt]);
1149
1150 /* If we are writing to COMPARE */
1151 /* Clear pending timer interrupt, if any */
1152 kvm_mips_write_compare(vcpu,
1153 vcpu->arch.gprs[rt],
1154 true);
1155 } else if ((rd == MIPS_CP0_STATUS) && (sel == 0)) {
1156 unsigned int old_val, val, change;
1157
1158 old_val = kvm_read_c0_guest_status(cop0);
1159 val = vcpu->arch.gprs[rt];
1160 change = val ^ old_val;
1161
1162 /* Make sure that the NMI bit is never set */
1163 val &= ~ST0_NMI;
1164
1165 /*
1166 * Don't allow CU1 or FR to be set unless FPU
1167 * capability enabled and exists in guest
1168 * configuration.
1169 */
1170 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
1171 val &= ~(ST0_CU1 | ST0_FR);
1172
1173 /*
1174 * Also don't allow FR to be set if host doesn't
1175 * support it.
1176 */
1177 if (!(current_cpu_data.fpu_id & MIPS_FPIR_F64))
1178 val &= ~ST0_FR;
1179
1180
1181 /* Handle changes in FPU mode */
1182 preempt_disable();
1183
1184 /*
1185 * FPU and Vector register state is made
1186 * UNPREDICTABLE by a change of FR, so don't
1187 * even bother saving it.
1188 */
1189 if (change & ST0_FR)
1190 kvm_drop_fpu(vcpu);
1191
1192 /*
1193 * If MSA state is already live, it is undefined
1194 * how it interacts with FR=0 FPU state, and we
1195 * don't want to hit reserved instruction
1196 * exceptions trying to save the MSA state later
1197 * when CU=1 && FR=1, so play it safe and save
1198 * it first.
1199 */
1200 if (change & ST0_CU1 && !(val & ST0_FR) &&
1201 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA)
1202 kvm_lose_fpu(vcpu);
1203
1204 /*
1205 * Propagate CU1 (FPU enable) changes
1206 * immediately if the FPU context is already
1207 * loaded. When disabling we leave the context
1208 * loaded so it can be quickly enabled again in
1209 * the near future.
1210 */
1211 if (change & ST0_CU1 &&
1212 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
1213 change_c0_status(ST0_CU1, val);
1214
1215 preempt_enable();
1216
1217 kvm_write_c0_guest_status(cop0, val);
1218
1219 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1220 /*
1221 * If FPU present, we need CU1/FR bits to take
1222 * effect fairly soon.
1223 */
1224 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
1225 kvm_mips_trans_mtc0(inst, opc, vcpu);
1226 #endif
1227 } else if ((rd == MIPS_CP0_CONFIG) && (sel == 5)) {
1228 unsigned int old_val, val, change, wrmask;
1229
1230 old_val = kvm_read_c0_guest_config5(cop0);
1231 val = vcpu->arch.gprs[rt];
1232
1233 /* Only a few bits are writable in Config5 */
1234 wrmask = kvm_mips_config5_wrmask(vcpu);
1235 change = (val ^ old_val) & wrmask;
1236 val = old_val ^ change;
1237
1238
1239 /* Handle changes in FPU/MSA modes */
1240 preempt_disable();
1241
1242 /*
1243 * Propagate FRE changes immediately if the FPU
1244 * context is already loaded.
1245 */
1246 if (change & MIPS_CONF5_FRE &&
1247 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
1248 change_c0_config5(MIPS_CONF5_FRE, val);
1249
1250 /*
1251 * Propagate MSAEn changes immediately if the
1252 * MSA context is already loaded. When disabling
1253 * we leave the context loaded so it can be
1254 * quickly enabled again in the near future.
1255 */
1256 if (change & MIPS_CONF5_MSAEN &&
1257 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA)
1258 change_c0_config5(MIPS_CONF5_MSAEN,
1259 val);
1260
1261 preempt_enable();
1262
1263 kvm_write_c0_guest_config5(cop0, val);
1264 } else if ((rd == MIPS_CP0_CAUSE) && (sel == 0)) {
1265 uint32_t old_cause, new_cause;
1266
1267 old_cause = kvm_read_c0_guest_cause(cop0);
1268 new_cause = vcpu->arch.gprs[rt];
1269 /* Update R/W bits */
1270 kvm_change_c0_guest_cause(cop0, 0x08800300,
1271 new_cause);
1272 /* DC bit enabling/disabling timer? */
1273 if ((old_cause ^ new_cause) & CAUSEF_DC) {
1274 if (new_cause & CAUSEF_DC)
1275 kvm_mips_count_disable_cause(vcpu);
1276 else
1277 kvm_mips_count_enable_cause(vcpu);
1278 }
1279 } else {
1280 cop0->reg[rd][sel] = vcpu->arch.gprs[rt];
1281 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1282 kvm_mips_trans_mtc0(inst, opc, vcpu);
1283 #endif
1284 }
1285
1286 kvm_debug("[%#x] MTCz, cop0->reg[%d][%d]: %#lx\n", pc,
1287 rd, sel, cop0->reg[rd][sel]);
1288 break;
1289
1290 case dmtc_op:
1291 kvm_err("!!!!!!![%#lx]dmtc_op: rt: %d, rd: %d, sel: %d!!!!!!\n",
1292 vcpu->arch.pc, rt, rd, sel);
1293 er = EMULATE_FAIL;
1294 break;
1295
1296 case mfmcz_op:
1297 #ifdef KVM_MIPS_DEBUG_COP0_COUNTERS
1298 cop0->stat[MIPS_CP0_STATUS][0]++;
1299 #endif
1300 if (rt != 0) {
1301 vcpu->arch.gprs[rt] =
1302 kvm_read_c0_guest_status(cop0);
1303 }
1304 /* EI */
1305 if (inst & 0x20) {
1306 kvm_debug("[%#lx] mfmcz_op: EI\n",
1307 vcpu->arch.pc);
1308 kvm_set_c0_guest_status(cop0, ST0_IE);
1309 } else {
1310 kvm_debug("[%#lx] mfmcz_op: DI\n",
1311 vcpu->arch.pc);
1312 kvm_clear_c0_guest_status(cop0, ST0_IE);
1313 }
1314
1315 break;
1316
1317 case wrpgpr_op:
1318 {
1319 uint32_t css =
1320 cop0->reg[MIPS_CP0_STATUS][2] & 0xf;
1321 uint32_t pss =
1322 (cop0->reg[MIPS_CP0_STATUS][2] >> 6) & 0xf;
1323 /*
1324 * We don't support any shadow register sets, so
1325 * SRSCtl[PSS] == SRSCtl[CSS] = 0
1326 */
1327 if (css || pss) {
1328 er = EMULATE_FAIL;
1329 break;
1330 }
1331 kvm_debug("WRPGPR[%d][%d] = %#lx\n", pss, rd,
1332 vcpu->arch.gprs[rt]);
1333 vcpu->arch.gprs[rd] = vcpu->arch.gprs[rt];
1334 }
1335 break;
1336 default:
1337 kvm_err("[%#lx]MachEmulateCP0: unsupported COP0, copz: 0x%x\n",
1338 vcpu->arch.pc, copz);
1339 er = EMULATE_FAIL;
1340 break;
1341 }
1342 }
1343
1344 done:
1345 /* Rollback PC only if emulation was unsuccessful */
1346 if (er == EMULATE_FAIL)
1347 vcpu->arch.pc = curr_pc;
1348
1349 dont_update_pc:
1350 /*
1351 * This is for special instructions whose emulation
1352 * updates the PC, so do not overwrite the PC under
1353 * any circumstances
1354 */
1355
1356 return er;
1357 }
1358
kvm_mips_emulate_store(uint32_t inst,uint32_t cause,struct kvm_run * run,struct kvm_vcpu * vcpu)1359 enum emulation_result kvm_mips_emulate_store(uint32_t inst, uint32_t cause,
1360 struct kvm_run *run,
1361 struct kvm_vcpu *vcpu)
1362 {
1363 enum emulation_result er = EMULATE_DO_MMIO;
1364 int32_t op, base, rt, offset;
1365 uint32_t bytes;
1366 void *data = run->mmio.data;
1367 unsigned long curr_pc;
1368
1369 /*
1370 * Update PC and hold onto current PC in case there is
1371 * an error and we want to rollback the PC
1372 */
1373 curr_pc = vcpu->arch.pc;
1374 er = update_pc(vcpu, cause);
1375 if (er == EMULATE_FAIL)
1376 return er;
1377
1378 rt = (inst >> 16) & 0x1f;
1379 base = (inst >> 21) & 0x1f;
1380 offset = inst & 0xffff;
1381 op = (inst >> 26) & 0x3f;
1382
1383 switch (op) {
1384 case sb_op:
1385 bytes = 1;
1386 if (bytes > sizeof(run->mmio.data)) {
1387 kvm_err("%s: bad MMIO length: %d\n", __func__,
1388 run->mmio.len);
1389 }
1390 run->mmio.phys_addr =
1391 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1392 host_cp0_badvaddr);
1393 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1394 er = EMULATE_FAIL;
1395 break;
1396 }
1397 run->mmio.len = bytes;
1398 run->mmio.is_write = 1;
1399 vcpu->mmio_needed = 1;
1400 vcpu->mmio_is_write = 1;
1401 *(u8 *) data = vcpu->arch.gprs[rt];
1402 kvm_debug("OP_SB: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1403 vcpu->arch.host_cp0_badvaddr, vcpu->arch.gprs[rt],
1404 *(uint8_t *) data);
1405
1406 break;
1407
1408 case sw_op:
1409 bytes = 4;
1410 if (bytes > sizeof(run->mmio.data)) {
1411 kvm_err("%s: bad MMIO length: %d\n", __func__,
1412 run->mmio.len);
1413 }
1414 run->mmio.phys_addr =
1415 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1416 host_cp0_badvaddr);
1417 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1418 er = EMULATE_FAIL;
1419 break;
1420 }
1421
1422 run->mmio.len = bytes;
1423 run->mmio.is_write = 1;
1424 vcpu->mmio_needed = 1;
1425 vcpu->mmio_is_write = 1;
1426 *(uint32_t *) data = vcpu->arch.gprs[rt];
1427
1428 kvm_debug("[%#lx] OP_SW: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1429 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1430 vcpu->arch.gprs[rt], *(uint32_t *) data);
1431 break;
1432
1433 case sh_op:
1434 bytes = 2;
1435 if (bytes > sizeof(run->mmio.data)) {
1436 kvm_err("%s: bad MMIO length: %d\n", __func__,
1437 run->mmio.len);
1438 }
1439 run->mmio.phys_addr =
1440 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1441 host_cp0_badvaddr);
1442 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1443 er = EMULATE_FAIL;
1444 break;
1445 }
1446
1447 run->mmio.len = bytes;
1448 run->mmio.is_write = 1;
1449 vcpu->mmio_needed = 1;
1450 vcpu->mmio_is_write = 1;
1451 *(uint16_t *) data = vcpu->arch.gprs[rt];
1452
1453 kvm_debug("[%#lx] OP_SH: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1454 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1455 vcpu->arch.gprs[rt], *(uint32_t *) data);
1456 break;
1457
1458 default:
1459 kvm_err("Store not yet supported");
1460 er = EMULATE_FAIL;
1461 break;
1462 }
1463
1464 /* Rollback PC if emulation was unsuccessful */
1465 if (er == EMULATE_FAIL)
1466 vcpu->arch.pc = curr_pc;
1467
1468 return er;
1469 }
1470
kvm_mips_emulate_load(uint32_t inst,uint32_t cause,struct kvm_run * run,struct kvm_vcpu * vcpu)1471 enum emulation_result kvm_mips_emulate_load(uint32_t inst, uint32_t cause,
1472 struct kvm_run *run,
1473 struct kvm_vcpu *vcpu)
1474 {
1475 enum emulation_result er = EMULATE_DO_MMIO;
1476 unsigned long curr_pc;
1477 int32_t op, base, rt, offset;
1478 uint32_t bytes;
1479
1480 rt = (inst >> 16) & 0x1f;
1481 base = (inst >> 21) & 0x1f;
1482 offset = inst & 0xffff;
1483 op = (inst >> 26) & 0x3f;
1484
1485 /*
1486 * Find the resume PC now while we have safe and easy access to the
1487 * prior branch instruction, and save it for
1488 * kvm_mips_complete_mmio_load() to restore later.
1489 */
1490 curr_pc = vcpu->arch.pc;
1491 er = update_pc(vcpu, cause);
1492 if (er == EMULATE_FAIL)
1493 return er;
1494 vcpu->arch.io_pc = vcpu->arch.pc;
1495 vcpu->arch.pc = curr_pc;
1496
1497 vcpu->arch.io_gpr = rt;
1498
1499 switch (op) {
1500 case lw_op:
1501 bytes = 4;
1502 if (bytes > sizeof(run->mmio.data)) {
1503 kvm_err("%s: bad MMIO length: %d\n", __func__,
1504 run->mmio.len);
1505 er = EMULATE_FAIL;
1506 break;
1507 }
1508 run->mmio.phys_addr =
1509 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1510 host_cp0_badvaddr);
1511 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1512 er = EMULATE_FAIL;
1513 break;
1514 }
1515
1516 run->mmio.len = bytes;
1517 run->mmio.is_write = 0;
1518 vcpu->mmio_needed = 1;
1519 vcpu->mmio_is_write = 0;
1520 break;
1521
1522 case lh_op:
1523 case lhu_op:
1524 bytes = 2;
1525 if (bytes > sizeof(run->mmio.data)) {
1526 kvm_err("%s: bad MMIO length: %d\n", __func__,
1527 run->mmio.len);
1528 er = EMULATE_FAIL;
1529 break;
1530 }
1531 run->mmio.phys_addr =
1532 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1533 host_cp0_badvaddr);
1534 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1535 er = EMULATE_FAIL;
1536 break;
1537 }
1538
1539 run->mmio.len = bytes;
1540 run->mmio.is_write = 0;
1541 vcpu->mmio_needed = 1;
1542 vcpu->mmio_is_write = 0;
1543
1544 if (op == lh_op)
1545 vcpu->mmio_needed = 2;
1546 else
1547 vcpu->mmio_needed = 1;
1548
1549 break;
1550
1551 case lbu_op:
1552 case lb_op:
1553 bytes = 1;
1554 if (bytes > sizeof(run->mmio.data)) {
1555 kvm_err("%s: bad MMIO length: %d\n", __func__,
1556 run->mmio.len);
1557 er = EMULATE_FAIL;
1558 break;
1559 }
1560 run->mmio.phys_addr =
1561 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1562 host_cp0_badvaddr);
1563 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1564 er = EMULATE_FAIL;
1565 break;
1566 }
1567
1568 run->mmio.len = bytes;
1569 run->mmio.is_write = 0;
1570 vcpu->mmio_is_write = 0;
1571
1572 if (op == lb_op)
1573 vcpu->mmio_needed = 2;
1574 else
1575 vcpu->mmio_needed = 1;
1576
1577 break;
1578
1579 default:
1580 kvm_err("Load not yet supported");
1581 er = EMULATE_FAIL;
1582 break;
1583 }
1584
1585 return er;
1586 }
1587
kvm_mips_sync_icache(unsigned long va,struct kvm_vcpu * vcpu)1588 int kvm_mips_sync_icache(unsigned long va, struct kvm_vcpu *vcpu)
1589 {
1590 unsigned long offset = (va & ~PAGE_MASK);
1591 struct kvm *kvm = vcpu->kvm;
1592 unsigned long pa;
1593 gfn_t gfn;
1594 pfn_t pfn;
1595
1596 gfn = va >> PAGE_SHIFT;
1597
1598 if (gfn >= kvm->arch.guest_pmap_npages) {
1599 kvm_err("%s: Invalid gfn: %#llx\n", __func__, gfn);
1600 kvm_mips_dump_host_tlbs();
1601 kvm_arch_vcpu_dump_regs(vcpu);
1602 return -1;
1603 }
1604 pfn = kvm->arch.guest_pmap[gfn];
1605 pa = (pfn << PAGE_SHIFT) | offset;
1606
1607 kvm_debug("%s: va: %#lx, unmapped: %#x\n", __func__, va,
1608 CKSEG0ADDR(pa));
1609
1610 local_flush_icache_range(CKSEG0ADDR(pa), 32);
1611 return 0;
1612 }
1613
1614 #define MIPS_CACHE_OP_INDEX_INV 0x0
1615 #define MIPS_CACHE_OP_INDEX_LD_TAG 0x1
1616 #define MIPS_CACHE_OP_INDEX_ST_TAG 0x2
1617 #define MIPS_CACHE_OP_IMP 0x3
1618 #define MIPS_CACHE_OP_HIT_INV 0x4
1619 #define MIPS_CACHE_OP_FILL_WB_INV 0x5
1620 #define MIPS_CACHE_OP_HIT_HB 0x6
1621 #define MIPS_CACHE_OP_FETCH_LOCK 0x7
1622
1623 #define MIPS_CACHE_ICACHE 0x0
1624 #define MIPS_CACHE_DCACHE 0x1
1625 #define MIPS_CACHE_SEC 0x3
1626
kvm_mips_emulate_cache(uint32_t inst,uint32_t * opc,uint32_t cause,struct kvm_run * run,struct kvm_vcpu * vcpu)1627 enum emulation_result kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc,
1628 uint32_t cause,
1629 struct kvm_run *run,
1630 struct kvm_vcpu *vcpu)
1631 {
1632 struct mips_coproc *cop0 = vcpu->arch.cop0;
1633 enum emulation_result er = EMULATE_DONE;
1634 int32_t offset, cache, op_inst, op, base;
1635 struct kvm_vcpu_arch *arch = &vcpu->arch;
1636 unsigned long va;
1637 unsigned long curr_pc;
1638
1639 /*
1640 * Update PC and hold onto current PC in case there is
1641 * an error and we want to rollback the PC
1642 */
1643 curr_pc = vcpu->arch.pc;
1644 er = update_pc(vcpu, cause);
1645 if (er == EMULATE_FAIL)
1646 return er;
1647
1648 base = (inst >> 21) & 0x1f;
1649 op_inst = (inst >> 16) & 0x1f;
1650 offset = (int16_t)inst;
1651 cache = (inst >> 16) & 0x3;
1652 op = (inst >> 18) & 0x7;
1653
1654 va = arch->gprs[base] + offset;
1655
1656 kvm_debug("CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1657 cache, op, base, arch->gprs[base], offset);
1658
1659 /*
1660 * Treat INDEX_INV as a nop, basically issued by Linux on startup to
1661 * invalidate the caches entirely by stepping through all the
1662 * ways/indexes
1663 */
1664 if (op == MIPS_CACHE_OP_INDEX_INV) {
1665 kvm_debug("@ %#lx/%#lx CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1666 vcpu->arch.pc, vcpu->arch.gprs[31], cache, op, base,
1667 arch->gprs[base], offset);
1668
1669 if (cache == MIPS_CACHE_DCACHE)
1670 r4k_blast_dcache();
1671 else if (cache == MIPS_CACHE_ICACHE)
1672 r4k_blast_icache();
1673 else {
1674 kvm_err("%s: unsupported CACHE INDEX operation\n",
1675 __func__);
1676 return EMULATE_FAIL;
1677 }
1678
1679 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1680 kvm_mips_trans_cache_index(inst, opc, vcpu);
1681 #endif
1682 goto done;
1683 }
1684
1685 preempt_disable();
1686 if (KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG0) {
1687 if (kvm_mips_host_tlb_lookup(vcpu, va) < 0 &&
1688 kvm_mips_handle_kseg0_tlb_fault(va, vcpu)) {
1689 kvm_err("%s: handling mapped kseg0 tlb fault for %lx, vcpu: %p, ASID: %#lx\n",
1690 __func__, va, vcpu, read_c0_entryhi());
1691 er = EMULATE_FAIL;
1692 preempt_enable();
1693 goto done;
1694 }
1695 } else if ((KVM_GUEST_KSEGX(va) < KVM_GUEST_KSEG0) ||
1696 KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG23) {
1697 int index;
1698
1699 /* If an entry already exists then skip */
1700 if (kvm_mips_host_tlb_lookup(vcpu, va) >= 0)
1701 goto skip_fault;
1702
1703 /*
1704 * If address not in the guest TLB, then give the guest a fault,
1705 * the resulting handler will do the right thing
1706 */
1707 index = kvm_mips_guest_tlb_lookup(vcpu, (va & VPN2_MASK) |
1708 (kvm_read_c0_guest_entryhi
1709 (cop0) & ASID_MASK));
1710
1711 if (index < 0) {
1712 vcpu->arch.host_cp0_entryhi = (va & VPN2_MASK);
1713 vcpu->arch.host_cp0_badvaddr = va;
1714 er = kvm_mips_emulate_tlbmiss_ld(cause, NULL, run,
1715 vcpu);
1716 preempt_enable();
1717 goto dont_update_pc;
1718 } else {
1719 struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index];
1720 /*
1721 * Check if the entry is valid, if not then setup a TLB
1722 * invalid exception to the guest
1723 */
1724 if (!TLB_IS_VALID(*tlb, va)) {
1725 er = kvm_mips_emulate_tlbinv_ld(cause, NULL,
1726 run, vcpu);
1727 preempt_enable();
1728 goto dont_update_pc;
1729 }
1730 /*
1731 * We fault an entry from the guest tlb to the
1732 * shadow host TLB
1733 */
1734 if (kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb,
1735 NULL, NULL)) {
1736 kvm_err("%s: handling mapped seg tlb fault for %lx, index: %u, vcpu: %p, ASID: %#lx\n",
1737 __func__, va, index, vcpu,
1738 read_c0_entryhi());
1739 er = EMULATE_FAIL;
1740 preempt_enable();
1741 goto done;
1742 }
1743 }
1744 } else {
1745 kvm_err("INVALID CACHE INDEX/ADDRESS (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1746 cache, op, base, arch->gprs[base], offset);
1747 er = EMULATE_FAIL;
1748 preempt_enable();
1749 goto dont_update_pc;
1750
1751 }
1752
1753 skip_fault:
1754 /* XXXKYMA: Only a subset of cache ops are supported, used by Linux */
1755 if (cache == MIPS_CACHE_DCACHE
1756 && (op == MIPS_CACHE_OP_FILL_WB_INV
1757 || op == MIPS_CACHE_OP_HIT_INV)) {
1758 flush_dcache_line(va);
1759
1760 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1761 /*
1762 * Replace the CACHE instruction, with a SYNCI, not the same,
1763 * but avoids a trap
1764 */
1765 kvm_mips_trans_cache_va(inst, opc, vcpu);
1766 #endif
1767 } else if (op == MIPS_CACHE_OP_HIT_INV && cache == MIPS_CACHE_ICACHE) {
1768 flush_dcache_line(va);
1769 flush_icache_line(va);
1770
1771 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1772 /* Replace the CACHE instruction, with a SYNCI */
1773 kvm_mips_trans_cache_va(inst, opc, vcpu);
1774 #endif
1775 } else {
1776 kvm_err("NO-OP CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1777 cache, op, base, arch->gprs[base], offset);
1778 er = EMULATE_FAIL;
1779 preempt_enable();
1780 goto dont_update_pc;
1781 }
1782
1783 preempt_enable();
1784
1785 dont_update_pc:
1786 /* Rollback PC */
1787 vcpu->arch.pc = curr_pc;
1788 done:
1789 return er;
1790 }
1791
kvm_mips_emulate_inst(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)1792 enum emulation_result kvm_mips_emulate_inst(unsigned long cause, uint32_t *opc,
1793 struct kvm_run *run,
1794 struct kvm_vcpu *vcpu)
1795 {
1796 enum emulation_result er = EMULATE_DONE;
1797 uint32_t inst;
1798
1799 /* Fetch the instruction. */
1800 if (cause & CAUSEF_BD)
1801 opc += 1;
1802
1803 inst = kvm_get_inst(opc, vcpu);
1804
1805 switch (((union mips_instruction)inst).r_format.opcode) {
1806 case cop0_op:
1807 er = kvm_mips_emulate_CP0(inst, opc, cause, run, vcpu);
1808 break;
1809 case sb_op:
1810 case sh_op:
1811 case sw_op:
1812 er = kvm_mips_emulate_store(inst, cause, run, vcpu);
1813 break;
1814 case lb_op:
1815 case lbu_op:
1816 case lhu_op:
1817 case lh_op:
1818 case lw_op:
1819 er = kvm_mips_emulate_load(inst, cause, run, vcpu);
1820 break;
1821
1822 case cache_op:
1823 ++vcpu->stat.cache_exits;
1824 trace_kvm_exit(vcpu, CACHE_EXITS);
1825 er = kvm_mips_emulate_cache(inst, opc, cause, run, vcpu);
1826 break;
1827
1828 default:
1829 kvm_err("Instruction emulation not supported (%p/%#x)\n", opc,
1830 inst);
1831 kvm_arch_vcpu_dump_regs(vcpu);
1832 er = EMULATE_FAIL;
1833 break;
1834 }
1835
1836 return er;
1837 }
1838
kvm_mips_emulate_syscall(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)1839 enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
1840 uint32_t *opc,
1841 struct kvm_run *run,
1842 struct kvm_vcpu *vcpu)
1843 {
1844 struct mips_coproc *cop0 = vcpu->arch.cop0;
1845 struct kvm_vcpu_arch *arch = &vcpu->arch;
1846 enum emulation_result er = EMULATE_DONE;
1847
1848 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1849 /* save old pc */
1850 kvm_write_c0_guest_epc(cop0, arch->pc);
1851 kvm_set_c0_guest_status(cop0, ST0_EXL);
1852
1853 if (cause & CAUSEF_BD)
1854 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1855 else
1856 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1857
1858 kvm_debug("Delivering SYSCALL @ pc %#lx\n", arch->pc);
1859
1860 kvm_change_c0_guest_cause(cop0, (0xff),
1861 (T_SYSCALL << CAUSEB_EXCCODE));
1862
1863 /* Set PC to the exception entry point */
1864 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1865
1866 } else {
1867 kvm_err("Trying to deliver SYSCALL when EXL is already set\n");
1868 er = EMULATE_FAIL;
1869 }
1870
1871 return er;
1872 }
1873
kvm_mips_emulate_tlbmiss_ld(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)1874 enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
1875 uint32_t *opc,
1876 struct kvm_run *run,
1877 struct kvm_vcpu *vcpu)
1878 {
1879 struct mips_coproc *cop0 = vcpu->arch.cop0;
1880 struct kvm_vcpu_arch *arch = &vcpu->arch;
1881 unsigned long entryhi = (vcpu->arch. host_cp0_badvaddr & VPN2_MASK) |
1882 (kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
1883
1884 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1885 /* save old pc */
1886 kvm_write_c0_guest_epc(cop0, arch->pc);
1887 kvm_set_c0_guest_status(cop0, ST0_EXL);
1888
1889 if (cause & CAUSEF_BD)
1890 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1891 else
1892 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1893
1894 kvm_debug("[EXL == 0] delivering TLB MISS @ pc %#lx\n",
1895 arch->pc);
1896
1897 /* set pc to the exception entry point */
1898 arch->pc = KVM_GUEST_KSEG0 + 0x0;
1899
1900 } else {
1901 kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n",
1902 arch->pc);
1903
1904 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1905 }
1906
1907 kvm_change_c0_guest_cause(cop0, (0xff),
1908 (T_TLB_LD_MISS << CAUSEB_EXCCODE));
1909
1910 /* setup badvaddr, context and entryhi registers for the guest */
1911 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1912 /* XXXKYMA: is the context register used by linux??? */
1913 kvm_write_c0_guest_entryhi(cop0, entryhi);
1914 /* Blow away the shadow host TLBs */
1915 kvm_mips_flush_host_tlb(1);
1916
1917 return EMULATE_DONE;
1918 }
1919
kvm_mips_emulate_tlbinv_ld(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)1920 enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
1921 uint32_t *opc,
1922 struct kvm_run *run,
1923 struct kvm_vcpu *vcpu)
1924 {
1925 struct mips_coproc *cop0 = vcpu->arch.cop0;
1926 struct kvm_vcpu_arch *arch = &vcpu->arch;
1927 unsigned long entryhi =
1928 (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1929 (kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
1930
1931 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1932 /* save old pc */
1933 kvm_write_c0_guest_epc(cop0, arch->pc);
1934 kvm_set_c0_guest_status(cop0, ST0_EXL);
1935
1936 if (cause & CAUSEF_BD)
1937 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1938 else
1939 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1940
1941 kvm_debug("[EXL == 0] delivering TLB INV @ pc %#lx\n",
1942 arch->pc);
1943
1944 /* set pc to the exception entry point */
1945 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1946
1947 } else {
1948 kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n",
1949 arch->pc);
1950 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1951 }
1952
1953 kvm_change_c0_guest_cause(cop0, (0xff),
1954 (T_TLB_LD_MISS << CAUSEB_EXCCODE));
1955
1956 /* setup badvaddr, context and entryhi registers for the guest */
1957 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1958 /* XXXKYMA: is the context register used by linux??? */
1959 kvm_write_c0_guest_entryhi(cop0, entryhi);
1960 /* Blow away the shadow host TLBs */
1961 kvm_mips_flush_host_tlb(1);
1962
1963 return EMULATE_DONE;
1964 }
1965
kvm_mips_emulate_tlbmiss_st(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)1966 enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
1967 uint32_t *opc,
1968 struct kvm_run *run,
1969 struct kvm_vcpu *vcpu)
1970 {
1971 struct mips_coproc *cop0 = vcpu->arch.cop0;
1972 struct kvm_vcpu_arch *arch = &vcpu->arch;
1973 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1974 (kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
1975
1976 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1977 /* save old pc */
1978 kvm_write_c0_guest_epc(cop0, arch->pc);
1979 kvm_set_c0_guest_status(cop0, ST0_EXL);
1980
1981 if (cause & CAUSEF_BD)
1982 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1983 else
1984 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1985
1986 kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n",
1987 arch->pc);
1988
1989 /* Set PC to the exception entry point */
1990 arch->pc = KVM_GUEST_KSEG0 + 0x0;
1991 } else {
1992 kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n",
1993 arch->pc);
1994 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1995 }
1996
1997 kvm_change_c0_guest_cause(cop0, (0xff),
1998 (T_TLB_ST_MISS << CAUSEB_EXCCODE));
1999
2000 /* setup badvaddr, context and entryhi registers for the guest */
2001 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2002 /* XXXKYMA: is the context register used by linux??? */
2003 kvm_write_c0_guest_entryhi(cop0, entryhi);
2004 /* Blow away the shadow host TLBs */
2005 kvm_mips_flush_host_tlb(1);
2006
2007 return EMULATE_DONE;
2008 }
2009
kvm_mips_emulate_tlbinv_st(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)2010 enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
2011 uint32_t *opc,
2012 struct kvm_run *run,
2013 struct kvm_vcpu *vcpu)
2014 {
2015 struct mips_coproc *cop0 = vcpu->arch.cop0;
2016 struct kvm_vcpu_arch *arch = &vcpu->arch;
2017 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
2018 (kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
2019
2020 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2021 /* save old pc */
2022 kvm_write_c0_guest_epc(cop0, arch->pc);
2023 kvm_set_c0_guest_status(cop0, ST0_EXL);
2024
2025 if (cause & CAUSEF_BD)
2026 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2027 else
2028 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2029
2030 kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n",
2031 arch->pc);
2032
2033 /* Set PC to the exception entry point */
2034 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2035 } else {
2036 kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n",
2037 arch->pc);
2038 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2039 }
2040
2041 kvm_change_c0_guest_cause(cop0, (0xff),
2042 (T_TLB_ST_MISS << CAUSEB_EXCCODE));
2043
2044 /* setup badvaddr, context and entryhi registers for the guest */
2045 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2046 /* XXXKYMA: is the context register used by linux??? */
2047 kvm_write_c0_guest_entryhi(cop0, entryhi);
2048 /* Blow away the shadow host TLBs */
2049 kvm_mips_flush_host_tlb(1);
2050
2051 return EMULATE_DONE;
2052 }
2053
2054 /* TLBMOD: store into address matching TLB with Dirty bit off */
kvm_mips_handle_tlbmod(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)2055 enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause, uint32_t *opc,
2056 struct kvm_run *run,
2057 struct kvm_vcpu *vcpu)
2058 {
2059 enum emulation_result er = EMULATE_DONE;
2060 #ifdef DEBUG
2061 struct mips_coproc *cop0 = vcpu->arch.cop0;
2062 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
2063 (kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
2064 int index;
2065
2066 /* If address not in the guest TLB, then we are in trouble */
2067 index = kvm_mips_guest_tlb_lookup(vcpu, entryhi);
2068 if (index < 0) {
2069 /* XXXKYMA Invalidate and retry */
2070 kvm_mips_host_tlb_inv(vcpu, vcpu->arch.host_cp0_badvaddr);
2071 kvm_err("%s: host got TLBMOD for %#lx but entry not present in Guest TLB\n",
2072 __func__, entryhi);
2073 kvm_mips_dump_guest_tlbs(vcpu);
2074 kvm_mips_dump_host_tlbs();
2075 return EMULATE_FAIL;
2076 }
2077 #endif
2078
2079 er = kvm_mips_emulate_tlbmod(cause, opc, run, vcpu);
2080 return er;
2081 }
2082
kvm_mips_emulate_tlbmod(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)2083 enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
2084 uint32_t *opc,
2085 struct kvm_run *run,
2086 struct kvm_vcpu *vcpu)
2087 {
2088 struct mips_coproc *cop0 = vcpu->arch.cop0;
2089 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
2090 (kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
2091 struct kvm_vcpu_arch *arch = &vcpu->arch;
2092
2093 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2094 /* save old pc */
2095 kvm_write_c0_guest_epc(cop0, arch->pc);
2096 kvm_set_c0_guest_status(cop0, ST0_EXL);
2097
2098 if (cause & CAUSEF_BD)
2099 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2100 else
2101 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2102
2103 kvm_debug("[EXL == 0] Delivering TLB MOD @ pc %#lx\n",
2104 arch->pc);
2105
2106 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2107 } else {
2108 kvm_debug("[EXL == 1] Delivering TLB MOD @ pc %#lx\n",
2109 arch->pc);
2110 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2111 }
2112
2113 kvm_change_c0_guest_cause(cop0, (0xff), (T_TLB_MOD << CAUSEB_EXCCODE));
2114
2115 /* setup badvaddr, context and entryhi registers for the guest */
2116 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2117 /* XXXKYMA: is the context register used by linux??? */
2118 kvm_write_c0_guest_entryhi(cop0, entryhi);
2119 /* Blow away the shadow host TLBs */
2120 kvm_mips_flush_host_tlb(1);
2121
2122 return EMULATE_DONE;
2123 }
2124
kvm_mips_emulate_fpu_exc(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)2125 enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
2126 uint32_t *opc,
2127 struct kvm_run *run,
2128 struct kvm_vcpu *vcpu)
2129 {
2130 struct mips_coproc *cop0 = vcpu->arch.cop0;
2131 struct kvm_vcpu_arch *arch = &vcpu->arch;
2132
2133 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2134 /* save old pc */
2135 kvm_write_c0_guest_epc(cop0, arch->pc);
2136 kvm_set_c0_guest_status(cop0, ST0_EXL);
2137
2138 if (cause & CAUSEF_BD)
2139 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2140 else
2141 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2142
2143 }
2144
2145 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2146
2147 kvm_change_c0_guest_cause(cop0, (0xff),
2148 (T_COP_UNUSABLE << CAUSEB_EXCCODE));
2149 kvm_change_c0_guest_cause(cop0, (CAUSEF_CE), (0x1 << CAUSEB_CE));
2150
2151 return EMULATE_DONE;
2152 }
2153
kvm_mips_emulate_ri_exc(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)2154 enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
2155 uint32_t *opc,
2156 struct kvm_run *run,
2157 struct kvm_vcpu *vcpu)
2158 {
2159 struct mips_coproc *cop0 = vcpu->arch.cop0;
2160 struct kvm_vcpu_arch *arch = &vcpu->arch;
2161 enum emulation_result er = EMULATE_DONE;
2162
2163 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2164 /* save old pc */
2165 kvm_write_c0_guest_epc(cop0, arch->pc);
2166 kvm_set_c0_guest_status(cop0, ST0_EXL);
2167
2168 if (cause & CAUSEF_BD)
2169 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2170 else
2171 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2172
2173 kvm_debug("Delivering RI @ pc %#lx\n", arch->pc);
2174
2175 kvm_change_c0_guest_cause(cop0, (0xff),
2176 (T_RES_INST << CAUSEB_EXCCODE));
2177
2178 /* Set PC to the exception entry point */
2179 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2180
2181 } else {
2182 kvm_err("Trying to deliver RI when EXL is already set\n");
2183 er = EMULATE_FAIL;
2184 }
2185
2186 return er;
2187 }
2188
kvm_mips_emulate_bp_exc(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)2189 enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
2190 uint32_t *opc,
2191 struct kvm_run *run,
2192 struct kvm_vcpu *vcpu)
2193 {
2194 struct mips_coproc *cop0 = vcpu->arch.cop0;
2195 struct kvm_vcpu_arch *arch = &vcpu->arch;
2196 enum emulation_result er = EMULATE_DONE;
2197
2198 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2199 /* save old pc */
2200 kvm_write_c0_guest_epc(cop0, arch->pc);
2201 kvm_set_c0_guest_status(cop0, ST0_EXL);
2202
2203 if (cause & CAUSEF_BD)
2204 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2205 else
2206 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2207
2208 kvm_debug("Delivering BP @ pc %#lx\n", arch->pc);
2209
2210 kvm_change_c0_guest_cause(cop0, (0xff),
2211 (T_BREAK << CAUSEB_EXCCODE));
2212
2213 /* Set PC to the exception entry point */
2214 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2215
2216 } else {
2217 kvm_err("Trying to deliver BP when EXL is already set\n");
2218 er = EMULATE_FAIL;
2219 }
2220
2221 return er;
2222 }
2223
kvm_mips_emulate_trap_exc(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)2224 enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause,
2225 uint32_t *opc,
2226 struct kvm_run *run,
2227 struct kvm_vcpu *vcpu)
2228 {
2229 struct mips_coproc *cop0 = vcpu->arch.cop0;
2230 struct kvm_vcpu_arch *arch = &vcpu->arch;
2231 enum emulation_result er = EMULATE_DONE;
2232
2233 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2234 /* save old pc */
2235 kvm_write_c0_guest_epc(cop0, arch->pc);
2236 kvm_set_c0_guest_status(cop0, ST0_EXL);
2237
2238 if (cause & CAUSEF_BD)
2239 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2240 else
2241 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2242
2243 kvm_debug("Delivering TRAP @ pc %#lx\n", arch->pc);
2244
2245 kvm_change_c0_guest_cause(cop0, (0xff),
2246 (T_TRAP << CAUSEB_EXCCODE));
2247
2248 /* Set PC to the exception entry point */
2249 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2250
2251 } else {
2252 kvm_err("Trying to deliver TRAP when EXL is already set\n");
2253 er = EMULATE_FAIL;
2254 }
2255
2256 return er;
2257 }
2258
kvm_mips_emulate_msafpe_exc(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)2259 enum emulation_result kvm_mips_emulate_msafpe_exc(unsigned long cause,
2260 uint32_t *opc,
2261 struct kvm_run *run,
2262 struct kvm_vcpu *vcpu)
2263 {
2264 struct mips_coproc *cop0 = vcpu->arch.cop0;
2265 struct kvm_vcpu_arch *arch = &vcpu->arch;
2266 enum emulation_result er = EMULATE_DONE;
2267
2268 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2269 /* save old pc */
2270 kvm_write_c0_guest_epc(cop0, arch->pc);
2271 kvm_set_c0_guest_status(cop0, ST0_EXL);
2272
2273 if (cause & CAUSEF_BD)
2274 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2275 else
2276 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2277
2278 kvm_debug("Delivering MSAFPE @ pc %#lx\n", arch->pc);
2279
2280 kvm_change_c0_guest_cause(cop0, (0xff),
2281 (T_MSAFPE << CAUSEB_EXCCODE));
2282
2283 /* Set PC to the exception entry point */
2284 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2285
2286 } else {
2287 kvm_err("Trying to deliver MSAFPE when EXL is already set\n");
2288 er = EMULATE_FAIL;
2289 }
2290
2291 return er;
2292 }
2293
kvm_mips_emulate_fpe_exc(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)2294 enum emulation_result kvm_mips_emulate_fpe_exc(unsigned long cause,
2295 uint32_t *opc,
2296 struct kvm_run *run,
2297 struct kvm_vcpu *vcpu)
2298 {
2299 struct mips_coproc *cop0 = vcpu->arch.cop0;
2300 struct kvm_vcpu_arch *arch = &vcpu->arch;
2301 enum emulation_result er = EMULATE_DONE;
2302
2303 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2304 /* save old pc */
2305 kvm_write_c0_guest_epc(cop0, arch->pc);
2306 kvm_set_c0_guest_status(cop0, ST0_EXL);
2307
2308 if (cause & CAUSEF_BD)
2309 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2310 else
2311 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2312
2313 kvm_debug("Delivering FPE @ pc %#lx\n", arch->pc);
2314
2315 kvm_change_c0_guest_cause(cop0, (0xff),
2316 (T_FPE << CAUSEB_EXCCODE));
2317
2318 /* Set PC to the exception entry point */
2319 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2320
2321 } else {
2322 kvm_err("Trying to deliver FPE when EXL is already set\n");
2323 er = EMULATE_FAIL;
2324 }
2325
2326 return er;
2327 }
2328
kvm_mips_emulate_msadis_exc(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)2329 enum emulation_result kvm_mips_emulate_msadis_exc(unsigned long cause,
2330 uint32_t *opc,
2331 struct kvm_run *run,
2332 struct kvm_vcpu *vcpu)
2333 {
2334 struct mips_coproc *cop0 = vcpu->arch.cop0;
2335 struct kvm_vcpu_arch *arch = &vcpu->arch;
2336 enum emulation_result er = EMULATE_DONE;
2337
2338 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2339 /* save old pc */
2340 kvm_write_c0_guest_epc(cop0, arch->pc);
2341 kvm_set_c0_guest_status(cop0, ST0_EXL);
2342
2343 if (cause & CAUSEF_BD)
2344 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2345 else
2346 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2347
2348 kvm_debug("Delivering MSADIS @ pc %#lx\n", arch->pc);
2349
2350 kvm_change_c0_guest_cause(cop0, (0xff),
2351 (T_MSADIS << CAUSEB_EXCCODE));
2352
2353 /* Set PC to the exception entry point */
2354 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2355
2356 } else {
2357 kvm_err("Trying to deliver MSADIS when EXL is already set\n");
2358 er = EMULATE_FAIL;
2359 }
2360
2361 return er;
2362 }
2363
2364 /* ll/sc, rdhwr, sync emulation */
2365
2366 #define OPCODE 0xfc000000
2367 #define BASE 0x03e00000
2368 #define RT 0x001f0000
2369 #define OFFSET 0x0000ffff
2370 #define LL 0xc0000000
2371 #define SC 0xe0000000
2372 #define SPEC0 0x00000000
2373 #define SPEC3 0x7c000000
2374 #define RD 0x0000f800
2375 #define FUNC 0x0000003f
2376 #define SYNC 0x0000000f
2377 #define RDHWR 0x0000003b
2378
kvm_mips_handle_ri(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)2379 enum emulation_result kvm_mips_handle_ri(unsigned long cause, uint32_t *opc,
2380 struct kvm_run *run,
2381 struct kvm_vcpu *vcpu)
2382 {
2383 struct mips_coproc *cop0 = vcpu->arch.cop0;
2384 struct kvm_vcpu_arch *arch = &vcpu->arch;
2385 enum emulation_result er = EMULATE_DONE;
2386 unsigned long curr_pc;
2387 uint32_t inst;
2388
2389 /*
2390 * Update PC and hold onto current PC in case there is
2391 * an error and we want to rollback the PC
2392 */
2393 curr_pc = vcpu->arch.pc;
2394 er = update_pc(vcpu, cause);
2395 if (er == EMULATE_FAIL)
2396 return er;
2397
2398 /* Fetch the instruction. */
2399 if (cause & CAUSEF_BD)
2400 opc += 1;
2401
2402 inst = kvm_get_inst(opc, vcpu);
2403
2404 if (inst == KVM_INVALID_INST) {
2405 kvm_err("%s: Cannot get inst @ %p\n", __func__, opc);
2406 return EMULATE_FAIL;
2407 }
2408
2409 if ((inst & OPCODE) == SPEC3 && (inst & FUNC) == RDHWR) {
2410 int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
2411 int rd = (inst & RD) >> 11;
2412 int rt = (inst & RT) >> 16;
2413 /* If usermode, check RDHWR rd is allowed by guest HWREna */
2414 if (usermode && !(kvm_read_c0_guest_hwrena(cop0) & BIT(rd))) {
2415 kvm_debug("RDHWR %#x disallowed by HWREna @ %p\n",
2416 rd, opc);
2417 goto emulate_ri;
2418 }
2419 switch (rd) {
2420 case 0: /* CPU number */
2421 arch->gprs[rt] = 0;
2422 break;
2423 case 1: /* SYNCI length */
2424 arch->gprs[rt] = min(current_cpu_data.dcache.linesz,
2425 current_cpu_data.icache.linesz);
2426 break;
2427 case 2: /* Read count register */
2428 arch->gprs[rt] = kvm_mips_read_count(vcpu);
2429 break;
2430 case 3: /* Count register resolution */
2431 switch (current_cpu_data.cputype) {
2432 case CPU_20KC:
2433 case CPU_25KF:
2434 arch->gprs[rt] = 1;
2435 break;
2436 default:
2437 arch->gprs[rt] = 2;
2438 }
2439 break;
2440 case 29:
2441 arch->gprs[rt] = kvm_read_c0_guest_userlocal(cop0);
2442 break;
2443
2444 default:
2445 kvm_debug("RDHWR %#x not supported @ %p\n", rd, opc);
2446 goto emulate_ri;
2447 }
2448 } else {
2449 kvm_debug("Emulate RI not supported @ %p: %#x\n", opc, inst);
2450 goto emulate_ri;
2451 }
2452
2453 return EMULATE_DONE;
2454
2455 emulate_ri:
2456 /*
2457 * Rollback PC (if in branch delay slot then the PC already points to
2458 * branch target), and pass the RI exception to the guest OS.
2459 */
2460 vcpu->arch.pc = curr_pc;
2461 return kvm_mips_emulate_ri_exc(cause, opc, run, vcpu);
2462 }
2463
kvm_mips_complete_mmio_load(struct kvm_vcpu * vcpu,struct kvm_run * run)2464 enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
2465 struct kvm_run *run)
2466 {
2467 unsigned long *gpr = &vcpu->arch.gprs[vcpu->arch.io_gpr];
2468 enum emulation_result er = EMULATE_DONE;
2469
2470 if (run->mmio.len > sizeof(*gpr)) {
2471 kvm_err("Bad MMIO length: %d", run->mmio.len);
2472 er = EMULATE_FAIL;
2473 goto done;
2474 }
2475
2476 /* Restore saved resume PC */
2477 vcpu->arch.pc = vcpu->arch.io_pc;
2478
2479 switch (run->mmio.len) {
2480 case 4:
2481 *gpr = *(int32_t *) run->mmio.data;
2482 break;
2483
2484 case 2:
2485 if (vcpu->mmio_needed == 2)
2486 *gpr = *(int16_t *) run->mmio.data;
2487 else
2488 *gpr = *(uint16_t *)run->mmio.data;
2489
2490 break;
2491 case 1:
2492 if (vcpu->mmio_needed == 2)
2493 *gpr = *(int8_t *) run->mmio.data;
2494 else
2495 *gpr = *(u8 *) run->mmio.data;
2496 break;
2497 }
2498
2499 done:
2500 return er;
2501 }
2502
kvm_mips_emulate_exc(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)2503 static enum emulation_result kvm_mips_emulate_exc(unsigned long cause,
2504 uint32_t *opc,
2505 struct kvm_run *run,
2506 struct kvm_vcpu *vcpu)
2507 {
2508 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
2509 struct mips_coproc *cop0 = vcpu->arch.cop0;
2510 struct kvm_vcpu_arch *arch = &vcpu->arch;
2511 enum emulation_result er = EMULATE_DONE;
2512
2513 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2514 /* save old pc */
2515 kvm_write_c0_guest_epc(cop0, arch->pc);
2516 kvm_set_c0_guest_status(cop0, ST0_EXL);
2517
2518 if (cause & CAUSEF_BD)
2519 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2520 else
2521 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2522
2523 kvm_change_c0_guest_cause(cop0, (0xff),
2524 (exccode << CAUSEB_EXCCODE));
2525
2526 /* Set PC to the exception entry point */
2527 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2528 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2529
2530 kvm_debug("Delivering EXC %d @ pc %#lx, badVaddr: %#lx\n",
2531 exccode, kvm_read_c0_guest_epc(cop0),
2532 kvm_read_c0_guest_badvaddr(cop0));
2533 } else {
2534 kvm_err("Trying to deliver EXC when EXL is already set\n");
2535 er = EMULATE_FAIL;
2536 }
2537
2538 return er;
2539 }
2540
kvm_mips_check_privilege(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)2541 enum emulation_result kvm_mips_check_privilege(unsigned long cause,
2542 uint32_t *opc,
2543 struct kvm_run *run,
2544 struct kvm_vcpu *vcpu)
2545 {
2546 enum emulation_result er = EMULATE_DONE;
2547 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
2548 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
2549
2550 int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
2551
2552 if (usermode) {
2553 switch (exccode) {
2554 case T_INT:
2555 case T_SYSCALL:
2556 case T_BREAK:
2557 case T_RES_INST:
2558 case T_TRAP:
2559 case T_MSAFPE:
2560 case T_FPE:
2561 case T_MSADIS:
2562 break;
2563
2564 case T_COP_UNUSABLE:
2565 if (((cause & CAUSEF_CE) >> CAUSEB_CE) == 0)
2566 er = EMULATE_PRIV_FAIL;
2567 break;
2568
2569 case T_TLB_MOD:
2570 break;
2571
2572 case T_TLB_LD_MISS:
2573 /*
2574 * We we are accessing Guest kernel space, then send an
2575 * address error exception to the guest
2576 */
2577 if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) {
2578 kvm_debug("%s: LD MISS @ %#lx\n", __func__,
2579 badvaddr);
2580 cause &= ~0xff;
2581 cause |= (T_ADDR_ERR_LD << CAUSEB_EXCCODE);
2582 er = EMULATE_PRIV_FAIL;
2583 }
2584 break;
2585
2586 case T_TLB_ST_MISS:
2587 /*
2588 * We we are accessing Guest kernel space, then send an
2589 * address error exception to the guest
2590 */
2591 if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) {
2592 kvm_debug("%s: ST MISS @ %#lx\n", __func__,
2593 badvaddr);
2594 cause &= ~0xff;
2595 cause |= (T_ADDR_ERR_ST << CAUSEB_EXCCODE);
2596 er = EMULATE_PRIV_FAIL;
2597 }
2598 break;
2599
2600 case T_ADDR_ERR_ST:
2601 kvm_debug("%s: address error ST @ %#lx\n", __func__,
2602 badvaddr);
2603 if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) {
2604 cause &= ~0xff;
2605 cause |= (T_TLB_ST_MISS << CAUSEB_EXCCODE);
2606 }
2607 er = EMULATE_PRIV_FAIL;
2608 break;
2609 case T_ADDR_ERR_LD:
2610 kvm_debug("%s: address error LD @ %#lx\n", __func__,
2611 badvaddr);
2612 if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) {
2613 cause &= ~0xff;
2614 cause |= (T_TLB_LD_MISS << CAUSEB_EXCCODE);
2615 }
2616 er = EMULATE_PRIV_FAIL;
2617 break;
2618 default:
2619 er = EMULATE_PRIV_FAIL;
2620 break;
2621 }
2622 }
2623
2624 if (er == EMULATE_PRIV_FAIL)
2625 kvm_mips_emulate_exc(cause, opc, run, vcpu);
2626
2627 return er;
2628 }
2629
2630 /*
2631 * User Address (UA) fault, this could happen if
2632 * (1) TLB entry not present/valid in both Guest and shadow host TLBs, in this
2633 * case we pass on the fault to the guest kernel and let it handle it.
2634 * (2) TLB entry is present in the Guest TLB but not in the shadow, in this
2635 * case we inject the TLB from the Guest TLB into the shadow host TLB
2636 */
kvm_mips_handle_tlbmiss(unsigned long cause,uint32_t * opc,struct kvm_run * run,struct kvm_vcpu * vcpu)2637 enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
2638 uint32_t *opc,
2639 struct kvm_run *run,
2640 struct kvm_vcpu *vcpu)
2641 {
2642 enum emulation_result er = EMULATE_DONE;
2643 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
2644 unsigned long va = vcpu->arch.host_cp0_badvaddr;
2645 int index;
2646
2647 kvm_debug("kvm_mips_handle_tlbmiss: badvaddr: %#lx, entryhi: %#lx\n",
2648 vcpu->arch.host_cp0_badvaddr, vcpu->arch.host_cp0_entryhi);
2649
2650 /*
2651 * KVM would not have got the exception if this entry was valid in the
2652 * shadow host TLB. Check the Guest TLB, if the entry is not there then
2653 * send the guest an exception. The guest exc handler should then inject
2654 * an entry into the guest TLB.
2655 */
2656 index = kvm_mips_guest_tlb_lookup(vcpu,
2657 (va & VPN2_MASK) |
2658 (kvm_read_c0_guest_entryhi
2659 (vcpu->arch.cop0) & ASID_MASK));
2660 if (index < 0) {
2661 if (exccode == T_TLB_LD_MISS) {
2662 er = kvm_mips_emulate_tlbmiss_ld(cause, opc, run, vcpu);
2663 } else if (exccode == T_TLB_ST_MISS) {
2664 er = kvm_mips_emulate_tlbmiss_st(cause, opc, run, vcpu);
2665 } else {
2666 kvm_err("%s: invalid exc code: %d\n", __func__,
2667 exccode);
2668 er = EMULATE_FAIL;
2669 }
2670 } else {
2671 struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index];
2672
2673 /*
2674 * Check if the entry is valid, if not then setup a TLB invalid
2675 * exception to the guest
2676 */
2677 if (!TLB_IS_VALID(*tlb, va)) {
2678 if (exccode == T_TLB_LD_MISS) {
2679 er = kvm_mips_emulate_tlbinv_ld(cause, opc, run,
2680 vcpu);
2681 } else if (exccode == T_TLB_ST_MISS) {
2682 er = kvm_mips_emulate_tlbinv_st(cause, opc, run,
2683 vcpu);
2684 } else {
2685 kvm_err("%s: invalid exc code: %d\n", __func__,
2686 exccode);
2687 er = EMULATE_FAIL;
2688 }
2689 } else {
2690 kvm_debug("Injecting hi: %#lx, lo0: %#lx, lo1: %#lx into shadow host TLB\n",
2691 tlb->tlb_hi, tlb->tlb_lo0, tlb->tlb_lo1);
2692 /*
2693 * OK we have a Guest TLB entry, now inject it into the
2694 * shadow host TLB
2695 */
2696 if (kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb,
2697 NULL, NULL)) {
2698 kvm_err("%s: handling mapped seg tlb fault for %lx, index: %u, vcpu: %p, ASID: %#lx\n",
2699 __func__, va, index, vcpu,
2700 read_c0_entryhi());
2701 er = EMULATE_FAIL;
2702 }
2703 }
2704 }
2705
2706 return er;
2707 }
2708