1 /* 2 * Format of an instruction in memory. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 2000 by Ralf Baechle 9 * Copyright (C) 2006 by Thiemo Seufer 10 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 11 * Copyright (C) 2014 Imagination Technologies Ltd. 12 */ 13 #ifndef _UAPI_ASM_INST_H 14 #define _UAPI_ASM_INST_H 15 16 #include <asm/bitfield.h> 17 18 /* 19 * Major opcodes; before MIPS IV cop1x was called cop3. 20 */ 21 enum major_op { 22 spec_op, bcond_op, j_op, jal_op, 23 beq_op, bne_op, blez_op, bgtz_op, 24 addi_op, pop10_op = addi_op, addiu_op, slti_op, sltiu_op, 25 andi_op, ori_op, xori_op, lui_op, 26 cop0_op, cop1_op, cop2_op, cop1x_op, 27 beql_op, bnel_op, blezl_op, bgtzl_op, 28 daddi_op, pop30_op = daddi_op, daddiu_op, ldl_op, ldr_op, 29 spec2_op, jalx_op, mdmx_op, msa_op = mdmx_op, spec3_op, 30 lb_op, lh_op, lwl_op, lw_op, 31 lbu_op, lhu_op, lwr_op, lwu_op, 32 sb_op, sh_op, swl_op, sw_op, 33 sdl_op, sdr_op, swr_op, cache_op, 34 ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op, 35 lld_op, ldc1_op, ldc2_op, pop66_op = ldc2_op, ld_op, 36 sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op, 37 scd_op, sdc1_op, sdc2_op, pop76_op = sdc2_op, sd_op 38 }; 39 40 /* 41 * func field of spec opcode. 42 */ 43 enum spec_op { 44 sll_op, movc_op, srl_op, sra_op, 45 sllv_op, pmon_op, srlv_op, srav_op, 46 jr_op, jalr_op, movz_op, movn_op, 47 syscall_op, break_op, spim_op, sync_op, 48 mfhi_op, mthi_op, mflo_op, mtlo_op, 49 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op, 50 mult_op, multu_op, div_op, divu_op, 51 dmult_op, dmultu_op, ddiv_op, ddivu_op, 52 add_op, addu_op, sub_op, subu_op, 53 and_op, or_op, xor_op, nor_op, 54 spec3_unused_op, spec4_unused_op, slt_op, sltu_op, 55 dadd_op, daddu_op, dsub_op, dsubu_op, 56 tge_op, tgeu_op, tlt_op, tltu_op, 57 teq_op, spec5_unused_op, tne_op, spec6_unused_op, 58 dsll_op, spec7_unused_op, dsrl_op, dsra_op, 59 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op 60 }; 61 62 /* 63 * func field of spec2 opcode. 64 */ 65 enum spec2_op { 66 madd_op, maddu_op, mul_op, spec2_3_unused_op, 67 msub_op, msubu_op, /* more unused ops */ 68 clz_op = 0x20, clo_op, 69 dclz_op = 0x24, dclo_op, 70 sdbpp_op = 0x3f 71 }; 72 73 /* 74 * func field of spec3 opcode. 75 */ 76 enum spec3_op { 77 ext_op, dextm_op, dextu_op, dext_op, 78 ins_op, dinsm_op, dinsu_op, dins_op, 79 yield_op = 0x09, lx_op = 0x0a, 80 lwle_op = 0x19, lwre_op = 0x1a, 81 cachee_op = 0x1b, sbe_op = 0x1c, 82 she_op = 0x1d, sce_op = 0x1e, 83 swe_op = 0x1f, bshfl_op = 0x20, 84 swle_op = 0x21, swre_op = 0x22, 85 prefe_op = 0x23, dbshfl_op = 0x24, 86 cache6_op = 0x25, sc6_op = 0x26, 87 scd6_op = 0x27, lbue_op = 0x28, 88 lhue_op = 0x29, lbe_op = 0x2c, 89 lhe_op = 0x2d, lle_op = 0x2e, 90 lwe_op = 0x2f, pref6_op = 0x35, 91 ll6_op = 0x36, lld6_op = 0x37, 92 rdhwr_op = 0x3b 93 }; 94 95 /* 96 * rt field of bcond opcodes. 97 */ 98 enum rt_op { 99 bltz_op, bgez_op, bltzl_op, bgezl_op, 100 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, 101 tgei_op, tgeiu_op, tlti_op, tltiu_op, 102 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, 103 bltzal_op, bgezal_op, bltzall_op, bgezall_op, 104 rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17, 105 rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b, 106 bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f 107 }; 108 109 /* 110 * rs field of cop opcodes. 111 */ 112 enum cop_op { 113 mfc_op = 0x00, dmfc_op = 0x01, 114 cfc_op = 0x02, mfhc0_op = 0x02, 115 mfhc_op = 0x03, mtc_op = 0x04, 116 dmtc_op = 0x05, ctc_op = 0x06, 117 mthc0_op = 0x06, mthc_op = 0x07, 118 bc_op = 0x08, bc1eqz_op = 0x09, 119 bc1nez_op = 0x0d, cop_op = 0x10, 120 copm_op = 0x18 121 }; 122 123 /* 124 * rt field of cop.bc_op opcodes 125 */ 126 enum bcop_op { 127 bcf_op, bct_op, bcfl_op, bctl_op 128 }; 129 130 /* 131 * func field of cop0 coi opcodes. 132 */ 133 enum cop0_coi_func { 134 tlbr_op = 0x01, tlbwi_op = 0x02, 135 tlbwr_op = 0x06, tlbp_op = 0x08, 136 rfe_op = 0x10, eret_op = 0x18, 137 wait_op = 0x20, 138 }; 139 140 /* 141 * func field of cop0 com opcodes. 142 */ 143 enum cop0_com_func { 144 tlbr1_op = 0x01, tlbw_op = 0x02, 145 tlbp1_op = 0x08, dctr_op = 0x09, 146 dctw_op = 0x0a 147 }; 148 149 /* 150 * fmt field of cop1 opcodes. 151 */ 152 enum cop1_fmt { 153 s_fmt, d_fmt, e_fmt, q_fmt, 154 w_fmt, l_fmt 155 }; 156 157 /* 158 * func field of cop1 instructions using d, s or w format. 159 */ 160 enum cop1_sdw_func { 161 fadd_op = 0x00, fsub_op = 0x01, 162 fmul_op = 0x02, fdiv_op = 0x03, 163 fsqrt_op = 0x04, fabs_op = 0x05, 164 fmov_op = 0x06, fneg_op = 0x07, 165 froundl_op = 0x08, ftruncl_op = 0x09, 166 fceill_op = 0x0a, ffloorl_op = 0x0b, 167 fround_op = 0x0c, ftrunc_op = 0x0d, 168 fceil_op = 0x0e, ffloor_op = 0x0f, 169 fsel_op = 0x10, 170 fmovc_op = 0x11, fmovz_op = 0x12, 171 fmovn_op = 0x13, fseleqz_op = 0x14, 172 frecip_op = 0x15, frsqrt_op = 0x16, 173 fselnez_op = 0x17, fmaddf_op = 0x18, 174 fmsubf_op = 0x19, frint_op = 0x1a, 175 fclass_op = 0x1b, fmin_op = 0x1c, 176 fmina_op = 0x1d, fmax_op = 0x1e, 177 fmaxa_op = 0x1f, fcvts_op = 0x20, 178 fcvtd_op = 0x21, fcvte_op = 0x22, 179 fcvtw_op = 0x24, fcvtl_op = 0x25, 180 fcmp_op = 0x30 181 }; 182 183 /* 184 * func field of cop1x opcodes (MIPS IV). 185 */ 186 enum cop1x_func { 187 lwxc1_op = 0x00, ldxc1_op = 0x01, 188 swxc1_op = 0x08, sdxc1_op = 0x09, 189 pfetch_op = 0x0f, madd_s_op = 0x20, 190 madd_d_op = 0x21, madd_e_op = 0x22, 191 msub_s_op = 0x28, msub_d_op = 0x29, 192 msub_e_op = 0x2a, nmadd_s_op = 0x30, 193 nmadd_d_op = 0x31, nmadd_e_op = 0x32, 194 nmsub_s_op = 0x38, nmsub_d_op = 0x39, 195 nmsub_e_op = 0x3a 196 }; 197 198 /* 199 * func field for mad opcodes (MIPS IV). 200 */ 201 enum mad_func { 202 madd_fp_op = 0x08, msub_fp_op = 0x0a, 203 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e 204 }; 205 206 /* 207 * func field for special3 lx opcodes (Cavium Octeon). 208 */ 209 enum lx_func { 210 lwx_op = 0x00, 211 lhx_op = 0x04, 212 lbux_op = 0x06, 213 ldx_op = 0x08, 214 lwux_op = 0x10, 215 lhux_op = 0x14, 216 lbx_op = 0x16, 217 }; 218 219 /* 220 * BSHFL opcodes 221 */ 222 enum bshfl_func { 223 wsbh_op = 0x2, 224 dshd_op = 0x5, 225 seb_op = 0x10, 226 seh_op = 0x18, 227 }; 228 229 /* 230 * func field for MSA MI10 format. 231 */ 232 enum msa_mi10_func { 233 msa_ld_op = 8, 234 msa_st_op = 9, 235 }; 236 237 /* 238 * MSA 2 bit format fields. 239 */ 240 enum msa_2b_fmt { 241 msa_fmt_b = 0, 242 msa_fmt_h = 1, 243 msa_fmt_w = 2, 244 msa_fmt_d = 3, 245 }; 246 247 /* 248 * (microMIPS) Major opcodes. 249 */ 250 enum mm_major_op { 251 mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op, 252 mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op, 253 mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op, 254 mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op, 255 mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op, 256 mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op, 257 mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op, 258 mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op, 259 mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op, 260 mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op, 261 mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op, 262 mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op, 263 mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op, 264 mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op, 265 mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op, 266 mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op, 267 }; 268 269 /* 270 * (microMIPS) POOL32I minor opcodes. 271 */ 272 enum mm_32i_minor_op { 273 mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op, 274 mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op, 275 mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op, 276 mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op, 277 mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op, 278 mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op, 279 mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op, 280 mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op, 281 mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op, 282 }; 283 284 /* 285 * (microMIPS) POOL32A minor opcodes. 286 */ 287 enum mm_32a_minor_op { 288 mm_sll32_op = 0x000, 289 mm_ins_op = 0x00c, 290 mm_sllv32_op = 0x010, 291 mm_ext_op = 0x02c, 292 mm_pool32axf_op = 0x03c, 293 mm_srl32_op = 0x040, 294 mm_srlv32_op = 0x050, 295 mm_sra_op = 0x080, 296 mm_rotr_op = 0x0c0, 297 mm_lwxs_op = 0x118, 298 mm_addu32_op = 0x150, 299 mm_subu32_op = 0x1d0, 300 mm_wsbh_op = 0x1ec, 301 mm_mul_op = 0x210, 302 mm_and_op = 0x250, 303 mm_or32_op = 0x290, 304 mm_xor32_op = 0x310, 305 mm_slt_op = 0x350, 306 mm_sltu_op = 0x390, 307 }; 308 309 /* 310 * (microMIPS) POOL32B functions. 311 */ 312 enum mm_32b_func { 313 mm_lwc2_func = 0x0, 314 mm_lwp_func = 0x1, 315 mm_ldc2_func = 0x2, 316 mm_ldp_func = 0x4, 317 mm_lwm32_func = 0x5, 318 mm_cache_func = 0x6, 319 mm_ldm_func = 0x7, 320 mm_swc2_func = 0x8, 321 mm_swp_func = 0x9, 322 mm_sdc2_func = 0xa, 323 mm_sdp_func = 0xc, 324 mm_swm32_func = 0xd, 325 mm_sdm_func = 0xf, 326 }; 327 328 /* 329 * (microMIPS) POOL32C functions. 330 */ 331 enum mm_32c_func { 332 mm_pref_func = 0x2, 333 mm_ll_func = 0x3, 334 mm_swr_func = 0x9, 335 mm_sc_func = 0xb, 336 mm_lwu_func = 0xe, 337 }; 338 339 /* 340 * (microMIPS) POOL32AXF minor opcodes. 341 */ 342 enum mm_32axf_minor_op { 343 mm_mfc0_op = 0x003, 344 mm_mtc0_op = 0x00b, 345 mm_tlbp_op = 0x00d, 346 mm_mfhi32_op = 0x035, 347 mm_jalr_op = 0x03c, 348 mm_tlbr_op = 0x04d, 349 mm_mflo32_op = 0x075, 350 mm_jalrhb_op = 0x07c, 351 mm_tlbwi_op = 0x08d, 352 mm_tlbwr_op = 0x0cd, 353 mm_jalrs_op = 0x13c, 354 mm_jalrshb_op = 0x17c, 355 mm_sync_op = 0x1ad, 356 mm_syscall_op = 0x22d, 357 mm_wait_op = 0x24d, 358 mm_eret_op = 0x3cd, 359 mm_divu_op = 0x5dc, 360 }; 361 362 /* 363 * (microMIPS) POOL32F minor opcodes. 364 */ 365 enum mm_32f_minor_op { 366 mm_32f_00_op = 0x00, 367 mm_32f_01_op = 0x01, 368 mm_32f_02_op = 0x02, 369 mm_32f_10_op = 0x08, 370 mm_32f_11_op = 0x09, 371 mm_32f_12_op = 0x0a, 372 mm_32f_20_op = 0x10, 373 mm_32f_30_op = 0x18, 374 mm_32f_40_op = 0x20, 375 mm_32f_41_op = 0x21, 376 mm_32f_42_op = 0x22, 377 mm_32f_50_op = 0x28, 378 mm_32f_51_op = 0x29, 379 mm_32f_52_op = 0x2a, 380 mm_32f_60_op = 0x30, 381 mm_32f_70_op = 0x38, 382 mm_32f_73_op = 0x3b, 383 mm_32f_74_op = 0x3c, 384 }; 385 386 /* 387 * (microMIPS) POOL32F secondary minor opcodes. 388 */ 389 enum mm_32f_10_minor_op { 390 mm_lwxc1_op = 0x1, 391 mm_swxc1_op, 392 mm_ldxc1_op, 393 mm_sdxc1_op, 394 mm_luxc1_op, 395 mm_suxc1_op, 396 }; 397 398 enum mm_32f_func { 399 mm_lwxc1_func = 0x048, 400 mm_swxc1_func = 0x088, 401 mm_ldxc1_func = 0x0c8, 402 mm_sdxc1_func = 0x108, 403 }; 404 405 /* 406 * (microMIPS) POOL32F secondary minor opcodes. 407 */ 408 enum mm_32f_40_minor_op { 409 mm_fmovf_op, 410 mm_fmovt_op, 411 }; 412 413 /* 414 * (microMIPS) POOL32F secondary minor opcodes. 415 */ 416 enum mm_32f_60_minor_op { 417 mm_fadd_op, 418 mm_fsub_op, 419 mm_fmul_op, 420 mm_fdiv_op, 421 }; 422 423 /* 424 * (microMIPS) POOL32F secondary minor opcodes. 425 */ 426 enum mm_32f_70_minor_op { 427 mm_fmovn_op, 428 mm_fmovz_op, 429 }; 430 431 /* 432 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F. 433 */ 434 enum mm_32f_73_minor_op { 435 mm_fmov0_op = 0x01, 436 mm_fcvtl_op = 0x04, 437 mm_movf0_op = 0x05, 438 mm_frsqrt_op = 0x08, 439 mm_ffloorl_op = 0x0c, 440 mm_fabs0_op = 0x0d, 441 mm_fcvtw_op = 0x24, 442 mm_movt0_op = 0x25, 443 mm_fsqrt_op = 0x28, 444 mm_ffloorw_op = 0x2c, 445 mm_fneg0_op = 0x2d, 446 mm_cfc1_op = 0x40, 447 mm_frecip_op = 0x48, 448 mm_fceill_op = 0x4c, 449 mm_fcvtd0_op = 0x4d, 450 mm_ctc1_op = 0x60, 451 mm_fceilw_op = 0x6c, 452 mm_fcvts0_op = 0x6d, 453 mm_mfc1_op = 0x80, 454 mm_fmov1_op = 0x81, 455 mm_movf1_op = 0x85, 456 mm_ftruncl_op = 0x8c, 457 mm_fabs1_op = 0x8d, 458 mm_mtc1_op = 0xa0, 459 mm_movt1_op = 0xa5, 460 mm_ftruncw_op = 0xac, 461 mm_fneg1_op = 0xad, 462 mm_mfhc1_op = 0xc0, 463 mm_froundl_op = 0xcc, 464 mm_fcvtd1_op = 0xcd, 465 mm_mthc1_op = 0xe0, 466 mm_froundw_op = 0xec, 467 mm_fcvts1_op = 0xed, 468 }; 469 470 /* 471 * (microMIPS) POOL16C minor opcodes. 472 */ 473 enum mm_16c_minor_op { 474 mm_lwm16_op = 0x04, 475 mm_swm16_op = 0x05, 476 mm_jr16_op = 0x0c, 477 mm_jrc_op = 0x0d, 478 mm_jalr16_op = 0x0e, 479 mm_jalrs16_op = 0x0f, 480 mm_jraddiusp_op = 0x18, 481 }; 482 483 /* 484 * (microMIPS) POOL16D minor opcodes. 485 */ 486 enum mm_16d_minor_op { 487 mm_addius5_func, 488 mm_addiusp_func, 489 }; 490 491 /* 492 * (MIPS16e) opcodes. 493 */ 494 enum MIPS16e_ops { 495 MIPS16e_jal_op = 003, 496 MIPS16e_ld_op = 007, 497 MIPS16e_i8_op = 014, 498 MIPS16e_sd_op = 017, 499 MIPS16e_lb_op = 020, 500 MIPS16e_lh_op = 021, 501 MIPS16e_lwsp_op = 022, 502 MIPS16e_lw_op = 023, 503 MIPS16e_lbu_op = 024, 504 MIPS16e_lhu_op = 025, 505 MIPS16e_lwpc_op = 026, 506 MIPS16e_lwu_op = 027, 507 MIPS16e_sb_op = 030, 508 MIPS16e_sh_op = 031, 509 MIPS16e_swsp_op = 032, 510 MIPS16e_sw_op = 033, 511 MIPS16e_rr_op = 035, 512 MIPS16e_extend_op = 036, 513 MIPS16e_i64_op = 037, 514 }; 515 516 enum MIPS16e_i64_func { 517 MIPS16e_ldsp_func, 518 MIPS16e_sdsp_func, 519 MIPS16e_sdrasp_func, 520 MIPS16e_dadjsp_func, 521 MIPS16e_ldpc_func, 522 }; 523 524 enum MIPS16e_rr_func { 525 MIPS16e_jr_func, 526 }; 527 528 enum MIPS6e_i8_func { 529 MIPS16e_swrasp_func = 02, 530 }; 531 532 /* 533 * (microMIPS & MIPS16e) NOP instruction. 534 */ 535 #define MM_NOP16 0x0c00 536 537 struct j_format { 538 __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */ 539 __BITFIELD_FIELD(unsigned int target : 26, 540 ;)) 541 }; 542 543 struct i_format { /* signed immediate format */ 544 __BITFIELD_FIELD(unsigned int opcode : 6, 545 __BITFIELD_FIELD(unsigned int rs : 5, 546 __BITFIELD_FIELD(unsigned int rt : 5, 547 __BITFIELD_FIELD(signed int simmediate : 16, 548 ;)))) 549 }; 550 551 struct u_format { /* unsigned immediate format */ 552 __BITFIELD_FIELD(unsigned int opcode : 6, 553 __BITFIELD_FIELD(unsigned int rs : 5, 554 __BITFIELD_FIELD(unsigned int rt : 5, 555 __BITFIELD_FIELD(unsigned int uimmediate : 16, 556 ;)))) 557 }; 558 559 struct c_format { /* Cache (>= R6000) format */ 560 __BITFIELD_FIELD(unsigned int opcode : 6, 561 __BITFIELD_FIELD(unsigned int rs : 5, 562 __BITFIELD_FIELD(unsigned int c_op : 3, 563 __BITFIELD_FIELD(unsigned int cache : 2, 564 __BITFIELD_FIELD(unsigned int simmediate : 16, 565 ;))))) 566 }; 567 568 struct r_format { /* Register format */ 569 __BITFIELD_FIELD(unsigned int opcode : 6, 570 __BITFIELD_FIELD(unsigned int rs : 5, 571 __BITFIELD_FIELD(unsigned int rt : 5, 572 __BITFIELD_FIELD(unsigned int rd : 5, 573 __BITFIELD_FIELD(unsigned int re : 5, 574 __BITFIELD_FIELD(unsigned int func : 6, 575 ;)))))) 576 }; 577 578 struct p_format { /* Performance counter format (R10000) */ 579 __BITFIELD_FIELD(unsigned int opcode : 6, 580 __BITFIELD_FIELD(unsigned int rs : 5, 581 __BITFIELD_FIELD(unsigned int rt : 5, 582 __BITFIELD_FIELD(unsigned int rd : 5, 583 __BITFIELD_FIELD(unsigned int re : 5, 584 __BITFIELD_FIELD(unsigned int func : 6, 585 ;)))))) 586 }; 587 588 struct f_format { /* FPU register format */ 589 __BITFIELD_FIELD(unsigned int opcode : 6, 590 __BITFIELD_FIELD(unsigned int : 1, 591 __BITFIELD_FIELD(unsigned int fmt : 4, 592 __BITFIELD_FIELD(unsigned int rt : 5, 593 __BITFIELD_FIELD(unsigned int rd : 5, 594 __BITFIELD_FIELD(unsigned int re : 5, 595 __BITFIELD_FIELD(unsigned int func : 6, 596 ;))))))) 597 }; 598 599 struct ma_format { /* FPU multiply and add format (MIPS IV) */ 600 __BITFIELD_FIELD(unsigned int opcode : 6, 601 __BITFIELD_FIELD(unsigned int fr : 5, 602 __BITFIELD_FIELD(unsigned int ft : 5, 603 __BITFIELD_FIELD(unsigned int fs : 5, 604 __BITFIELD_FIELD(unsigned int fd : 5, 605 __BITFIELD_FIELD(unsigned int func : 4, 606 __BITFIELD_FIELD(unsigned int fmt : 2, 607 ;))))))) 608 }; 609 610 struct b_format { /* BREAK and SYSCALL */ 611 __BITFIELD_FIELD(unsigned int opcode : 6, 612 __BITFIELD_FIELD(unsigned int code : 20, 613 __BITFIELD_FIELD(unsigned int func : 6, 614 ;))) 615 }; 616 617 struct ps_format { /* MIPS-3D / paired single format */ 618 __BITFIELD_FIELD(unsigned int opcode : 6, 619 __BITFIELD_FIELD(unsigned int rs : 5, 620 __BITFIELD_FIELD(unsigned int ft : 5, 621 __BITFIELD_FIELD(unsigned int fs : 5, 622 __BITFIELD_FIELD(unsigned int fd : 5, 623 __BITFIELD_FIELD(unsigned int func : 6, 624 ;)))))) 625 }; 626 627 struct v_format { /* MDMX vector format */ 628 __BITFIELD_FIELD(unsigned int opcode : 6, 629 __BITFIELD_FIELD(unsigned int sel : 4, 630 __BITFIELD_FIELD(unsigned int fmt : 1, 631 __BITFIELD_FIELD(unsigned int vt : 5, 632 __BITFIELD_FIELD(unsigned int vs : 5, 633 __BITFIELD_FIELD(unsigned int vd : 5, 634 __BITFIELD_FIELD(unsigned int func : 6, 635 ;))))))) 636 }; 637 638 struct msa_mi10_format { /* MSA MI10 */ 639 __BITFIELD_FIELD(unsigned int opcode : 6, 640 __BITFIELD_FIELD(signed int s10 : 10, 641 __BITFIELD_FIELD(unsigned int rs : 5, 642 __BITFIELD_FIELD(unsigned int wd : 5, 643 __BITFIELD_FIELD(unsigned int func : 4, 644 __BITFIELD_FIELD(unsigned int df : 2, 645 ;)))))) 646 }; 647 648 struct dsp_format { /* SPEC3 DSP format instructions */ 649 __BITFIELD_FIELD(unsigned int opcode : 6, 650 __BITFIELD_FIELD(unsigned int base : 5, 651 __BITFIELD_FIELD(unsigned int index : 5, 652 __BITFIELD_FIELD(unsigned int rd : 5, 653 __BITFIELD_FIELD(unsigned int op : 5, 654 __BITFIELD_FIELD(unsigned int func : 6, 655 ;)))))) 656 }; 657 658 struct spec3_format { /* SPEC3 */ 659 __BITFIELD_FIELD(unsigned int opcode:6, 660 __BITFIELD_FIELD(unsigned int rs:5, 661 __BITFIELD_FIELD(unsigned int rt:5, 662 __BITFIELD_FIELD(signed int simmediate:9, 663 __BITFIELD_FIELD(unsigned int func:7, 664 ;))))) 665 }; 666 667 /* 668 * microMIPS instruction formats (32-bit length) 669 * 670 * NOTE: 671 * Parenthesis denote whether the format is a microMIPS instruction or 672 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE. 673 */ 674 struct fb_format { /* FPU branch format (MIPS32) */ 675 __BITFIELD_FIELD(unsigned int opcode : 6, 676 __BITFIELD_FIELD(unsigned int bc : 5, 677 __BITFIELD_FIELD(unsigned int cc : 3, 678 __BITFIELD_FIELD(unsigned int flag : 2, 679 __BITFIELD_FIELD(signed int simmediate : 16, 680 ;))))) 681 }; 682 683 struct fp0_format { /* FPU multiply and add format (MIPS32) */ 684 __BITFIELD_FIELD(unsigned int opcode : 6, 685 __BITFIELD_FIELD(unsigned int fmt : 5, 686 __BITFIELD_FIELD(unsigned int ft : 5, 687 __BITFIELD_FIELD(unsigned int fs : 5, 688 __BITFIELD_FIELD(unsigned int fd : 5, 689 __BITFIELD_FIELD(unsigned int func : 6, 690 ;)))))) 691 }; 692 693 struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ 694 __BITFIELD_FIELD(unsigned int opcode : 6, 695 __BITFIELD_FIELD(unsigned int ft : 5, 696 __BITFIELD_FIELD(unsigned int fs : 5, 697 __BITFIELD_FIELD(unsigned int fd : 5, 698 __BITFIELD_FIELD(unsigned int fmt : 3, 699 __BITFIELD_FIELD(unsigned int op : 2, 700 __BITFIELD_FIELD(unsigned int func : 6, 701 ;))))))) 702 }; 703 704 struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ 705 __BITFIELD_FIELD(unsigned int opcode : 6, 706 __BITFIELD_FIELD(unsigned int op : 5, 707 __BITFIELD_FIELD(unsigned int rt : 5, 708 __BITFIELD_FIELD(unsigned int fs : 5, 709 __BITFIELD_FIELD(unsigned int fd : 5, 710 __BITFIELD_FIELD(unsigned int func : 6, 711 ;)))))) 712 }; 713 714 struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ 715 __BITFIELD_FIELD(unsigned int opcode : 6, 716 __BITFIELD_FIELD(unsigned int rt : 5, 717 __BITFIELD_FIELD(unsigned int fs : 5, 718 __BITFIELD_FIELD(unsigned int fmt : 2, 719 __BITFIELD_FIELD(unsigned int op : 8, 720 __BITFIELD_FIELD(unsigned int func : 6, 721 ;)))))) 722 }; 723 724 struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ 725 __BITFIELD_FIELD(unsigned int opcode : 6, 726 __BITFIELD_FIELD(unsigned int fd : 5, 727 __BITFIELD_FIELD(unsigned int fs : 5, 728 __BITFIELD_FIELD(unsigned int cc : 3, 729 __BITFIELD_FIELD(unsigned int zero : 2, 730 __BITFIELD_FIELD(unsigned int fmt : 2, 731 __BITFIELD_FIELD(unsigned int op : 3, 732 __BITFIELD_FIELD(unsigned int func : 6, 733 ;)))))))) 734 }; 735 736 struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ 737 __BITFIELD_FIELD(unsigned int opcode : 6, 738 __BITFIELD_FIELD(unsigned int rt : 5, 739 __BITFIELD_FIELD(unsigned int fs : 5, 740 __BITFIELD_FIELD(unsigned int fmt : 3, 741 __BITFIELD_FIELD(unsigned int op : 7, 742 __BITFIELD_FIELD(unsigned int func : 6, 743 ;)))))) 744 }; 745 746 struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ 747 __BITFIELD_FIELD(unsigned int opcode : 6, 748 __BITFIELD_FIELD(unsigned int rt : 5, 749 __BITFIELD_FIELD(unsigned int fs : 5, 750 __BITFIELD_FIELD(unsigned int cc : 3, 751 __BITFIELD_FIELD(unsigned int fmt : 3, 752 __BITFIELD_FIELD(unsigned int cond : 4, 753 __BITFIELD_FIELD(unsigned int func : 6, 754 ;))))))) 755 }; 756 757 struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ 758 __BITFIELD_FIELD(unsigned int opcode : 6, 759 __BITFIELD_FIELD(unsigned int index : 5, 760 __BITFIELD_FIELD(unsigned int base : 5, 761 __BITFIELD_FIELD(unsigned int fd : 5, 762 __BITFIELD_FIELD(unsigned int op : 5, 763 __BITFIELD_FIELD(unsigned int func : 6, 764 ;)))))) 765 }; 766 767 struct fp6_format { /* FPU madd and msub format (MIPS IV) */ 768 __BITFIELD_FIELD(unsigned int opcode : 6, 769 __BITFIELD_FIELD(unsigned int fr : 5, 770 __BITFIELD_FIELD(unsigned int ft : 5, 771 __BITFIELD_FIELD(unsigned int fs : 5, 772 __BITFIELD_FIELD(unsigned int fd : 5, 773 __BITFIELD_FIELD(unsigned int func : 6, 774 ;)))))) 775 }; 776 777 struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ 778 __BITFIELD_FIELD(unsigned int opcode : 6, 779 __BITFIELD_FIELD(unsigned int ft : 5, 780 __BITFIELD_FIELD(unsigned int fs : 5, 781 __BITFIELD_FIELD(unsigned int fd : 5, 782 __BITFIELD_FIELD(unsigned int fr : 5, 783 __BITFIELD_FIELD(unsigned int func : 6, 784 ;)))))) 785 }; 786 787 struct mm_i_format { /* Immediate format (microMIPS) */ 788 __BITFIELD_FIELD(unsigned int opcode : 6, 789 __BITFIELD_FIELD(unsigned int rt : 5, 790 __BITFIELD_FIELD(unsigned int rs : 5, 791 __BITFIELD_FIELD(signed int simmediate : 16, 792 ;)))) 793 }; 794 795 struct mm_m_format { /* Multi-word load/store format (microMIPS) */ 796 __BITFIELD_FIELD(unsigned int opcode : 6, 797 __BITFIELD_FIELD(unsigned int rd : 5, 798 __BITFIELD_FIELD(unsigned int base : 5, 799 __BITFIELD_FIELD(unsigned int func : 4, 800 __BITFIELD_FIELD(signed int simmediate : 12, 801 ;))))) 802 }; 803 804 struct mm_x_format { /* Scaled indexed load format (microMIPS) */ 805 __BITFIELD_FIELD(unsigned int opcode : 6, 806 __BITFIELD_FIELD(unsigned int index : 5, 807 __BITFIELD_FIELD(unsigned int base : 5, 808 __BITFIELD_FIELD(unsigned int rd : 5, 809 __BITFIELD_FIELD(unsigned int func : 11, 810 ;))))) 811 }; 812 813 struct mm_a_format { /* ADDIUPC format (microMIPS) */ 814 __BITFIELD_FIELD(unsigned int opcode : 6, 815 __BITFIELD_FIELD(unsigned int rs : 3, 816 __BITFIELD_FIELD(signed int simmediate : 23, 817 ;))) 818 }; 819 820 /* 821 * microMIPS instruction formats (16-bit length) 822 */ 823 struct mm_b0_format { /* Unconditional branch format (microMIPS) */ 824 __BITFIELD_FIELD(unsigned int opcode : 6, 825 __BITFIELD_FIELD(signed int simmediate : 10, 826 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 827 ;))) 828 }; 829 830 struct mm_b1_format { /* Conditional branch format (microMIPS) */ 831 __BITFIELD_FIELD(unsigned int opcode : 6, 832 __BITFIELD_FIELD(unsigned int rs : 3, 833 __BITFIELD_FIELD(signed int simmediate : 7, 834 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 835 ;)))) 836 }; 837 838 struct mm16_m_format { /* Multi-word load/store format */ 839 __BITFIELD_FIELD(unsigned int opcode : 6, 840 __BITFIELD_FIELD(unsigned int func : 4, 841 __BITFIELD_FIELD(unsigned int rlist : 2, 842 __BITFIELD_FIELD(unsigned int imm : 4, 843 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 844 ;))))) 845 }; 846 847 struct mm16_rb_format { /* Signed immediate format */ 848 __BITFIELD_FIELD(unsigned int opcode : 6, 849 __BITFIELD_FIELD(unsigned int rt : 3, 850 __BITFIELD_FIELD(unsigned int base : 3, 851 __BITFIELD_FIELD(signed int simmediate : 4, 852 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 853 ;))))) 854 }; 855 856 struct mm16_r3_format { /* Load from global pointer format */ 857 __BITFIELD_FIELD(unsigned int opcode : 6, 858 __BITFIELD_FIELD(unsigned int rt : 3, 859 __BITFIELD_FIELD(signed int simmediate : 7, 860 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 861 ;)))) 862 }; 863 864 struct mm16_r5_format { /* Load/store from stack pointer format */ 865 __BITFIELD_FIELD(unsigned int opcode : 6, 866 __BITFIELD_FIELD(unsigned int rt : 5, 867 __BITFIELD_FIELD(unsigned int imm : 5, 868 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 869 ;)))) 870 }; 871 872 /* 873 * MIPS16e instruction formats (16-bit length) 874 */ 875 struct m16e_rr { 876 __BITFIELD_FIELD(unsigned int opcode : 5, 877 __BITFIELD_FIELD(unsigned int rx : 3, 878 __BITFIELD_FIELD(unsigned int nd : 1, 879 __BITFIELD_FIELD(unsigned int l : 1, 880 __BITFIELD_FIELD(unsigned int ra : 1, 881 __BITFIELD_FIELD(unsigned int func : 5, 882 ;)))))) 883 }; 884 885 struct m16e_jal { 886 __BITFIELD_FIELD(unsigned int opcode : 5, 887 __BITFIELD_FIELD(unsigned int x : 1, 888 __BITFIELD_FIELD(unsigned int imm20_16 : 5, 889 __BITFIELD_FIELD(signed int imm25_21 : 5, 890 ;)))) 891 }; 892 893 struct m16e_i64 { 894 __BITFIELD_FIELD(unsigned int opcode : 5, 895 __BITFIELD_FIELD(unsigned int func : 3, 896 __BITFIELD_FIELD(unsigned int imm : 8, 897 ;))) 898 }; 899 900 struct m16e_ri64 { 901 __BITFIELD_FIELD(unsigned int opcode : 5, 902 __BITFIELD_FIELD(unsigned int func : 3, 903 __BITFIELD_FIELD(unsigned int ry : 3, 904 __BITFIELD_FIELD(unsigned int imm : 5, 905 ;)))) 906 }; 907 908 struct m16e_ri { 909 __BITFIELD_FIELD(unsigned int opcode : 5, 910 __BITFIELD_FIELD(unsigned int rx : 3, 911 __BITFIELD_FIELD(unsigned int imm : 8, 912 ;))) 913 }; 914 915 struct m16e_rri { 916 __BITFIELD_FIELD(unsigned int opcode : 5, 917 __BITFIELD_FIELD(unsigned int rx : 3, 918 __BITFIELD_FIELD(unsigned int ry : 3, 919 __BITFIELD_FIELD(unsigned int imm : 5, 920 ;)))) 921 }; 922 923 struct m16e_i8 { 924 __BITFIELD_FIELD(unsigned int opcode : 5, 925 __BITFIELD_FIELD(unsigned int func : 3, 926 __BITFIELD_FIELD(unsigned int imm : 8, 927 ;))) 928 }; 929 930 union mips_instruction { 931 unsigned int word; 932 unsigned short halfword[2]; 933 unsigned char byte[4]; 934 struct j_format j_format; 935 struct i_format i_format; 936 struct u_format u_format; 937 struct c_format c_format; 938 struct r_format r_format; 939 struct p_format p_format; 940 struct f_format f_format; 941 struct ma_format ma_format; 942 struct msa_mi10_format msa_mi10_format; 943 struct b_format b_format; 944 struct ps_format ps_format; 945 struct v_format v_format; 946 struct dsp_format dsp_format; 947 struct spec3_format spec3_format; 948 struct fb_format fb_format; 949 struct fp0_format fp0_format; 950 struct mm_fp0_format mm_fp0_format; 951 struct fp1_format fp1_format; 952 struct mm_fp1_format mm_fp1_format; 953 struct mm_fp2_format mm_fp2_format; 954 struct mm_fp3_format mm_fp3_format; 955 struct mm_fp4_format mm_fp4_format; 956 struct mm_fp5_format mm_fp5_format; 957 struct fp6_format fp6_format; 958 struct mm_fp6_format mm_fp6_format; 959 struct mm_i_format mm_i_format; 960 struct mm_m_format mm_m_format; 961 struct mm_x_format mm_x_format; 962 struct mm_a_format mm_a_format; 963 struct mm_b0_format mm_b0_format; 964 struct mm_b1_format mm_b1_format; 965 struct mm16_m_format mm16_m_format ; 966 struct mm16_rb_format mm16_rb_format; 967 struct mm16_r3_format mm16_r3_format; 968 struct mm16_r5_format mm16_r5_format; 969 }; 970 971 union mips16e_instruction { 972 unsigned int full : 16; 973 struct m16e_rr rr; 974 struct m16e_jal jal; 975 struct m16e_i64 i64; 976 struct m16e_ri64 ri64; 977 struct m16e_ri ri; 978 struct m16e_rri rri; 979 struct m16e_i8 i8; 980 }; 981 982 #endif /* _UAPI_ASM_INST_H */ 983