1 /*
2 * arch/arm/mach-lpc32xx/common.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/err.h>
24 #include <linux/i2c.h>
25 #include <linux/i2c-pnx.h>
26 #include <linux/io.h>
27
28 #include <asm/mach/map.h>
29 #include <asm/system_info.h>
30
31 #include <mach/hardware.h>
32 #include <mach/platform.h>
33 #include "common.h"
34
35 /*
36 * Returns the unique ID for the device
37 */
lpc32xx_get_uid(u32 devid[4])38 void lpc32xx_get_uid(u32 devid[4])
39 {
40 int i;
41
42 for (i = 0; i < 4; i++)
43 devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
44 }
45
46 /*
47 * Returns SYSCLK source
48 * 0 = PLL397, 1 = main oscillator
49 */
clk_is_sysclk_mainosc(void)50 int clk_is_sysclk_mainosc(void)
51 {
52 if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) &
53 LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0)
54 return 1;
55
56 return 0;
57 }
58
59 /*
60 * Detects and returns IRAM size for the device variation
61 */
62 #define LPC32XX_IRAM_BANK_SIZE SZ_128K
63 static u32 iram_size;
lpc32xx_return_iram_size(void)64 u32 lpc32xx_return_iram_size(void)
65 {
66 if (iram_size == 0) {
67 u32 savedval1, savedval2;
68 void __iomem *iramptr1, *iramptr2;
69
70 iramptr1 = io_p2v(LPC32XX_IRAM_BASE);
71 iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
72 savedval1 = __raw_readl(iramptr1);
73 savedval2 = __raw_readl(iramptr2);
74
75 if (savedval1 == savedval2) {
76 __raw_writel(savedval2 + 1, iramptr2);
77 if (__raw_readl(iramptr1) == savedval2 + 1)
78 iram_size = LPC32XX_IRAM_BANK_SIZE;
79 else
80 iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
81 __raw_writel(savedval2, iramptr2);
82 } else
83 iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
84 }
85
86 return iram_size;
87 }
88 EXPORT_SYMBOL_GPL(lpc32xx_return_iram_size);
89
90 /*
91 * Computes PLL rate from PLL register and input clock
92 */
clk_check_pll_setup(u32 ifreq,struct clk_pll_setup * pllsetup)93 u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup)
94 {
95 u32 ilfreq, p, m, n, fcco, fref, cfreq;
96 int mode;
97
98 /*
99 * PLL requirements
100 * ifreq must be >= 1MHz and <= 20MHz
101 * FCCO must be >= 156MHz and <= 320MHz
102 * FREF must be >= 1MHz and <= 27MHz
103 * Assume the passed input data is not valid
104 */
105
106 ilfreq = ifreq;
107 m = pllsetup->pll_m;
108 n = pllsetup->pll_n;
109 p = pllsetup->pll_p;
110
111 mode = (pllsetup->cco_bypass_b15 << 2) |
112 (pllsetup->direct_output_b14 << 1) |
113 pllsetup->fdbk_div_ctrl_b13;
114
115 switch (mode) {
116 case 0x0: /* Non-integer mode */
117 cfreq = (m * ilfreq) / (2 * p * n);
118 fcco = (m * ilfreq) / n;
119 fref = ilfreq / n;
120 break;
121
122 case 0x1: /* integer mode */
123 cfreq = (m * ilfreq) / n;
124 fcco = (m * ilfreq) / (n * 2 * p);
125 fref = ilfreq / n;
126 break;
127
128 case 0x2:
129 case 0x3: /* Direct mode */
130 cfreq = (m * ilfreq) / n;
131 fcco = cfreq;
132 fref = ilfreq / n;
133 break;
134
135 case 0x4:
136 case 0x5: /* Bypass mode */
137 cfreq = ilfreq / (2 * p);
138 fcco = 156000000;
139 fref = 1000000;
140 break;
141
142 case 0x6:
143 case 0x7: /* Direct bypass mode */
144 default:
145 cfreq = ilfreq;
146 fcco = 156000000;
147 fref = 1000000;
148 break;
149 }
150
151 if (fcco < 156000000 || fcco > 320000000)
152 cfreq = 0;
153
154 if (fref < 1000000 || fref > 27000000)
155 cfreq = 0;
156
157 return (u32) cfreq;
158 }
159
clk_get_pclk_div(void)160 u32 clk_get_pclk_div(void)
161 {
162 return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F);
163 }
164
165 static struct map_desc lpc32xx_io_desc[] __initdata = {
166 {
167 .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START),
168 .pfn = __phys_to_pfn(LPC32XX_AHB0_START),
169 .length = LPC32XX_AHB0_SIZE,
170 .type = MT_DEVICE
171 },
172 {
173 .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB1_START),
174 .pfn = __phys_to_pfn(LPC32XX_AHB1_START),
175 .length = LPC32XX_AHB1_SIZE,
176 .type = MT_DEVICE
177 },
178 {
179 .virtual = (unsigned long)IO_ADDRESS(LPC32XX_FABAPB_START),
180 .pfn = __phys_to_pfn(LPC32XX_FABAPB_START),
181 .length = LPC32XX_FABAPB_SIZE,
182 .type = MT_DEVICE
183 },
184 {
185 .virtual = (unsigned long)IO_ADDRESS(LPC32XX_IRAM_BASE),
186 .pfn = __phys_to_pfn(LPC32XX_IRAM_BASE),
187 .length = (LPC32XX_IRAM_BANK_SIZE * 2),
188 .type = MT_DEVICE
189 },
190 };
191
lpc32xx_map_io(void)192 void __init lpc32xx_map_io(void)
193 {
194 iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
195 }
196
lpc23xx_restart(enum reboot_mode mode,const char * cmd)197 void lpc23xx_restart(enum reboot_mode mode, const char *cmd)
198 {
199 /* Make sure WDT clocks are enabled */
200 __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
201 LPC32XX_CLKPWR_TIMER_CLK_CTRL);
202
203 /* Instant assert of RESETOUT_N with pulse length 1mS */
204 __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
205 __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
206
207 /* Wait for watchdog to reset system */
208 while (1)
209 ;
210 }
211
lpc32xx_check_uid(void)212 static int __init lpc32xx_check_uid(void)
213 {
214 u32 uid[4];
215
216 lpc32xx_get_uid(uid);
217
218 printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
219 uid[3], uid[2], uid[1], uid[0]);
220
221 if (!system_serial_low && !system_serial_high) {
222 system_serial_low = uid[0];
223 system_serial_high = uid[1];
224 }
225
226 return 1;
227 }
228 arch_initcall(lpc32xx_check_uid);
229