1 /*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/init.h>
19 #include <linux/platform_device.h>
20 #include <linux/io.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/module.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
26
27 #include <lantiq_soc.h>
28 #include <xway_dma.h>
29
30 #define LTQ_DMA_ID 0x08
31 #define LTQ_DMA_CTRL 0x10
32 #define LTQ_DMA_CPOLL 0x14
33 #define LTQ_DMA_CS 0x18
34 #define LTQ_DMA_CCTRL 0x1C
35 #define LTQ_DMA_CDBA 0x20
36 #define LTQ_DMA_CDLEN 0x24
37 #define LTQ_DMA_CIS 0x28
38 #define LTQ_DMA_CIE 0x2C
39 #define LTQ_DMA_PS 0x40
40 #define LTQ_DMA_PCTRL 0x44
41 #define LTQ_DMA_IRNEN 0xf4
42
43 #define DMA_ID_CHNR GENMASK(26, 20) /* channel number */
44 #define DMA_DESCPT BIT(3) /* descriptor complete irq */
45 #define DMA_TX BIT(8) /* TX channel direction */
46 #define DMA_CHAN_ON BIT(0) /* channel on / off bit */
47 #define DMA_PDEN BIT(6) /* enable packet drop */
48 #define DMA_CHAN_RST BIT(1) /* channel on / off bit */
49 #define DMA_RESET BIT(0) /* channel on / off bit */
50 #define DMA_IRQ_ACK 0x7e /* IRQ status register */
51 #define DMA_POLL BIT(31) /* turn on channel polling */
52 #define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
53 #define DMA_2W_BURST BIT(1) /* 2 word burst length */
54 #define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */
55 #define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
56
57 #define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x))
58 #define ltq_dma_w32(x, y) ltq_w32(x, ltq_dma_membase + (y))
59 #define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \
60 ltq_dma_membase + (z))
61
62 static void __iomem *ltq_dma_membase;
63
64 void
ltq_dma_enable_irq(struct ltq_dma_channel * ch)65 ltq_dma_enable_irq(struct ltq_dma_channel *ch)
66 {
67 unsigned long flags;
68
69 local_irq_save(flags);
70 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
71 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
72 local_irq_restore(flags);
73 }
74 EXPORT_SYMBOL_GPL(ltq_dma_enable_irq);
75
76 void
ltq_dma_disable_irq(struct ltq_dma_channel * ch)77 ltq_dma_disable_irq(struct ltq_dma_channel *ch)
78 {
79 unsigned long flags;
80
81 local_irq_save(flags);
82 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
83 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
84 local_irq_restore(flags);
85 }
86 EXPORT_SYMBOL_GPL(ltq_dma_disable_irq);
87
88 void
ltq_dma_ack_irq(struct ltq_dma_channel * ch)89 ltq_dma_ack_irq(struct ltq_dma_channel *ch)
90 {
91 unsigned long flags;
92
93 local_irq_save(flags);
94 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
95 ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS);
96 local_irq_restore(flags);
97 }
98 EXPORT_SYMBOL_GPL(ltq_dma_ack_irq);
99
100 void
ltq_dma_open(struct ltq_dma_channel * ch)101 ltq_dma_open(struct ltq_dma_channel *ch)
102 {
103 unsigned long flag;
104
105 local_irq_save(flag);
106 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
107 ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);
108 ltq_dma_enable_irq(ch);
109 local_irq_restore(flag);
110 }
111 EXPORT_SYMBOL_GPL(ltq_dma_open);
112
113 void
ltq_dma_close(struct ltq_dma_channel * ch)114 ltq_dma_close(struct ltq_dma_channel *ch)
115 {
116 unsigned long flag;
117
118 local_irq_save(flag);
119 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
120 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
121 ltq_dma_disable_irq(ch);
122 local_irq_restore(flag);
123 }
124 EXPORT_SYMBOL_GPL(ltq_dma_close);
125
126 static void
ltq_dma_alloc(struct ltq_dma_channel * ch)127 ltq_dma_alloc(struct ltq_dma_channel *ch)
128 {
129 unsigned long flags;
130
131 ch->desc = 0;
132 ch->desc_base = dma_alloc_coherent(NULL,
133 LTQ_DESC_NUM * LTQ_DESC_SIZE,
134 &ch->phys, GFP_ATOMIC);
135 memset(ch->desc_base, 0, LTQ_DESC_NUM * LTQ_DESC_SIZE);
136
137 local_irq_save(flags);
138 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
139 ltq_dma_w32(ch->phys, LTQ_DMA_CDBA);
140 ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN);
141 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
142 wmb();
143 ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL);
144 while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST)
145 ;
146 local_irq_restore(flags);
147 }
148
149 void
ltq_dma_alloc_tx(struct ltq_dma_channel * ch)150 ltq_dma_alloc_tx(struct ltq_dma_channel *ch)
151 {
152 unsigned long flags;
153
154 ltq_dma_alloc(ch);
155
156 local_irq_save(flags);
157 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
158 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
159 ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL);
160 local_irq_restore(flags);
161 }
162 EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx);
163
164 void
ltq_dma_alloc_rx(struct ltq_dma_channel * ch)165 ltq_dma_alloc_rx(struct ltq_dma_channel *ch)
166 {
167 unsigned long flags;
168
169 ltq_dma_alloc(ch);
170
171 local_irq_save(flags);
172 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
173 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
174 ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL);
175 local_irq_restore(flags);
176 }
177 EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx);
178
179 void
ltq_dma_free(struct ltq_dma_channel * ch)180 ltq_dma_free(struct ltq_dma_channel *ch)
181 {
182 if (!ch->desc_base)
183 return;
184 ltq_dma_close(ch);
185 dma_free_coherent(NULL, LTQ_DESC_NUM * LTQ_DESC_SIZE,
186 ch->desc_base, ch->phys);
187 }
188 EXPORT_SYMBOL_GPL(ltq_dma_free);
189
190 void
ltq_dma_init_port(int p)191 ltq_dma_init_port(int p)
192 {
193 ltq_dma_w32(p, LTQ_DMA_PS);
194 switch (p) {
195 case DMA_PORT_ETOP:
196 /*
197 * Tell the DMA engine to swap the endianness of data frames and
198 * drop packets if the channel arbitration fails.
199 */
200 ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN,
201 LTQ_DMA_PCTRL);
202 break;
203
204 case DMA_PORT_DEU:
205 ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2),
206 LTQ_DMA_PCTRL);
207 break;
208
209 default:
210 break;
211 }
212 }
213 EXPORT_SYMBOL_GPL(ltq_dma_init_port);
214
215 static int
ltq_dma_init(struct platform_device * pdev)216 ltq_dma_init(struct platform_device *pdev)
217 {
218 struct clk *clk;
219 struct resource *res;
220 unsigned int id, nchannels;
221 int i;
222
223 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
224 ltq_dma_membase = devm_ioremap_resource(&pdev->dev, res);
225 if (IS_ERR(ltq_dma_membase))
226 panic("Failed to remap dma resource");
227
228 /* power up and reset the dma engine */
229 clk = clk_get(&pdev->dev, NULL);
230 if (IS_ERR(clk))
231 panic("Failed to get dma clock");
232
233 clk_enable(clk);
234 ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
235
236 usleep_range(1, 10);
237
238 /* disable all interrupts */
239 ltq_dma_w32(0, LTQ_DMA_IRNEN);
240
241 /* reset/configure each channel */
242 id = ltq_dma_r32(LTQ_DMA_ID);
243 nchannels = ((id & DMA_ID_CHNR) >> 20);
244 for (i = 0; i < nchannels; i++) {
245 ltq_dma_w32(i, LTQ_DMA_CS);
246 ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
247 ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
248 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
249 }
250
251 dev_info(&pdev->dev,
252 "Init done - hw rev: %X, ports: %d, channels: %d\n",
253 id & 0x1f, (id >> 16) & 0xf, nchannels);
254
255 return 0;
256 }
257
258 static const struct of_device_id dma_match[] = {
259 { .compatible = "lantiq,dma-xway" },
260 {},
261 };
262 MODULE_DEVICE_TABLE(of, dma_match);
263
264 static struct platform_driver dma_driver = {
265 .probe = ltq_dma_init,
266 .driver = {
267 .name = "dma-xway",
268 .of_match_table = dma_match,
269 },
270 };
271
272 int __init
dma_init(void)273 dma_init(void)
274 {
275 return platform_driver_register(&dma_driver);
276 }
277
278 postcore_initcall(dma_init);
279