1 /*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
8 */
9
10 #include <linux/interrupt.h>
11 #include <linux/ioport.h>
12 #include <linux/sched.h>
13 #include <linux/irqdomain.h>
14 #include <linux/of_platform.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17
18 #include <asm/bootinfo.h>
19 #include <asm/irq_cpu.h>
20
21 #include <lantiq_soc.h>
22 #include <irq.h>
23
24 /* register definitions - internal irqs */
25 #define LTQ_ICU_IM0_ISR 0x0000
26 #define LTQ_ICU_IM0_IER 0x0008
27 #define LTQ_ICU_IM0_IOSR 0x0010
28 #define LTQ_ICU_IM0_IRSR 0x0018
29 #define LTQ_ICU_IM0_IMR 0x0020
30 #define LTQ_ICU_IM1_ISR 0x0028
31 #define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
32
33 /* register definitions - external irqs */
34 #define LTQ_EIU_EXIN_C 0x0000
35 #define LTQ_EIU_EXIN_INIC 0x0004
36 #define LTQ_EIU_EXIN_INC 0x0008
37 #define LTQ_EIU_EXIN_INEN 0x000C
38
39 /* number of external interrupts */
40 #define MAX_EIU 6
41
42 /* the performance counter */
43 #define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31)
44
45 /*
46 * irqs generated by devices attached to the EBU need to be acked in
47 * a special manner
48 */
49 #define LTQ_ICU_EBU_IRQ 22
50
51 #define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y))
52 #define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x))
53
54 #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
55 #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
56
57 /* our 2 ipi interrupts for VSMP */
58 #define MIPS_CPU_IPI_RESCHED_IRQ 0
59 #define MIPS_CPU_IPI_CALL_IRQ 1
60
61 /* we have a cascade of 8 irqs */
62 #define MIPS_CPU_IRQ_CASCADE 8
63
64 #ifdef CONFIG_MIPS_MT_SMP
65 int gic_present;
66 #endif
67
68 static int exin_avail;
69 static struct resource ltq_eiu_irq[MAX_EIU];
70 static void __iomem *ltq_icu_membase[MAX_IM];
71 static void __iomem *ltq_eiu_membase;
72 static struct irq_domain *ltq_domain;
73 static int ltq_perfcount_irq;
74
ltq_eiu_get_irq(int exin)75 int ltq_eiu_get_irq(int exin)
76 {
77 if (exin < exin_avail)
78 return ltq_eiu_irq[exin].start;
79 return -1;
80 }
81
ltq_disable_irq(struct irq_data * d)82 void ltq_disable_irq(struct irq_data *d)
83 {
84 u32 ier = LTQ_ICU_IM0_IER;
85 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
86 int im = offset / INT_NUM_IM_OFFSET;
87
88 offset %= INT_NUM_IM_OFFSET;
89 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
90 }
91
ltq_mask_and_ack_irq(struct irq_data * d)92 void ltq_mask_and_ack_irq(struct irq_data *d)
93 {
94 u32 ier = LTQ_ICU_IM0_IER;
95 u32 isr = LTQ_ICU_IM0_ISR;
96 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
97 int im = offset / INT_NUM_IM_OFFSET;
98
99 offset %= INT_NUM_IM_OFFSET;
100 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
101 ltq_icu_w32(im, BIT(offset), isr);
102 }
103
ltq_ack_irq(struct irq_data * d)104 static void ltq_ack_irq(struct irq_data *d)
105 {
106 u32 isr = LTQ_ICU_IM0_ISR;
107 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
108 int im = offset / INT_NUM_IM_OFFSET;
109
110 offset %= INT_NUM_IM_OFFSET;
111 ltq_icu_w32(im, BIT(offset), isr);
112 }
113
ltq_enable_irq(struct irq_data * d)114 void ltq_enable_irq(struct irq_data *d)
115 {
116 u32 ier = LTQ_ICU_IM0_IER;
117 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
118 int im = offset / INT_NUM_IM_OFFSET;
119
120 offset %= INT_NUM_IM_OFFSET;
121 ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
122 }
123
ltq_eiu_settype(struct irq_data * d,unsigned int type)124 static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
125 {
126 int i;
127
128 for (i = 0; i < MAX_EIU; i++) {
129 if (d->hwirq == ltq_eiu_irq[i].start) {
130 int val = 0;
131 int edge = 0;
132
133 switch (type) {
134 case IRQF_TRIGGER_NONE:
135 break;
136 case IRQF_TRIGGER_RISING:
137 val = 1;
138 edge = 1;
139 break;
140 case IRQF_TRIGGER_FALLING:
141 val = 2;
142 edge = 1;
143 break;
144 case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
145 val = 3;
146 edge = 1;
147 break;
148 case IRQF_TRIGGER_HIGH:
149 val = 5;
150 break;
151 case IRQF_TRIGGER_LOW:
152 val = 6;
153 break;
154 default:
155 pr_err("invalid type %d for irq %ld\n",
156 type, d->hwirq);
157 return -EINVAL;
158 }
159
160 if (edge)
161 irq_set_handler(d->hwirq, handle_edge_irq);
162
163 ltq_eiu_w32((ltq_eiu_r32(LTQ_EIU_EXIN_C) &
164 (~(7 << (i * 4)))) | (val << (i * 4)),
165 LTQ_EIU_EXIN_C);
166 }
167 }
168
169 return 0;
170 }
171
ltq_startup_eiu_irq(struct irq_data * d)172 static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
173 {
174 int i;
175
176 ltq_enable_irq(d);
177 for (i = 0; i < MAX_EIU; i++) {
178 if (d->hwirq == ltq_eiu_irq[i].start) {
179 /* by default we are low level triggered */
180 ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
181 /* clear all pending */
182 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i),
183 LTQ_EIU_EXIN_INC);
184 /* enable */
185 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
186 LTQ_EIU_EXIN_INEN);
187 break;
188 }
189 }
190
191 return 0;
192 }
193
ltq_shutdown_eiu_irq(struct irq_data * d)194 static void ltq_shutdown_eiu_irq(struct irq_data *d)
195 {
196 int i;
197
198 ltq_disable_irq(d);
199 for (i = 0; i < MAX_EIU; i++) {
200 if (d->hwirq == ltq_eiu_irq[i].start) {
201 /* disable */
202 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
203 LTQ_EIU_EXIN_INEN);
204 break;
205 }
206 }
207 }
208
209 static struct irq_chip ltq_irq_type = {
210 "icu",
211 .irq_enable = ltq_enable_irq,
212 .irq_disable = ltq_disable_irq,
213 .irq_unmask = ltq_enable_irq,
214 .irq_ack = ltq_ack_irq,
215 .irq_mask = ltq_disable_irq,
216 .irq_mask_ack = ltq_mask_and_ack_irq,
217 };
218
219 static struct irq_chip ltq_eiu_type = {
220 "eiu",
221 .irq_startup = ltq_startup_eiu_irq,
222 .irq_shutdown = ltq_shutdown_eiu_irq,
223 .irq_enable = ltq_enable_irq,
224 .irq_disable = ltq_disable_irq,
225 .irq_unmask = ltq_enable_irq,
226 .irq_ack = ltq_ack_irq,
227 .irq_mask = ltq_disable_irq,
228 .irq_mask_ack = ltq_mask_and_ack_irq,
229 .irq_set_type = ltq_eiu_settype,
230 };
231
ltq_hw_irqdispatch(int module)232 static void ltq_hw_irqdispatch(int module)
233 {
234 u32 irq;
235
236 irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
237 if (irq == 0)
238 return;
239
240 /*
241 * silicon bug causes only the msb set to 1 to be valid. all
242 * other bits might be bogus
243 */
244 irq = __fls(irq);
245 do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));
246
247 /* if this is a EBU irq, we need to ack it or get a deadlock */
248 if (irq == LTQ_ICU_EBU_IRQ && !module && LTQ_EBU_PCC_ISTAT != 0)
249 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
250 LTQ_EBU_PCC_ISTAT);
251 }
252
253 #define DEFINE_HWx_IRQDISPATCH(x) \
254 static void ltq_hw ## x ## _irqdispatch(void) \
255 { \
256 ltq_hw_irqdispatch(x); \
257 }
258 DEFINE_HWx_IRQDISPATCH(0)
259 DEFINE_HWx_IRQDISPATCH(1)
260 DEFINE_HWx_IRQDISPATCH(2)
261 DEFINE_HWx_IRQDISPATCH(3)
262 DEFINE_HWx_IRQDISPATCH(4)
263
264 #if MIPS_CPU_TIMER_IRQ == 7
ltq_hw5_irqdispatch(void)265 static void ltq_hw5_irqdispatch(void)
266 {
267 do_IRQ(MIPS_CPU_TIMER_IRQ);
268 }
269 #else
270 DEFINE_HWx_IRQDISPATCH(5)
271 #endif
272
273 #ifdef CONFIG_MIPS_MT_SMP
arch_init_ipiirq(int irq,struct irqaction * action)274 void __init arch_init_ipiirq(int irq, struct irqaction *action)
275 {
276 setup_irq(irq, action);
277 irq_set_handler(irq, handle_percpu_irq);
278 }
279
ltq_sw0_irqdispatch(void)280 static void ltq_sw0_irqdispatch(void)
281 {
282 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
283 }
284
ltq_sw1_irqdispatch(void)285 static void ltq_sw1_irqdispatch(void)
286 {
287 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
288 }
ipi_resched_interrupt(int irq,void * dev_id)289 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
290 {
291 scheduler_ipi();
292 return IRQ_HANDLED;
293 }
294
ipi_call_interrupt(int irq,void * dev_id)295 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
296 {
297 generic_smp_call_function_interrupt();
298 return IRQ_HANDLED;
299 }
300
301 static struct irqaction irq_resched = {
302 .handler = ipi_resched_interrupt,
303 .flags = IRQF_PERCPU,
304 .name = "IPI_resched"
305 };
306
307 static struct irqaction irq_call = {
308 .handler = ipi_call_interrupt,
309 .flags = IRQF_PERCPU,
310 .name = "IPI_call"
311 };
312 #endif
313
plat_irq_dispatch(void)314 asmlinkage void plat_irq_dispatch(void)
315 {
316 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
317 unsigned int i;
318
319 if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) {
320 do_IRQ(MIPS_CPU_TIMER_IRQ);
321 goto out;
322 } else {
323 for (i = 0; i < MAX_IM; i++) {
324 if (pending & (CAUSEF_IP2 << i)) {
325 ltq_hw_irqdispatch(i);
326 goto out;
327 }
328 }
329 }
330 pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
331
332 out:
333 return;
334 }
335
icu_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)336 static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
337 {
338 struct irq_chip *chip = <q_irq_type;
339 int i;
340
341 if (hw < MIPS_CPU_IRQ_CASCADE)
342 return 0;
343
344 for (i = 0; i < exin_avail; i++)
345 if (hw == ltq_eiu_irq[i].start)
346 chip = <q_eiu_type;
347
348 irq_set_chip_and_handler(hw, chip, handle_level_irq);
349
350 return 0;
351 }
352
353 static const struct irq_domain_ops irq_domain_ops = {
354 .xlate = irq_domain_xlate_onetwocell,
355 .map = icu_map,
356 };
357
358 static struct irqaction cascade = {
359 .handler = no_action,
360 .name = "cascade",
361 };
362
icu_of_init(struct device_node * node,struct device_node * parent)363 int __init icu_of_init(struct device_node *node, struct device_node *parent)
364 {
365 struct device_node *eiu_node;
366 struct resource res;
367 int i, ret;
368
369 for (i = 0; i < MAX_IM; i++) {
370 if (of_address_to_resource(node, i, &res))
371 panic("Failed to get icu memory range");
372
373 if (!request_mem_region(res.start, resource_size(&res),
374 res.name))
375 pr_err("Failed to request icu memory");
376
377 ltq_icu_membase[i] = ioremap_nocache(res.start,
378 resource_size(&res));
379 if (!ltq_icu_membase[i])
380 panic("Failed to remap icu memory");
381 }
382
383 /* turn off all irqs by default */
384 for (i = 0; i < MAX_IM; i++) {
385 /* make sure all irqs are turned off by default */
386 ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
387 /* clear all possibly pending interrupts */
388 ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
389 }
390
391 mips_cpu_irq_init();
392
393 for (i = 0; i < MAX_IM; i++)
394 setup_irq(i + 2, &cascade);
395
396 if (cpu_has_vint) {
397 pr_info("Setting up vectored interrupts\n");
398 set_vi_handler(2, ltq_hw0_irqdispatch);
399 set_vi_handler(3, ltq_hw1_irqdispatch);
400 set_vi_handler(4, ltq_hw2_irqdispatch);
401 set_vi_handler(5, ltq_hw3_irqdispatch);
402 set_vi_handler(6, ltq_hw4_irqdispatch);
403 set_vi_handler(7, ltq_hw5_irqdispatch);
404 }
405
406 ltq_domain = irq_domain_add_linear(node,
407 (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
408 &irq_domain_ops, 0);
409
410 #if defined(CONFIG_MIPS_MT_SMP)
411 if (cpu_has_vint) {
412 pr_info("Setting up IPI vectored interrupts\n");
413 set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
414 set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
415 }
416 arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
417 &irq_resched);
418 arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
419 #endif
420
421 #ifndef CONFIG_MIPS_MT_SMP
422 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
423 IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
424 #else
425 set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
426 IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
427 #endif
428
429 /* tell oprofile which irq to use */
430 ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);
431
432 /*
433 * if the timer irq is not one of the mips irqs we need to
434 * create a mapping
435 */
436 if (MIPS_CPU_TIMER_IRQ != 7)
437 irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);
438
439 /* the external interrupts are optional and xway only */
440 eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
441 if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
442 /* find out how many external irq sources we have */
443 exin_avail = of_irq_count(eiu_node);
444
445 if (exin_avail > MAX_EIU)
446 exin_avail = MAX_EIU;
447
448 ret = of_irq_to_resource_table(eiu_node,
449 ltq_eiu_irq, exin_avail);
450 if (ret != exin_avail)
451 panic("failed to load external irq resources");
452
453 if (!request_mem_region(res.start, resource_size(&res),
454 res.name))
455 pr_err("Failed to request eiu memory");
456
457 ltq_eiu_membase = ioremap_nocache(res.start,
458 resource_size(&res));
459 if (!ltq_eiu_membase)
460 panic("Failed to remap eiu memory");
461 }
462
463 return 0;
464 }
465
get_c0_perfcount_int(void)466 int get_c0_perfcount_int(void)
467 {
468 return ltq_perfcount_irq;
469 }
470 EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
471
get_c0_compare_int(void)472 unsigned int get_c0_compare_int(void)
473 {
474 return MIPS_CPU_TIMER_IRQ;
475 }
476
477 static struct of_device_id __initdata of_irq_ids[] = {
478 { .compatible = "lantiq,icu", .data = icu_of_init },
479 {},
480 };
481
arch_init_irq(void)482 void __init arch_init_irq(void)
483 {
484 of_irq_init(of_irq_ids);
485 }
486