1 /*
2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 *
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
12 */
13
14 /*
15 * This file handles the architecture-dependent parts of hardware exceptions
16 */
17
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
21 #include <linux/mm.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/prctl.h>
30 #include <linux/delay.h>
31 #include <linux/kprobes.h>
32 #include <linux/kexec.h>
33 #include <linux/backlight.h>
34 #include <linux/bug.h>
35 #include <linux/kdebug.h>
36 #include <linux/debugfs.h>
37 #include <linux/ratelimit.h>
38 #include <linux/context_tracking.h>
39
40 #include <asm/emulated_ops.h>
41 #include <asm/pgtable.h>
42 #include <asm/uaccess.h>
43 #include <asm/io.h>
44 #include <asm/machdep.h>
45 #include <asm/rtas.h>
46 #include <asm/pmc.h>
47 #include <asm/reg.h>
48 #ifdef CONFIG_PMAC_BACKLIGHT
49 #include <asm/backlight.h>
50 #endif
51 #ifdef CONFIG_PPC64
52 #include <asm/firmware.h>
53 #include <asm/processor.h>
54 #include <asm/tm.h>
55 #endif
56 #include <asm/kexec.h>
57 #include <asm/ppc-opcode.h>
58 #include <asm/rio.h>
59 #include <asm/fadump.h>
60 #include <asm/switch_to.h>
61 #include <asm/tm.h>
62 #include <asm/debug.h>
63 #include <sysdev/fsl_pci.h>
64
65 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
66 int (*__debugger)(struct pt_regs *regs) __read_mostly;
67 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
68 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
69 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
70 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
71 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
72 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
73
74 EXPORT_SYMBOL(__debugger);
75 EXPORT_SYMBOL(__debugger_ipi);
76 EXPORT_SYMBOL(__debugger_bpt);
77 EXPORT_SYMBOL(__debugger_sstep);
78 EXPORT_SYMBOL(__debugger_iabr_match);
79 EXPORT_SYMBOL(__debugger_break_match);
80 EXPORT_SYMBOL(__debugger_fault_handler);
81 #endif
82
83 /* Transactional Memory trap debug */
84 #ifdef TM_DEBUG_SW
85 #define TM_DEBUG(x...) printk(KERN_INFO x)
86 #else
87 #define TM_DEBUG(x...) do { } while(0)
88 #endif
89
90 /*
91 * Trap & Exception support
92 */
93
94 #ifdef CONFIG_PMAC_BACKLIGHT
pmac_backlight_unblank(void)95 static void pmac_backlight_unblank(void)
96 {
97 mutex_lock(&pmac_backlight_mutex);
98 if (pmac_backlight) {
99 struct backlight_properties *props;
100
101 props = &pmac_backlight->props;
102 props->brightness = props->max_brightness;
103 props->power = FB_BLANK_UNBLANK;
104 backlight_update_status(pmac_backlight);
105 }
106 mutex_unlock(&pmac_backlight_mutex);
107 }
108 #else
pmac_backlight_unblank(void)109 static inline void pmac_backlight_unblank(void) { }
110 #endif
111
112 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
113 static int die_owner = -1;
114 static unsigned int die_nest_count;
115 static int die_counter;
116
oops_begin(struct pt_regs * regs)117 static unsigned __kprobes long oops_begin(struct pt_regs *regs)
118 {
119 int cpu;
120 unsigned long flags;
121
122 if (debugger(regs))
123 return 1;
124
125 oops_enter();
126
127 /* racy, but better than risking deadlock. */
128 raw_local_irq_save(flags);
129 cpu = smp_processor_id();
130 if (!arch_spin_trylock(&die_lock)) {
131 if (cpu == die_owner)
132 /* nested oops. should stop eventually */;
133 else
134 arch_spin_lock(&die_lock);
135 }
136 die_nest_count++;
137 die_owner = cpu;
138 console_verbose();
139 bust_spinlocks(1);
140 if (machine_is(powermac))
141 pmac_backlight_unblank();
142 return flags;
143 }
144
oops_end(unsigned long flags,struct pt_regs * regs,int signr)145 static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs,
146 int signr)
147 {
148 bust_spinlocks(0);
149 die_owner = -1;
150 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
151 die_nest_count--;
152 oops_exit();
153 printk("\n");
154 if (!die_nest_count)
155 /* Nest count reaches zero, release the lock. */
156 arch_spin_unlock(&die_lock);
157 raw_local_irq_restore(flags);
158
159 crash_fadump(regs, "die oops");
160
161 /*
162 * A system reset (0x100) is a request to dump, so we always send
163 * it through the crashdump code.
164 */
165 if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) {
166 crash_kexec(regs);
167
168 /*
169 * We aren't the primary crash CPU. We need to send it
170 * to a holding pattern to avoid it ending up in the panic
171 * code.
172 */
173 crash_kexec_secondary(regs);
174 }
175
176 if (!signr)
177 return;
178
179 /*
180 * While our oops output is serialised by a spinlock, output
181 * from panic() called below can race and corrupt it. If we
182 * know we are going to panic, delay for 1 second so we have a
183 * chance to get clean backtraces from all CPUs that are oopsing.
184 */
185 if (in_interrupt() || panic_on_oops || !current->pid ||
186 is_global_init(current)) {
187 mdelay(MSEC_PER_SEC);
188 }
189
190 if (in_interrupt())
191 panic("Fatal exception in interrupt");
192 if (panic_on_oops)
193 panic("Fatal exception");
194 do_exit(signr);
195 }
196
__die(const char * str,struct pt_regs * regs,long err)197 static int __kprobes __die(const char *str, struct pt_regs *regs, long err)
198 {
199 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
200 #ifdef CONFIG_PREEMPT
201 printk("PREEMPT ");
202 #endif
203 #ifdef CONFIG_SMP
204 printk("SMP NR_CPUS=%d ", NR_CPUS);
205 #endif
206 #ifdef CONFIG_DEBUG_PAGEALLOC
207 printk("DEBUG_PAGEALLOC ");
208 #endif
209 #ifdef CONFIG_NUMA
210 printk("NUMA ");
211 #endif
212 printk("%s\n", ppc_md.name ? ppc_md.name : "");
213
214 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
215 return 1;
216
217 print_modules();
218 show_regs(regs);
219
220 return 0;
221 }
222
die(const char * str,struct pt_regs * regs,long err)223 void die(const char *str, struct pt_regs *regs, long err)
224 {
225 unsigned long flags = oops_begin(regs);
226
227 if (__die(str, regs, err))
228 err = 0;
229 oops_end(flags, regs, err);
230 }
231
user_single_step_siginfo(struct task_struct * tsk,struct pt_regs * regs,siginfo_t * info)232 void user_single_step_siginfo(struct task_struct *tsk,
233 struct pt_regs *regs, siginfo_t *info)
234 {
235 memset(info, 0, sizeof(*info));
236 info->si_signo = SIGTRAP;
237 info->si_code = TRAP_TRACE;
238 info->si_addr = (void __user *)regs->nip;
239 }
240
_exception(int signr,struct pt_regs * regs,int code,unsigned long addr)241 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
242 {
243 siginfo_t info;
244 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
245 "at %08lx nip %08lx lr %08lx code %x\n";
246 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
247 "at %016lx nip %016lx lr %016lx code %x\n";
248
249 if (!user_mode(regs)) {
250 die("Exception in kernel mode", regs, signr);
251 return;
252 }
253
254 if (show_unhandled_signals && unhandled_signal(current, signr)) {
255 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
256 current->comm, current->pid, signr,
257 addr, regs->nip, regs->link, code);
258 }
259
260 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
261 local_irq_enable();
262
263 current->thread.trap_nr = code;
264 memset(&info, 0, sizeof(info));
265 info.si_signo = signr;
266 info.si_code = code;
267 info.si_addr = (void __user *) addr;
268 force_sig_info(signr, &info, current);
269 }
270
271 #ifdef CONFIG_PPC64
system_reset_exception(struct pt_regs * regs)272 void system_reset_exception(struct pt_regs *regs)
273 {
274 /* See if any machine dependent calls */
275 if (ppc_md.system_reset_exception) {
276 if (ppc_md.system_reset_exception(regs))
277 return;
278 }
279
280 die("System Reset", regs, SIGABRT);
281
282 /* Must die if the interrupt is not recoverable */
283 if (!(regs->msr & MSR_RI))
284 panic("Unrecoverable System Reset");
285
286 /* What should we do here? We could issue a shutdown or hard reset. */
287 }
288
289 /*
290 * This function is called in real mode. Strictly no printk's please.
291 *
292 * regs->nip and regs->msr contains srr0 and ssr1.
293 */
machine_check_early(struct pt_regs * regs)294 long machine_check_early(struct pt_regs *regs)
295 {
296 long handled = 0;
297
298 __this_cpu_inc(irq_stat.mce_exceptions);
299
300 if (cur_cpu_spec && cur_cpu_spec->machine_check_early)
301 handled = cur_cpu_spec->machine_check_early(regs);
302 return handled;
303 }
304
hmi_exception_realmode(struct pt_regs * regs)305 long hmi_exception_realmode(struct pt_regs *regs)
306 {
307 __this_cpu_inc(irq_stat.hmi_exceptions);
308
309 if (ppc_md.hmi_exception_early)
310 ppc_md.hmi_exception_early(regs);
311
312 return 0;
313 }
314
315 #endif
316
317 /*
318 * I/O accesses can cause machine checks on powermacs.
319 * Check if the NIP corresponds to the address of a sync
320 * instruction for which there is an entry in the exception
321 * table.
322 * Note that the 601 only takes a machine check on TEA
323 * (transfer error ack) signal assertion, and does not
324 * set any of the top 16 bits of SRR1.
325 * -- paulus.
326 */
check_io_access(struct pt_regs * regs)327 static inline int check_io_access(struct pt_regs *regs)
328 {
329 #ifdef CONFIG_PPC32
330 unsigned long msr = regs->msr;
331 const struct exception_table_entry *entry;
332 unsigned int *nip = (unsigned int *)regs->nip;
333
334 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
335 && (entry = search_exception_tables(regs->nip)) != NULL) {
336 /*
337 * Check that it's a sync instruction, or somewhere
338 * in the twi; isync; nop sequence that inb/inw/inl uses.
339 * As the address is in the exception table
340 * we should be able to read the instr there.
341 * For the debug message, we look at the preceding
342 * load or store.
343 */
344 if (*nip == 0x60000000) /* nop */
345 nip -= 2;
346 else if (*nip == 0x4c00012c) /* isync */
347 --nip;
348 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
349 /* sync or twi */
350 unsigned int rb;
351
352 --nip;
353 rb = (*nip >> 11) & 0x1f;
354 printk(KERN_DEBUG "%s bad port %lx at %p\n",
355 (*nip & 0x100)? "OUT to": "IN from",
356 regs->gpr[rb] - _IO_BASE, nip);
357 regs->msr |= MSR_RI;
358 regs->nip = entry->fixup;
359 return 1;
360 }
361 }
362 #endif /* CONFIG_PPC32 */
363 return 0;
364 }
365
366 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
367 /* On 4xx, the reason for the machine check or program exception
368 is in the ESR. */
369 #define get_reason(regs) ((regs)->dsisr)
370 #ifndef CONFIG_FSL_BOOKE
371 #define get_mc_reason(regs) ((regs)->dsisr)
372 #else
373 #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
374 #endif
375 #define REASON_FP ESR_FP
376 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
377 #define REASON_PRIVILEGED ESR_PPR
378 #define REASON_TRAP ESR_PTR
379
380 /* single-step stuff */
381 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
382 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
383
384 #else
385 /* On non-4xx, the reason for the machine check or program
386 exception is in the MSR. */
387 #define get_reason(regs) ((regs)->msr)
388 #define get_mc_reason(regs) ((regs)->msr)
389 #define REASON_TM 0x200000
390 #define REASON_FP 0x100000
391 #define REASON_ILLEGAL 0x80000
392 #define REASON_PRIVILEGED 0x40000
393 #define REASON_TRAP 0x20000
394
395 #define single_stepping(regs) ((regs)->msr & MSR_SE)
396 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
397 #endif
398
399 #if defined(CONFIG_4xx)
machine_check_4xx(struct pt_regs * regs)400 int machine_check_4xx(struct pt_regs *regs)
401 {
402 unsigned long reason = get_mc_reason(regs);
403
404 if (reason & ESR_IMCP) {
405 printk("Instruction");
406 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
407 } else
408 printk("Data");
409 printk(" machine check in kernel mode.\n");
410
411 return 0;
412 }
413
machine_check_440A(struct pt_regs * regs)414 int machine_check_440A(struct pt_regs *regs)
415 {
416 unsigned long reason = get_mc_reason(regs);
417
418 printk("Machine check in kernel mode.\n");
419 if (reason & ESR_IMCP){
420 printk("Instruction Synchronous Machine Check exception\n");
421 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
422 }
423 else {
424 u32 mcsr = mfspr(SPRN_MCSR);
425 if (mcsr & MCSR_IB)
426 printk("Instruction Read PLB Error\n");
427 if (mcsr & MCSR_DRB)
428 printk("Data Read PLB Error\n");
429 if (mcsr & MCSR_DWB)
430 printk("Data Write PLB Error\n");
431 if (mcsr & MCSR_TLBP)
432 printk("TLB Parity Error\n");
433 if (mcsr & MCSR_ICP){
434 flush_instruction_cache();
435 printk("I-Cache Parity Error\n");
436 }
437 if (mcsr & MCSR_DCSP)
438 printk("D-Cache Search Parity Error\n");
439 if (mcsr & MCSR_DCFP)
440 printk("D-Cache Flush Parity Error\n");
441 if (mcsr & MCSR_IMPE)
442 printk("Machine Check exception is imprecise\n");
443
444 /* Clear MCSR */
445 mtspr(SPRN_MCSR, mcsr);
446 }
447 return 0;
448 }
449
machine_check_47x(struct pt_regs * regs)450 int machine_check_47x(struct pt_regs *regs)
451 {
452 unsigned long reason = get_mc_reason(regs);
453 u32 mcsr;
454
455 printk(KERN_ERR "Machine check in kernel mode.\n");
456 if (reason & ESR_IMCP) {
457 printk(KERN_ERR
458 "Instruction Synchronous Machine Check exception\n");
459 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
460 return 0;
461 }
462 mcsr = mfspr(SPRN_MCSR);
463 if (mcsr & MCSR_IB)
464 printk(KERN_ERR "Instruction Read PLB Error\n");
465 if (mcsr & MCSR_DRB)
466 printk(KERN_ERR "Data Read PLB Error\n");
467 if (mcsr & MCSR_DWB)
468 printk(KERN_ERR "Data Write PLB Error\n");
469 if (mcsr & MCSR_TLBP)
470 printk(KERN_ERR "TLB Parity Error\n");
471 if (mcsr & MCSR_ICP) {
472 flush_instruction_cache();
473 printk(KERN_ERR "I-Cache Parity Error\n");
474 }
475 if (mcsr & MCSR_DCSP)
476 printk(KERN_ERR "D-Cache Search Parity Error\n");
477 if (mcsr & PPC47x_MCSR_GPR)
478 printk(KERN_ERR "GPR Parity Error\n");
479 if (mcsr & PPC47x_MCSR_FPR)
480 printk(KERN_ERR "FPR Parity Error\n");
481 if (mcsr & PPC47x_MCSR_IPR)
482 printk(KERN_ERR "Machine Check exception is imprecise\n");
483
484 /* Clear MCSR */
485 mtspr(SPRN_MCSR, mcsr);
486
487 return 0;
488 }
489 #elif defined(CONFIG_E500)
machine_check_e500mc(struct pt_regs * regs)490 int machine_check_e500mc(struct pt_regs *regs)
491 {
492 unsigned long mcsr = mfspr(SPRN_MCSR);
493 unsigned long reason = mcsr;
494 int recoverable = 1;
495
496 if (reason & MCSR_LD) {
497 recoverable = fsl_rio_mcheck_exception(regs);
498 if (recoverable == 1)
499 goto silent_out;
500 }
501
502 printk("Machine check in kernel mode.\n");
503 printk("Caused by (from MCSR=%lx): ", reason);
504
505 if (reason & MCSR_MCP)
506 printk("Machine Check Signal\n");
507
508 if (reason & MCSR_ICPERR) {
509 printk("Instruction Cache Parity Error\n");
510
511 /*
512 * This is recoverable by invalidating the i-cache.
513 */
514 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
515 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
516 ;
517
518 /*
519 * This will generally be accompanied by an instruction
520 * fetch error report -- only treat MCSR_IF as fatal
521 * if it wasn't due to an L1 parity error.
522 */
523 reason &= ~MCSR_IF;
524 }
525
526 if (reason & MCSR_DCPERR_MC) {
527 printk("Data Cache Parity Error\n");
528
529 /*
530 * In write shadow mode we auto-recover from the error, but it
531 * may still get logged and cause a machine check. We should
532 * only treat the non-write shadow case as non-recoverable.
533 */
534 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
535 recoverable = 0;
536 }
537
538 if (reason & MCSR_L2MMU_MHIT) {
539 printk("Hit on multiple TLB entries\n");
540 recoverable = 0;
541 }
542
543 if (reason & MCSR_NMI)
544 printk("Non-maskable interrupt\n");
545
546 if (reason & MCSR_IF) {
547 printk("Instruction Fetch Error Report\n");
548 recoverable = 0;
549 }
550
551 if (reason & MCSR_LD) {
552 printk("Load Error Report\n");
553 recoverable = 0;
554 }
555
556 if (reason & MCSR_ST) {
557 printk("Store Error Report\n");
558 recoverable = 0;
559 }
560
561 if (reason & MCSR_LDG) {
562 printk("Guarded Load Error Report\n");
563 recoverable = 0;
564 }
565
566 if (reason & MCSR_TLBSYNC)
567 printk("Simultaneous tlbsync operations\n");
568
569 if (reason & MCSR_BSL2_ERR) {
570 printk("Level 2 Cache Error\n");
571 recoverable = 0;
572 }
573
574 if (reason & MCSR_MAV) {
575 u64 addr;
576
577 addr = mfspr(SPRN_MCAR);
578 addr |= (u64)mfspr(SPRN_MCARU) << 32;
579
580 printk("Machine Check %s Address: %#llx\n",
581 reason & MCSR_MEA ? "Effective" : "Physical", addr);
582 }
583
584 silent_out:
585 mtspr(SPRN_MCSR, mcsr);
586 return mfspr(SPRN_MCSR) == 0 && recoverable;
587 }
588
machine_check_e500(struct pt_regs * regs)589 int machine_check_e500(struct pt_regs *regs)
590 {
591 unsigned long reason = get_mc_reason(regs);
592
593 if (reason & MCSR_BUS_RBERR) {
594 if (fsl_rio_mcheck_exception(regs))
595 return 1;
596 if (fsl_pci_mcheck_exception(regs))
597 return 1;
598 }
599
600 printk("Machine check in kernel mode.\n");
601 printk("Caused by (from MCSR=%lx): ", reason);
602
603 if (reason & MCSR_MCP)
604 printk("Machine Check Signal\n");
605 if (reason & MCSR_ICPERR)
606 printk("Instruction Cache Parity Error\n");
607 if (reason & MCSR_DCP_PERR)
608 printk("Data Cache Push Parity Error\n");
609 if (reason & MCSR_DCPERR)
610 printk("Data Cache Parity Error\n");
611 if (reason & MCSR_BUS_IAERR)
612 printk("Bus - Instruction Address Error\n");
613 if (reason & MCSR_BUS_RAERR)
614 printk("Bus - Read Address Error\n");
615 if (reason & MCSR_BUS_WAERR)
616 printk("Bus - Write Address Error\n");
617 if (reason & MCSR_BUS_IBERR)
618 printk("Bus - Instruction Data Error\n");
619 if (reason & MCSR_BUS_RBERR)
620 printk("Bus - Read Data Bus Error\n");
621 if (reason & MCSR_BUS_WBERR)
622 printk("Bus - Write Data Bus Error\n");
623 if (reason & MCSR_BUS_IPERR)
624 printk("Bus - Instruction Parity Error\n");
625 if (reason & MCSR_BUS_RPERR)
626 printk("Bus - Read Parity Error\n");
627
628 return 0;
629 }
630
machine_check_generic(struct pt_regs * regs)631 int machine_check_generic(struct pt_regs *regs)
632 {
633 return 0;
634 }
635 #elif defined(CONFIG_E200)
machine_check_e200(struct pt_regs * regs)636 int machine_check_e200(struct pt_regs *regs)
637 {
638 unsigned long reason = get_mc_reason(regs);
639
640 printk("Machine check in kernel mode.\n");
641 printk("Caused by (from MCSR=%lx): ", reason);
642
643 if (reason & MCSR_MCP)
644 printk("Machine Check Signal\n");
645 if (reason & MCSR_CP_PERR)
646 printk("Cache Push Parity Error\n");
647 if (reason & MCSR_CPERR)
648 printk("Cache Parity Error\n");
649 if (reason & MCSR_EXCP_ERR)
650 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
651 if (reason & MCSR_BUS_IRERR)
652 printk("Bus - Read Bus Error on instruction fetch\n");
653 if (reason & MCSR_BUS_DRERR)
654 printk("Bus - Read Bus Error on data load\n");
655 if (reason & MCSR_BUS_WRERR)
656 printk("Bus - Write Bus Error on buffered store or cache line push\n");
657
658 return 0;
659 }
660 #else
machine_check_generic(struct pt_regs * regs)661 int machine_check_generic(struct pt_regs *regs)
662 {
663 unsigned long reason = get_mc_reason(regs);
664
665 printk("Machine check in kernel mode.\n");
666 printk("Caused by (from SRR1=%lx): ", reason);
667 switch (reason & 0x601F0000) {
668 case 0x80000:
669 printk("Machine check signal\n");
670 break;
671 case 0: /* for 601 */
672 case 0x40000:
673 case 0x140000: /* 7450 MSS error and TEA */
674 printk("Transfer error ack signal\n");
675 break;
676 case 0x20000:
677 printk("Data parity error signal\n");
678 break;
679 case 0x10000:
680 printk("Address parity error signal\n");
681 break;
682 case 0x20000000:
683 printk("L1 Data Cache error\n");
684 break;
685 case 0x40000000:
686 printk("L1 Instruction Cache error\n");
687 break;
688 case 0x00100000:
689 printk("L2 data cache parity error\n");
690 break;
691 default:
692 printk("Unknown values in msr\n");
693 }
694 return 0;
695 }
696 #endif /* everything else */
697
machine_check_exception(struct pt_regs * regs)698 void machine_check_exception(struct pt_regs *regs)
699 {
700 enum ctx_state prev_state = exception_enter();
701 int recover = 0;
702
703 __this_cpu_inc(irq_stat.mce_exceptions);
704
705 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
706
707 /* See if any machine dependent calls. In theory, we would want
708 * to call the CPU first, and call the ppc_md. one if the CPU
709 * one returns a positive number. However there is existing code
710 * that assumes the board gets a first chance, so let's keep it
711 * that way for now and fix things later. --BenH.
712 */
713 if (ppc_md.machine_check_exception)
714 recover = ppc_md.machine_check_exception(regs);
715 else if (cur_cpu_spec->machine_check)
716 recover = cur_cpu_spec->machine_check(regs);
717
718 if (recover > 0)
719 goto bail;
720
721 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
722 /* the qspan pci read routines can cause machine checks -- Cort
723 *
724 * yuck !!! that totally needs to go away ! There are better ways
725 * to deal with that than having a wart in the mcheck handler.
726 * -- BenH
727 */
728 bad_page_fault(regs, regs->dar, SIGBUS);
729 goto bail;
730 #endif
731
732 if (debugger_fault_handler(regs))
733 goto bail;
734
735 if (check_io_access(regs))
736 goto bail;
737
738 die("Machine check", regs, SIGBUS);
739
740 /* Must die if the interrupt is not recoverable */
741 if (!(regs->msr & MSR_RI))
742 panic("Unrecoverable Machine check");
743
744 bail:
745 exception_exit(prev_state);
746 }
747
SMIException(struct pt_regs * regs)748 void SMIException(struct pt_regs *regs)
749 {
750 die("System Management Interrupt", regs, SIGABRT);
751 }
752
handle_hmi_exception(struct pt_regs * regs)753 void handle_hmi_exception(struct pt_regs *regs)
754 {
755 struct pt_regs *old_regs;
756
757 old_regs = set_irq_regs(regs);
758 irq_enter();
759
760 if (ppc_md.handle_hmi_exception)
761 ppc_md.handle_hmi_exception(regs);
762
763 irq_exit();
764 set_irq_regs(old_regs);
765 }
766
unknown_exception(struct pt_regs * regs)767 void unknown_exception(struct pt_regs *regs)
768 {
769 enum ctx_state prev_state = exception_enter();
770
771 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
772 regs->nip, regs->msr, regs->trap);
773
774 _exception(SIGTRAP, regs, 0, 0);
775
776 exception_exit(prev_state);
777 }
778
instruction_breakpoint_exception(struct pt_regs * regs)779 void instruction_breakpoint_exception(struct pt_regs *regs)
780 {
781 enum ctx_state prev_state = exception_enter();
782
783 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
784 5, SIGTRAP) == NOTIFY_STOP)
785 goto bail;
786 if (debugger_iabr_match(regs))
787 goto bail;
788 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
789
790 bail:
791 exception_exit(prev_state);
792 }
793
RunModeException(struct pt_regs * regs)794 void RunModeException(struct pt_regs *regs)
795 {
796 _exception(SIGTRAP, regs, 0, 0);
797 }
798
single_step_exception(struct pt_regs * regs)799 void __kprobes single_step_exception(struct pt_regs *regs)
800 {
801 enum ctx_state prev_state = exception_enter();
802
803 clear_single_step(regs);
804
805 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
806 5, SIGTRAP) == NOTIFY_STOP)
807 goto bail;
808 if (debugger_sstep(regs))
809 goto bail;
810
811 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
812
813 bail:
814 exception_exit(prev_state);
815 }
816
817 /*
818 * After we have successfully emulated an instruction, we have to
819 * check if the instruction was being single-stepped, and if so,
820 * pretend we got a single-step exception. This was pointed out
821 * by Kumar Gala. -- paulus
822 */
emulate_single_step(struct pt_regs * regs)823 static void emulate_single_step(struct pt_regs *regs)
824 {
825 if (single_stepping(regs))
826 single_step_exception(regs);
827 }
828
__parse_fpscr(unsigned long fpscr)829 static inline int __parse_fpscr(unsigned long fpscr)
830 {
831 int ret = 0;
832
833 /* Invalid operation */
834 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
835 ret = FPE_FLTINV;
836
837 /* Overflow */
838 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
839 ret = FPE_FLTOVF;
840
841 /* Underflow */
842 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
843 ret = FPE_FLTUND;
844
845 /* Divide by zero */
846 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
847 ret = FPE_FLTDIV;
848
849 /* Inexact result */
850 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
851 ret = FPE_FLTRES;
852
853 return ret;
854 }
855
parse_fpe(struct pt_regs * regs)856 static void parse_fpe(struct pt_regs *regs)
857 {
858 int code = 0;
859
860 flush_fp_to_thread(current);
861
862 code = __parse_fpscr(current->thread.fp_state.fpscr);
863
864 _exception(SIGFPE, regs, code, regs->nip);
865 }
866
867 /*
868 * Illegal instruction emulation support. Originally written to
869 * provide the PVR to user applications using the mfspr rd, PVR.
870 * Return non-zero if we can't emulate, or -EFAULT if the associated
871 * memory access caused an access fault. Return zero on success.
872 *
873 * There are a couple of ways to do this, either "decode" the instruction
874 * or directly match lots of bits. In this case, matching lots of
875 * bits is faster and easier.
876 *
877 */
emulate_string_inst(struct pt_regs * regs,u32 instword)878 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
879 {
880 u8 rT = (instword >> 21) & 0x1f;
881 u8 rA = (instword >> 16) & 0x1f;
882 u8 NB_RB = (instword >> 11) & 0x1f;
883 u32 num_bytes;
884 unsigned long EA;
885 int pos = 0;
886
887 /* Early out if we are an invalid form of lswx */
888 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
889 if ((rT == rA) || (rT == NB_RB))
890 return -EINVAL;
891
892 EA = (rA == 0) ? 0 : regs->gpr[rA];
893
894 switch (instword & PPC_INST_STRING_MASK) {
895 case PPC_INST_LSWX:
896 case PPC_INST_STSWX:
897 EA += NB_RB;
898 num_bytes = regs->xer & 0x7f;
899 break;
900 case PPC_INST_LSWI:
901 case PPC_INST_STSWI:
902 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
903 break;
904 default:
905 return -EINVAL;
906 }
907
908 while (num_bytes != 0)
909 {
910 u8 val;
911 u32 shift = 8 * (3 - (pos & 0x3));
912
913 /* if process is 32-bit, clear upper 32 bits of EA */
914 if ((regs->msr & MSR_64BIT) == 0)
915 EA &= 0xFFFFFFFF;
916
917 switch ((instword & PPC_INST_STRING_MASK)) {
918 case PPC_INST_LSWX:
919 case PPC_INST_LSWI:
920 if (get_user(val, (u8 __user *)EA))
921 return -EFAULT;
922 /* first time updating this reg,
923 * zero it out */
924 if (pos == 0)
925 regs->gpr[rT] = 0;
926 regs->gpr[rT] |= val << shift;
927 break;
928 case PPC_INST_STSWI:
929 case PPC_INST_STSWX:
930 val = regs->gpr[rT] >> shift;
931 if (put_user(val, (u8 __user *)EA))
932 return -EFAULT;
933 break;
934 }
935 /* move EA to next address */
936 EA += 1;
937 num_bytes--;
938
939 /* manage our position within the register */
940 if (++pos == 4) {
941 pos = 0;
942 if (++rT == 32)
943 rT = 0;
944 }
945 }
946
947 return 0;
948 }
949
emulate_popcntb_inst(struct pt_regs * regs,u32 instword)950 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
951 {
952 u32 ra,rs;
953 unsigned long tmp;
954
955 ra = (instword >> 16) & 0x1f;
956 rs = (instword >> 21) & 0x1f;
957
958 tmp = regs->gpr[rs];
959 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
960 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
961 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
962 regs->gpr[ra] = tmp;
963
964 return 0;
965 }
966
emulate_isel(struct pt_regs * regs,u32 instword)967 static int emulate_isel(struct pt_regs *regs, u32 instword)
968 {
969 u8 rT = (instword >> 21) & 0x1f;
970 u8 rA = (instword >> 16) & 0x1f;
971 u8 rB = (instword >> 11) & 0x1f;
972 u8 BC = (instword >> 6) & 0x1f;
973 u8 bit;
974 unsigned long tmp;
975
976 tmp = (rA == 0) ? 0 : regs->gpr[rA];
977 bit = (regs->ccr >> (31 - BC)) & 0x1;
978
979 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
980
981 return 0;
982 }
983
984 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
tm_abort_check(struct pt_regs * regs,int cause)985 static inline bool tm_abort_check(struct pt_regs *regs, int cause)
986 {
987 /* If we're emulating a load/store in an active transaction, we cannot
988 * emulate it as the kernel operates in transaction suspended context.
989 * We need to abort the transaction. This creates a persistent TM
990 * abort so tell the user what caused it with a new code.
991 */
992 if (MSR_TM_TRANSACTIONAL(regs->msr)) {
993 tm_enable();
994 tm_abort(cause);
995 return true;
996 }
997 return false;
998 }
999 #else
tm_abort_check(struct pt_regs * regs,int reason)1000 static inline bool tm_abort_check(struct pt_regs *regs, int reason)
1001 {
1002 return false;
1003 }
1004 #endif
1005
emulate_instruction(struct pt_regs * regs)1006 static int emulate_instruction(struct pt_regs *regs)
1007 {
1008 u32 instword;
1009 u32 rd;
1010
1011 if (!user_mode(regs))
1012 return -EINVAL;
1013 CHECK_FULL_REGS(regs);
1014
1015 if (get_user(instword, (u32 __user *)(regs->nip)))
1016 return -EFAULT;
1017
1018 /* Emulate the mfspr rD, PVR. */
1019 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
1020 PPC_WARN_EMULATED(mfpvr, regs);
1021 rd = (instword >> 21) & 0x1f;
1022 regs->gpr[rd] = mfspr(SPRN_PVR);
1023 return 0;
1024 }
1025
1026 /* Emulating the dcba insn is just a no-op. */
1027 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
1028 PPC_WARN_EMULATED(dcba, regs);
1029 return 0;
1030 }
1031
1032 /* Emulate the mcrxr insn. */
1033 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
1034 int shift = (instword >> 21) & 0x1c;
1035 unsigned long msk = 0xf0000000UL >> shift;
1036
1037 PPC_WARN_EMULATED(mcrxr, regs);
1038 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
1039 regs->xer &= ~0xf0000000UL;
1040 return 0;
1041 }
1042
1043 /* Emulate load/store string insn. */
1044 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
1045 if (tm_abort_check(regs,
1046 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
1047 return -EINVAL;
1048 PPC_WARN_EMULATED(string, regs);
1049 return emulate_string_inst(regs, instword);
1050 }
1051
1052 /* Emulate the popcntb (Population Count Bytes) instruction. */
1053 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
1054 PPC_WARN_EMULATED(popcntb, regs);
1055 return emulate_popcntb_inst(regs, instword);
1056 }
1057
1058 /* Emulate isel (Integer Select) instruction */
1059 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
1060 PPC_WARN_EMULATED(isel, regs);
1061 return emulate_isel(regs, instword);
1062 }
1063
1064 /* Emulate sync instruction variants */
1065 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) {
1066 PPC_WARN_EMULATED(sync, regs);
1067 asm volatile("sync");
1068 return 0;
1069 }
1070
1071 #ifdef CONFIG_PPC64
1072 /* Emulate the mfspr rD, DSCR. */
1073 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
1074 PPC_INST_MFSPR_DSCR_USER) ||
1075 ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
1076 PPC_INST_MFSPR_DSCR)) &&
1077 cpu_has_feature(CPU_FTR_DSCR)) {
1078 PPC_WARN_EMULATED(mfdscr, regs);
1079 rd = (instword >> 21) & 0x1f;
1080 regs->gpr[rd] = mfspr(SPRN_DSCR);
1081 return 0;
1082 }
1083 /* Emulate the mtspr DSCR, rD. */
1084 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
1085 PPC_INST_MTSPR_DSCR_USER) ||
1086 ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
1087 PPC_INST_MTSPR_DSCR)) &&
1088 cpu_has_feature(CPU_FTR_DSCR)) {
1089 PPC_WARN_EMULATED(mtdscr, regs);
1090 rd = (instword >> 21) & 0x1f;
1091 current->thread.dscr = regs->gpr[rd];
1092 current->thread.dscr_inherit = 1;
1093 mtspr(SPRN_DSCR, current->thread.dscr);
1094 return 0;
1095 }
1096 #endif
1097
1098 return -EINVAL;
1099 }
1100
is_valid_bugaddr(unsigned long addr)1101 int is_valid_bugaddr(unsigned long addr)
1102 {
1103 return is_kernel_addr(addr);
1104 }
1105
1106 #ifdef CONFIG_MATH_EMULATION
emulate_math(struct pt_regs * regs)1107 static int emulate_math(struct pt_regs *regs)
1108 {
1109 int ret;
1110 extern int do_mathemu(struct pt_regs *regs);
1111
1112 ret = do_mathemu(regs);
1113 if (ret >= 0)
1114 PPC_WARN_EMULATED(math, regs);
1115
1116 switch (ret) {
1117 case 0:
1118 emulate_single_step(regs);
1119 return 0;
1120 case 1: {
1121 int code = 0;
1122 code = __parse_fpscr(current->thread.fp_state.fpscr);
1123 _exception(SIGFPE, regs, code, regs->nip);
1124 return 0;
1125 }
1126 case -EFAULT:
1127 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1128 return 0;
1129 }
1130
1131 return -1;
1132 }
1133 #else
emulate_math(struct pt_regs * regs)1134 static inline int emulate_math(struct pt_regs *regs) { return -1; }
1135 #endif
1136
program_check_exception(struct pt_regs * regs)1137 void __kprobes program_check_exception(struct pt_regs *regs)
1138 {
1139 enum ctx_state prev_state = exception_enter();
1140 unsigned int reason = get_reason(regs);
1141
1142 /* We can now get here via a FP Unavailable exception if the core
1143 * has no FPU, in that case the reason flags will be 0 */
1144
1145 if (reason & REASON_FP) {
1146 /* IEEE FP exception */
1147 parse_fpe(regs);
1148 goto bail;
1149 }
1150 if (reason & REASON_TRAP) {
1151 /* Debugger is first in line to stop recursive faults in
1152 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1153 if (debugger_bpt(regs))
1154 goto bail;
1155
1156 /* trap exception */
1157 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1158 == NOTIFY_STOP)
1159 goto bail;
1160
1161 if (!(regs->msr & MSR_PR) && /* not user-mode */
1162 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
1163 regs->nip += 4;
1164 goto bail;
1165 }
1166 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1167 goto bail;
1168 }
1169 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1170 if (reason & REASON_TM) {
1171 /* This is a TM "Bad Thing Exception" program check.
1172 * This occurs when:
1173 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1174 * transition in TM states.
1175 * - A trechkpt is attempted when transactional.
1176 * - A treclaim is attempted when non transactional.
1177 * - A tend is illegally attempted.
1178 * - writing a TM SPR when transactional.
1179 */
1180 if (!user_mode(regs) &&
1181 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
1182 regs->nip += 4;
1183 goto bail;
1184 }
1185 /* If usermode caused this, it's done something illegal and
1186 * gets a SIGILL slap on the wrist. We call it an illegal
1187 * operand to distinguish from the instruction just being bad
1188 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1189 * illegal /placement/ of a valid instruction.
1190 */
1191 if (user_mode(regs)) {
1192 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1193 goto bail;
1194 } else {
1195 printk(KERN_EMERG "Unexpected TM Bad Thing exception "
1196 "at %lx (msr 0x%x)\n", regs->nip, reason);
1197 die("Unrecoverable exception", regs, SIGABRT);
1198 }
1199 }
1200 #endif
1201
1202 /*
1203 * If we took the program check in the kernel skip down to sending a
1204 * SIGILL. The subsequent cases all relate to emulating instructions
1205 * which we should only do for userspace. We also do not want to enable
1206 * interrupts for kernel faults because that might lead to further
1207 * faults, and loose the context of the original exception.
1208 */
1209 if (!user_mode(regs))
1210 goto sigill;
1211
1212 /* We restore the interrupt state now */
1213 if (!arch_irq_disabled_regs(regs))
1214 local_irq_enable();
1215
1216 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1217 * but there seems to be a hardware bug on the 405GP (RevD)
1218 * that means ESR is sometimes set incorrectly - either to
1219 * ESR_DST (!?) or 0. In the process of chasing this with the
1220 * hardware people - not sure if it can happen on any illegal
1221 * instruction or only on FP instructions, whether there is a
1222 * pattern to occurrences etc. -dgibson 31/Mar/2003
1223 */
1224 if (!emulate_math(regs))
1225 goto bail;
1226
1227 /* Try to emulate it if we should. */
1228 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1229 switch (emulate_instruction(regs)) {
1230 case 0:
1231 regs->nip += 4;
1232 emulate_single_step(regs);
1233 goto bail;
1234 case -EFAULT:
1235 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1236 goto bail;
1237 }
1238 }
1239
1240 sigill:
1241 if (reason & REASON_PRIVILEGED)
1242 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1243 else
1244 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1245
1246 bail:
1247 exception_exit(prev_state);
1248 }
1249
1250 /*
1251 * This occurs when running in hypervisor mode on POWER6 or later
1252 * and an illegal instruction is encountered.
1253 */
emulation_assist_interrupt(struct pt_regs * regs)1254 void __kprobes emulation_assist_interrupt(struct pt_regs *regs)
1255 {
1256 regs->msr |= REASON_ILLEGAL;
1257 program_check_exception(regs);
1258 }
1259
alignment_exception(struct pt_regs * regs)1260 void alignment_exception(struct pt_regs *regs)
1261 {
1262 enum ctx_state prev_state = exception_enter();
1263 int sig, code, fixed = 0;
1264
1265 /* We restore the interrupt state now */
1266 if (!arch_irq_disabled_regs(regs))
1267 local_irq_enable();
1268
1269 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
1270 goto bail;
1271
1272 /* we don't implement logging of alignment exceptions */
1273 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1274 fixed = fix_alignment(regs);
1275
1276 if (fixed == 1) {
1277 regs->nip += 4; /* skip over emulated instruction */
1278 emulate_single_step(regs);
1279 goto bail;
1280 }
1281
1282 /* Operand address was bad */
1283 if (fixed == -EFAULT) {
1284 sig = SIGSEGV;
1285 code = SEGV_ACCERR;
1286 } else {
1287 sig = SIGBUS;
1288 code = BUS_ADRALN;
1289 }
1290 if (user_mode(regs))
1291 _exception(sig, regs, code, regs->dar);
1292 else
1293 bad_page_fault(regs, regs->dar, sig);
1294
1295 bail:
1296 exception_exit(prev_state);
1297 }
1298
StackOverflow(struct pt_regs * regs)1299 void StackOverflow(struct pt_regs *regs)
1300 {
1301 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
1302 current, regs->gpr[1]);
1303 debugger(regs);
1304 show_regs(regs);
1305 panic("kernel stack overflow");
1306 }
1307
nonrecoverable_exception(struct pt_regs * regs)1308 void nonrecoverable_exception(struct pt_regs *regs)
1309 {
1310 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
1311 regs->nip, regs->msr);
1312 debugger(regs);
1313 die("nonrecoverable exception", regs, SIGKILL);
1314 }
1315
trace_syscall(struct pt_regs * regs)1316 void trace_syscall(struct pt_regs *regs)
1317 {
1318 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
1319 current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0],
1320 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
1321 }
1322
kernel_fp_unavailable_exception(struct pt_regs * regs)1323 void kernel_fp_unavailable_exception(struct pt_regs *regs)
1324 {
1325 enum ctx_state prev_state = exception_enter();
1326
1327 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1328 "%lx at %lx\n", regs->trap, regs->nip);
1329 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1330
1331 exception_exit(prev_state);
1332 }
1333
altivec_unavailable_exception(struct pt_regs * regs)1334 void altivec_unavailable_exception(struct pt_regs *regs)
1335 {
1336 enum ctx_state prev_state = exception_enter();
1337
1338 if (user_mode(regs)) {
1339 /* A user program has executed an altivec instruction,
1340 but this kernel doesn't support altivec. */
1341 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1342 goto bail;
1343 }
1344
1345 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1346 "%lx at %lx\n", regs->trap, regs->nip);
1347 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1348
1349 bail:
1350 exception_exit(prev_state);
1351 }
1352
vsx_unavailable_exception(struct pt_regs * regs)1353 void vsx_unavailable_exception(struct pt_regs *regs)
1354 {
1355 if (user_mode(regs)) {
1356 /* A user program has executed an vsx instruction,
1357 but this kernel doesn't support vsx. */
1358 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1359 return;
1360 }
1361
1362 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1363 "%lx at %lx\n", regs->trap, regs->nip);
1364 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1365 }
1366
1367 #ifdef CONFIG_PPC64
facility_unavailable_exception(struct pt_regs * regs)1368 void facility_unavailable_exception(struct pt_regs *regs)
1369 {
1370 static char *facility_strings[] = {
1371 [FSCR_FP_LG] = "FPU",
1372 [FSCR_VECVSX_LG] = "VMX/VSX",
1373 [FSCR_DSCR_LG] = "DSCR",
1374 [FSCR_PM_LG] = "PMU SPRs",
1375 [FSCR_BHRB_LG] = "BHRB",
1376 [FSCR_TM_LG] = "TM",
1377 [FSCR_EBB_LG] = "EBB",
1378 [FSCR_TAR_LG] = "TAR",
1379 };
1380 char *facility = "unknown";
1381 u64 value;
1382 u32 instword, rd;
1383 u8 status;
1384 bool hv;
1385
1386 hv = (regs->trap == 0xf80);
1387 if (hv)
1388 value = mfspr(SPRN_HFSCR);
1389 else
1390 value = mfspr(SPRN_FSCR);
1391
1392 status = value >> 56;
1393 if (status == FSCR_DSCR_LG) {
1394 /*
1395 * User is accessing the DSCR register using the problem
1396 * state only SPR number (0x03) either through a mfspr or
1397 * a mtspr instruction. If it is a write attempt through
1398 * a mtspr, then we set the inherit bit. This also allows
1399 * the user to write or read the register directly in the
1400 * future by setting via the FSCR DSCR bit. But in case it
1401 * is a read DSCR attempt through a mfspr instruction, we
1402 * just emulate the instruction instead. This code path will
1403 * always emulate all the mfspr instructions till the user
1404 * has attempted atleast one mtspr instruction. This way it
1405 * preserves the same behaviour when the user is accessing
1406 * the DSCR through privilege level only SPR number (0x11)
1407 * which is emulated through illegal instruction exception.
1408 * We always leave HFSCR DSCR set.
1409 */
1410 if (get_user(instword, (u32 __user *)(regs->nip))) {
1411 pr_err("Failed to fetch the user instruction\n");
1412 return;
1413 }
1414
1415 /* Write into DSCR (mtspr 0x03, RS) */
1416 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK)
1417 == PPC_INST_MTSPR_DSCR_USER) {
1418 rd = (instword >> 21) & 0x1f;
1419 current->thread.dscr = regs->gpr[rd];
1420 current->thread.dscr_inherit = 1;
1421 mtspr(SPRN_FSCR, value | FSCR_DSCR);
1422 }
1423
1424 /* Read from DSCR (mfspr RT, 0x03) */
1425 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK)
1426 == PPC_INST_MFSPR_DSCR_USER) {
1427 if (emulate_instruction(regs)) {
1428 pr_err("DSCR based mfspr emulation failed\n");
1429 return;
1430 }
1431 regs->nip += 4;
1432 emulate_single_step(regs);
1433 }
1434 return;
1435 }
1436
1437 if ((status < ARRAY_SIZE(facility_strings)) &&
1438 facility_strings[status])
1439 facility = facility_strings[status];
1440
1441 /* We restore the interrupt state now */
1442 if (!arch_irq_disabled_regs(regs))
1443 local_irq_enable();
1444
1445 pr_err_ratelimited(
1446 "%sFacility '%s' unavailable, exception at 0x%lx, MSR=%lx\n",
1447 hv ? "Hypervisor " : "", facility, regs->nip, regs->msr);
1448
1449 if (user_mode(regs)) {
1450 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1451 return;
1452 }
1453
1454 die("Unexpected facility unavailable exception", regs, SIGABRT);
1455 }
1456 #endif
1457
1458 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1459
fp_unavailable_tm(struct pt_regs * regs)1460 void fp_unavailable_tm(struct pt_regs *regs)
1461 {
1462 /* Note: This does not handle any kind of FP laziness. */
1463
1464 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1465 regs->nip, regs->msr);
1466
1467 /* We can only have got here if the task started using FP after
1468 * beginning the transaction. So, the transactional regs are just a
1469 * copy of the checkpointed ones. But, we still need to recheckpoint
1470 * as we're enabling FP for the process; it will return, abort the
1471 * transaction, and probably retry but now with FP enabled. So the
1472 * checkpointed FP registers need to be loaded.
1473 */
1474 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1475 /* Reclaim didn't save out any FPRs to transact_fprs. */
1476
1477 /* Enable FP for the task: */
1478 regs->msr |= (MSR_FP | current->thread.fpexc_mode);
1479
1480 /* This loads and recheckpoints the FP registers from
1481 * thread.fpr[]. They will remain in registers after the
1482 * checkpoint so we don't need to reload them after.
1483 * If VMX is in use, the VRs now hold checkpointed values,
1484 * so we don't want to load the VRs from the thread_struct.
1485 */
1486 tm_recheckpoint(¤t->thread, MSR_FP);
1487
1488 /* If VMX is in use, get the transactional values back */
1489 if (regs->msr & MSR_VEC) {
1490 do_load_up_transact_altivec(¤t->thread);
1491 /* At this point all the VSX state is loaded, so enable it */
1492 regs->msr |= MSR_VSX;
1493 }
1494 }
1495
altivec_unavailable_tm(struct pt_regs * regs)1496 void altivec_unavailable_tm(struct pt_regs *regs)
1497 {
1498 /* See the comments in fp_unavailable_tm(). This function operates
1499 * the same way.
1500 */
1501
1502 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1503 "MSR=%lx\n",
1504 regs->nip, regs->msr);
1505 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1506 regs->msr |= MSR_VEC;
1507 tm_recheckpoint(¤t->thread, MSR_VEC);
1508 current->thread.used_vr = 1;
1509
1510 if (regs->msr & MSR_FP) {
1511 do_load_up_transact_fpu(¤t->thread);
1512 regs->msr |= MSR_VSX;
1513 }
1514 }
1515
vsx_unavailable_tm(struct pt_regs * regs)1516 void vsx_unavailable_tm(struct pt_regs *regs)
1517 {
1518 unsigned long orig_msr = regs->msr;
1519
1520 /* See the comments in fp_unavailable_tm(). This works similarly,
1521 * though we're loading both FP and VEC registers in here.
1522 *
1523 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1524 * regs. Either way, set MSR_VSX.
1525 */
1526
1527 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1528 "MSR=%lx\n",
1529 regs->nip, regs->msr);
1530
1531 current->thread.used_vsr = 1;
1532
1533 /* If FP and VMX are already loaded, we have all the state we need */
1534 if ((orig_msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC)) {
1535 regs->msr |= MSR_VSX;
1536 return;
1537 }
1538
1539 /* This reclaims FP and/or VR regs if they're already enabled */
1540 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1541
1542 regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode |
1543 MSR_VSX;
1544
1545 /* This loads & recheckpoints FP and VRs; but we have
1546 * to be sure not to overwrite previously-valid state.
1547 */
1548 tm_recheckpoint(¤t->thread, regs->msr & ~orig_msr);
1549
1550 if (orig_msr & MSR_FP)
1551 do_load_up_transact_fpu(¤t->thread);
1552 if (orig_msr & MSR_VEC)
1553 do_load_up_transact_altivec(¤t->thread);
1554 }
1555 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1556
performance_monitor_exception(struct pt_regs * regs)1557 void performance_monitor_exception(struct pt_regs *regs)
1558 {
1559 __this_cpu_inc(irq_stat.pmu_irqs);
1560
1561 perf_irq(regs);
1562 }
1563
1564 #ifdef CONFIG_8xx
SoftwareEmulation(struct pt_regs * regs)1565 void SoftwareEmulation(struct pt_regs *regs)
1566 {
1567 CHECK_FULL_REGS(regs);
1568
1569 if (!user_mode(regs)) {
1570 debugger(regs);
1571 die("Kernel Mode Unimplemented Instruction or SW FPU Emulation",
1572 regs, SIGFPE);
1573 }
1574
1575 if (!emulate_math(regs))
1576 return;
1577
1578 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1579 }
1580 #endif /* CONFIG_8xx */
1581
1582 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
handle_debug(struct pt_regs * regs,unsigned long debug_status)1583 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1584 {
1585 int changed = 0;
1586 /*
1587 * Determine the cause of the debug event, clear the
1588 * event flags and send a trap to the handler. Torez
1589 */
1590 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1591 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1592 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1593 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
1594 #endif
1595 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
1596 5);
1597 changed |= 0x01;
1598 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1599 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1600 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
1601 6);
1602 changed |= 0x01;
1603 } else if (debug_status & DBSR_IAC1) {
1604 current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
1605 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1606 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
1607 1);
1608 changed |= 0x01;
1609 } else if (debug_status & DBSR_IAC2) {
1610 current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
1611 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
1612 2);
1613 changed |= 0x01;
1614 } else if (debug_status & DBSR_IAC3) {
1615 current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
1616 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1617 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
1618 3);
1619 changed |= 0x01;
1620 } else if (debug_status & DBSR_IAC4) {
1621 current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
1622 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
1623 4);
1624 changed |= 0x01;
1625 }
1626 /*
1627 * At the point this routine was called, the MSR(DE) was turned off.
1628 * Check all other debug flags and see if that bit needs to be turned
1629 * back on or not.
1630 */
1631 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1632 current->thread.debug.dbcr1))
1633 regs->msr |= MSR_DE;
1634 else
1635 /* Make sure the IDM flag is off */
1636 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1637
1638 if (changed & 0x01)
1639 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
1640 }
1641
DebugException(struct pt_regs * regs,unsigned long debug_status)1642 void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
1643 {
1644 current->thread.debug.dbsr = debug_status;
1645
1646 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1647 * on server, it stops on the target of the branch. In order to simulate
1648 * the server behaviour, we thus restart right away with a single step
1649 * instead of stopping here when hitting a BT
1650 */
1651 if (debug_status & DBSR_BT) {
1652 regs->msr &= ~MSR_DE;
1653
1654 /* Disable BT */
1655 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1656 /* Clear the BT event */
1657 mtspr(SPRN_DBSR, DBSR_BT);
1658
1659 /* Do the single step trick only when coming from userspace */
1660 if (user_mode(regs)) {
1661 current->thread.debug.dbcr0 &= ~DBCR0_BT;
1662 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1663 regs->msr |= MSR_DE;
1664 return;
1665 }
1666
1667 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1668 5, SIGTRAP) == NOTIFY_STOP) {
1669 return;
1670 }
1671 if (debugger_sstep(regs))
1672 return;
1673 } else if (debug_status & DBSR_IC) { /* Instruction complete */
1674 regs->msr &= ~MSR_DE;
1675
1676 /* Disable instruction completion */
1677 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1678 /* Clear the instruction completion event */
1679 mtspr(SPRN_DBSR, DBSR_IC);
1680
1681 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1682 5, SIGTRAP) == NOTIFY_STOP) {
1683 return;
1684 }
1685
1686 if (debugger_sstep(regs))
1687 return;
1688
1689 if (user_mode(regs)) {
1690 current->thread.debug.dbcr0 &= ~DBCR0_IC;
1691 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1692 current->thread.debug.dbcr1))
1693 regs->msr |= MSR_DE;
1694 else
1695 /* Make sure the IDM bit is off */
1696 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1697 }
1698
1699 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1700 } else
1701 handle_debug(regs, debug_status);
1702 }
1703 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1704
1705 #if !defined(CONFIG_TAU_INT)
TAUException(struct pt_regs * regs)1706 void TAUException(struct pt_regs *regs)
1707 {
1708 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1709 regs->nip, regs->msr, regs->trap, print_tainted());
1710 }
1711 #endif /* CONFIG_INT_TAU */
1712
1713 #ifdef CONFIG_ALTIVEC
altivec_assist_exception(struct pt_regs * regs)1714 void altivec_assist_exception(struct pt_regs *regs)
1715 {
1716 int err;
1717
1718 if (!user_mode(regs)) {
1719 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1720 " at %lx\n", regs->nip);
1721 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
1722 }
1723
1724 flush_altivec_to_thread(current);
1725
1726 PPC_WARN_EMULATED(altivec, regs);
1727 err = emulate_altivec(regs);
1728 if (err == 0) {
1729 regs->nip += 4; /* skip emulated instruction */
1730 emulate_single_step(regs);
1731 return;
1732 }
1733
1734 if (err == -EFAULT) {
1735 /* got an error reading the instruction */
1736 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1737 } else {
1738 /* didn't recognize the instruction */
1739 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1740 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
1741 "in %s at %lx\n", current->comm, regs->nip);
1742 current->thread.vr_state.vscr.u[3] |= 0x10000;
1743 }
1744 }
1745 #endif /* CONFIG_ALTIVEC */
1746
1747 #ifdef CONFIG_FSL_BOOKE
CacheLockingException(struct pt_regs * regs,unsigned long address,unsigned long error_code)1748 void CacheLockingException(struct pt_regs *regs, unsigned long address,
1749 unsigned long error_code)
1750 {
1751 /* We treat cache locking instructions from the user
1752 * as priv ops, in the future we could try to do
1753 * something smarter
1754 */
1755 if (error_code & (ESR_DLK|ESR_ILK))
1756 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1757 return;
1758 }
1759 #endif /* CONFIG_FSL_BOOKE */
1760
1761 #ifdef CONFIG_SPE
SPEFloatingPointException(struct pt_regs * regs)1762 void SPEFloatingPointException(struct pt_regs *regs)
1763 {
1764 extern int do_spe_mathemu(struct pt_regs *regs);
1765 unsigned long spefscr;
1766 int fpexc_mode;
1767 int code = 0;
1768 int err;
1769
1770 flush_spe_to_thread(current);
1771
1772 spefscr = current->thread.spefscr;
1773 fpexc_mode = current->thread.fpexc_mode;
1774
1775 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1776 code = FPE_FLTOVF;
1777 }
1778 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1779 code = FPE_FLTUND;
1780 }
1781 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1782 code = FPE_FLTDIV;
1783 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1784 code = FPE_FLTINV;
1785 }
1786 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1787 code = FPE_FLTRES;
1788
1789 err = do_spe_mathemu(regs);
1790 if (err == 0) {
1791 regs->nip += 4; /* skip emulated instruction */
1792 emulate_single_step(regs);
1793 return;
1794 }
1795
1796 if (err == -EFAULT) {
1797 /* got an error reading the instruction */
1798 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1799 } else if (err == -EINVAL) {
1800 /* didn't recognize the instruction */
1801 printk(KERN_ERR "unrecognized spe instruction "
1802 "in %s at %lx\n", current->comm, regs->nip);
1803 } else {
1804 _exception(SIGFPE, regs, code, regs->nip);
1805 }
1806
1807 return;
1808 }
1809
SPEFloatingPointRoundException(struct pt_regs * regs)1810 void SPEFloatingPointRoundException(struct pt_regs *regs)
1811 {
1812 extern int speround_handler(struct pt_regs *regs);
1813 int err;
1814
1815 preempt_disable();
1816 if (regs->msr & MSR_SPE)
1817 giveup_spe(current);
1818 preempt_enable();
1819
1820 regs->nip -= 4;
1821 err = speround_handler(regs);
1822 if (err == 0) {
1823 regs->nip += 4; /* skip emulated instruction */
1824 emulate_single_step(regs);
1825 return;
1826 }
1827
1828 if (err == -EFAULT) {
1829 /* got an error reading the instruction */
1830 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1831 } else if (err == -EINVAL) {
1832 /* didn't recognize the instruction */
1833 printk(KERN_ERR "unrecognized spe instruction "
1834 "in %s at %lx\n", current->comm, regs->nip);
1835 } else {
1836 _exception(SIGFPE, regs, 0, regs->nip);
1837 return;
1838 }
1839 }
1840 #endif
1841
1842 /*
1843 * We enter here if we get an unrecoverable exception, that is, one
1844 * that happened at a point where the RI (recoverable interrupt) bit
1845 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1846 * we therefore lost state by taking this exception.
1847 */
unrecoverable_exception(struct pt_regs * regs)1848 void unrecoverable_exception(struct pt_regs *regs)
1849 {
1850 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1851 regs->trap, regs->nip);
1852 die("Unrecoverable exception", regs, SIGABRT);
1853 }
1854
1855 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
1856 /*
1857 * Default handler for a Watchdog exception,
1858 * spins until a reboot occurs
1859 */
WatchdogHandler(struct pt_regs * regs)1860 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1861 {
1862 /* Generic WatchdogHandler, implement your own */
1863 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1864 return;
1865 }
1866
WatchdogException(struct pt_regs * regs)1867 void WatchdogException(struct pt_regs *regs)
1868 {
1869 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1870 WatchdogHandler(regs);
1871 }
1872 #endif
1873
1874 /*
1875 * We enter here if we discover during exception entry that we are
1876 * running in supervisor mode with a userspace value in the stack pointer.
1877 */
kernel_bad_stack(struct pt_regs * regs)1878 void kernel_bad_stack(struct pt_regs *regs)
1879 {
1880 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1881 regs->gpr[1], regs->nip);
1882 die("Bad kernel stack pointer", regs, SIGABRT);
1883 }
1884
trap_init(void)1885 void __init trap_init(void)
1886 {
1887 }
1888
1889
1890 #ifdef CONFIG_PPC_EMULATED_STATS
1891
1892 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1893
1894 struct ppc_emulated ppc_emulated = {
1895 #ifdef CONFIG_ALTIVEC
1896 WARN_EMULATED_SETUP(altivec),
1897 #endif
1898 WARN_EMULATED_SETUP(dcba),
1899 WARN_EMULATED_SETUP(dcbz),
1900 WARN_EMULATED_SETUP(fp_pair),
1901 WARN_EMULATED_SETUP(isel),
1902 WARN_EMULATED_SETUP(mcrxr),
1903 WARN_EMULATED_SETUP(mfpvr),
1904 WARN_EMULATED_SETUP(multiple),
1905 WARN_EMULATED_SETUP(popcntb),
1906 WARN_EMULATED_SETUP(spe),
1907 WARN_EMULATED_SETUP(string),
1908 WARN_EMULATED_SETUP(sync),
1909 WARN_EMULATED_SETUP(unaligned),
1910 #ifdef CONFIG_MATH_EMULATION
1911 WARN_EMULATED_SETUP(math),
1912 #endif
1913 #ifdef CONFIG_VSX
1914 WARN_EMULATED_SETUP(vsx),
1915 #endif
1916 #ifdef CONFIG_PPC64
1917 WARN_EMULATED_SETUP(mfdscr),
1918 WARN_EMULATED_SETUP(mtdscr),
1919 WARN_EMULATED_SETUP(lq_stq),
1920 #endif
1921 };
1922
1923 u32 ppc_warn_emulated;
1924
ppc_warn_emulated_print(const char * type)1925 void ppc_warn_emulated_print(const char *type)
1926 {
1927 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
1928 type);
1929 }
1930
ppc_warn_emulated_init(void)1931 static int __init ppc_warn_emulated_init(void)
1932 {
1933 struct dentry *dir, *d;
1934 unsigned int i;
1935 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
1936
1937 if (!powerpc_debugfs_root)
1938 return -ENODEV;
1939
1940 dir = debugfs_create_dir("emulated_instructions",
1941 powerpc_debugfs_root);
1942 if (!dir)
1943 return -ENOMEM;
1944
1945 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
1946 &ppc_warn_emulated);
1947 if (!d)
1948 goto fail;
1949
1950 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
1951 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
1952 (u32 *)&entries[i].val.counter);
1953 if (!d)
1954 goto fail;
1955 }
1956
1957 return 0;
1958
1959 fail:
1960 debugfs_remove_recursive(dir);
1961 return -ENOMEM;
1962 }
1963
1964 device_initcall(ppc_warn_emulated_init);
1965
1966 #endif /* CONFIG_PPC_EMULATED_STATS */
1967