1
2 /*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software Foundation,
21 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24 #ifndef __LINUX_XHCI_HCD_H
25 #define __LINUX_XHCI_HCD_H
26
27 #include <linux/usb.h>
28 #include <linux/timer.h>
29 #include <linux/kernel.h>
30 #include <linux/usb/hcd.h>
31 #include <linux/io-64-nonatomic-lo-hi.h>
32
33 /* Code sharing between pci-quirks and xhci hcd */
34 #include "xhci-ext-caps.h"
35 #include "pci-quirks.h"
36
37 /* xHCI PCI Configuration Registers */
38 #define XHCI_SBRN_OFFSET (0x60)
39
40 /* Max number of USB devices for any host controller - limit in section 6.1 */
41 #define MAX_HC_SLOTS 256
42 /* Section 5.3.3 - MaxPorts */
43 #define MAX_HC_PORTS 127
44
45 /*
46 * xHCI register interface.
47 * This corresponds to the eXtensible Host Controller Interface (xHCI)
48 * Revision 0.95 specification
49 */
50
51 /**
52 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
53 * @hc_capbase: length of the capabilities register and HC version number
54 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
55 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
56 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
57 * @hcc_params: HCCPARAMS - Capability Parameters
58 * @db_off: DBOFF - Doorbell array offset
59 * @run_regs_off: RTSOFF - Runtime register space offset
60 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
61 */
62 struct xhci_cap_regs {
63 __le32 hc_capbase;
64 __le32 hcs_params1;
65 __le32 hcs_params2;
66 __le32 hcs_params3;
67 __le32 hcc_params;
68 __le32 db_off;
69 __le32 run_regs_off;
70 __le32 hcc_params2; /* xhci 1.1 */
71 /* Reserved up to (CAPLENGTH - 0x1C) */
72 };
73
74 /* hc_capbase bitmasks */
75 /* bits 7:0 - how long is the Capabilities register */
76 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
77 /* bits 31:16 */
78 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
79
80 /* HCSPARAMS1 - hcs_params1 - bitmasks */
81 /* bits 0:7, Max Device Slots */
82 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
83 #define HCS_SLOTS_MASK 0xff
84 /* bits 8:18, Max Interrupters */
85 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
86 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
87 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
88
89 /* HCSPARAMS2 - hcs_params2 - bitmasks */
90 /* bits 0:3, frames or uframes that SW needs to queue transactions
91 * ahead of the HW to meet periodic deadlines */
92 #define HCS_IST(p) (((p) >> 0) & 0xf)
93 /* bits 4:7, max number of Event Ring segments */
94 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
95 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
96 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
97 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
98 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
99
100 /* HCSPARAMS3 - hcs_params3 - bitmasks */
101 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
102 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
103 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
104 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
105
106 /* HCCPARAMS - hcc_params - bitmasks */
107 /* true: HC can use 64-bit address pointers */
108 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
109 /* true: HC can do bandwidth negotiation */
110 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
111 /* true: HC uses 64-byte Device Context structures
112 * FIXME 64-byte context structures aren't supported yet.
113 */
114 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
115 /* true: HC has port power switches */
116 #define HCC_PPC(p) ((p) & (1 << 3))
117 /* true: HC has port indicators */
118 #define HCS_INDICATOR(p) ((p) & (1 << 4))
119 /* true: HC has Light HC Reset Capability */
120 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
121 /* true: HC supports latency tolerance messaging */
122 #define HCC_LTC(p) ((p) & (1 << 6))
123 /* true: no secondary Stream ID Support */
124 #define HCC_NSS(p) ((p) & (1 << 7))
125 /* true: HC supports Stopped - Short Packet */
126 #define HCC_SPC(p) ((p) & (1 << 9))
127 /* true: HC has Contiguous Frame ID Capability */
128 #define HCC_CFC(p) ((p) & (1 << 11))
129 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
130 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
131 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
132 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
133
134 /* db_off bitmask - bits 0:1 reserved */
135 #define DBOFF_MASK (~0x3)
136
137 /* run_regs_off bitmask - bits 0:4 reserved */
138 #define RTSOFF_MASK (~0x1f)
139
140 /* HCCPARAMS2 - hcc_params2 - bitmasks */
141 /* true: HC supports U3 entry Capability */
142 #define HCC2_U3C(p) ((p) & (1 << 0))
143 /* true: HC supports Configure endpoint command Max exit latency too large */
144 #define HCC2_CMC(p) ((p) & (1 << 1))
145 /* true: HC supports Force Save context Capability */
146 #define HCC2_FSC(p) ((p) & (1 << 2))
147 /* true: HC supports Compliance Transition Capability */
148 #define HCC2_CTC(p) ((p) & (1 << 3))
149 /* true: HC support Large ESIT payload Capability > 48k */
150 #define HCC2_LEC(p) ((p) & (1 << 4))
151 /* true: HC support Configuration Information Capability */
152 #define HCC2_CIC(p) ((p) & (1 << 5))
153 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
154 #define HCC2_ETC(p) ((p) & (1 << 6))
155
156 /* Number of registers per port */
157 #define NUM_PORT_REGS 4
158
159 #define PORTSC 0
160 #define PORTPMSC 1
161 #define PORTLI 2
162 #define PORTHLPMC 3
163
164 /**
165 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
166 * @command: USBCMD - xHC command register
167 * @status: USBSTS - xHC status register
168 * @page_size: This indicates the page size that the host controller
169 * supports. If bit n is set, the HC supports a page size
170 * of 2^(n+12), up to a 128MB page size.
171 * 4K is the minimum page size.
172 * @cmd_ring: CRP - 64-bit Command Ring Pointer
173 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
174 * @config_reg: CONFIG - Configure Register
175 * @port_status_base: PORTSCn - base address for Port Status and Control
176 * Each port has a Port Status and Control register,
177 * followed by a Port Power Management Status and Control
178 * register, a Port Link Info register, and a reserved
179 * register.
180 * @port_power_base: PORTPMSCn - base address for
181 * Port Power Management Status and Control
182 * @port_link_base: PORTLIn - base address for Port Link Info (current
183 * Link PM state and control) for USB 2.1 and USB 3.0
184 * devices.
185 */
186 struct xhci_op_regs {
187 __le32 command;
188 __le32 status;
189 __le32 page_size;
190 __le32 reserved1;
191 __le32 reserved2;
192 __le32 dev_notification;
193 __le64 cmd_ring;
194 /* rsvd: offset 0x20-2F */
195 __le32 reserved3[4];
196 __le64 dcbaa_ptr;
197 __le32 config_reg;
198 /* rsvd: offset 0x3C-3FF */
199 __le32 reserved4[241];
200 /* port 1 registers, which serve as a base address for other ports */
201 __le32 port_status_base;
202 __le32 port_power_base;
203 __le32 port_link_base;
204 __le32 reserved5;
205 /* registers for ports 2-255 */
206 __le32 reserved6[NUM_PORT_REGS*254];
207 };
208
209 /* USBCMD - USB command - command bitmasks */
210 /* start/stop HC execution - do not write unless HC is halted*/
211 #define CMD_RUN XHCI_CMD_RUN
212 /* Reset HC - resets internal HC state machine and all registers (except
213 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
214 * The xHCI driver must reinitialize the xHC after setting this bit.
215 */
216 #define CMD_RESET (1 << 1)
217 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
218 #define CMD_EIE XHCI_CMD_EIE
219 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
220 #define CMD_HSEIE XHCI_CMD_HSEIE
221 /* bits 4:6 are reserved (and should be preserved on writes). */
222 /* light reset (port status stays unchanged) - reset completed when this is 0 */
223 #define CMD_LRESET (1 << 7)
224 /* host controller save/restore state. */
225 #define CMD_CSS (1 << 8)
226 #define CMD_CRS (1 << 9)
227 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
228 #define CMD_EWE XHCI_CMD_EWE
229 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
230 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
231 * '0' means the xHC can power it off if all ports are in the disconnect,
232 * disabled, or powered-off state.
233 */
234 #define CMD_PM_INDEX (1 << 11)
235 /* bits 12:31 are reserved (and should be preserved on writes). */
236
237 /* IMAN - Interrupt Management Register */
238 #define IMAN_IE (1 << 1)
239 #define IMAN_IP (1 << 0)
240
241 /* USBSTS - USB status - status bitmasks */
242 /* HC not running - set to 1 when run/stop bit is cleared. */
243 #define STS_HALT XHCI_STS_HALT
244 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
245 #define STS_FATAL (1 << 2)
246 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
247 #define STS_EINT (1 << 3)
248 /* port change detect */
249 #define STS_PORT (1 << 4)
250 /* bits 5:7 reserved and zeroed */
251 /* save state status - '1' means xHC is saving state */
252 #define STS_SAVE (1 << 8)
253 /* restore state status - '1' means xHC is restoring state */
254 #define STS_RESTORE (1 << 9)
255 /* true: save or restore error */
256 #define STS_SRE (1 << 10)
257 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
258 #define STS_CNR XHCI_STS_CNR
259 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
260 #define STS_HCE (1 << 12)
261 /* bits 13:31 reserved and should be preserved */
262
263 /*
264 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
265 * Generate a device notification event when the HC sees a transaction with a
266 * notification type that matches a bit set in this bit field.
267 */
268 #define DEV_NOTE_MASK (0xffff)
269 #define ENABLE_DEV_NOTE(x) (1 << (x))
270 /* Most of the device notification types should only be used for debug.
271 * SW does need to pay attention to function wake notifications.
272 */
273 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
274
275 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
276 /* bit 0 is the command ring cycle state */
277 /* stop ring operation after completion of the currently executing command */
278 #define CMD_RING_PAUSE (1 << 1)
279 /* stop ring immediately - abort the currently executing command */
280 #define CMD_RING_ABORT (1 << 2)
281 /* true: command ring is running */
282 #define CMD_RING_RUNNING (1 << 3)
283 /* bits 4:5 reserved and should be preserved */
284 /* Command Ring pointer - bit mask for the lower 32 bits. */
285 #define CMD_RING_RSVD_BITS (0x3f)
286
287 /* CONFIG - Configure Register - config_reg bitmasks */
288 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
289 #define MAX_DEVS(p) ((p) & 0xff)
290 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
291 #define CONFIG_U3E (1 << 8)
292 /* bit 9: Configuration Information Enable, xhci 1.1 */
293 #define CONFIG_CIE (1 << 9)
294 /* bits 10:31 - reserved and should be preserved */
295
296 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
297 /* true: device connected */
298 #define PORT_CONNECT (1 << 0)
299 /* true: port enabled */
300 #define PORT_PE (1 << 1)
301 /* bit 2 reserved and zeroed */
302 /* true: port has an over-current condition */
303 #define PORT_OC (1 << 3)
304 /* true: port reset signaling asserted */
305 #define PORT_RESET (1 << 4)
306 /* Port Link State - bits 5:8
307 * A read gives the current link PM state of the port,
308 * a write with Link State Write Strobe set sets the link state.
309 */
310 #define PORT_PLS_MASK (0xf << 5)
311 #define XDEV_U0 (0x0 << 5)
312 #define XDEV_U1 (0x1 << 5)
313 #define XDEV_U2 (0x2 << 5)
314 #define XDEV_U3 (0x3 << 5)
315 #define XDEV_INACTIVE (0x6 << 5)
316 #define XDEV_POLLING (0x7 << 5)
317 #define XDEV_RECOVERY (0x8 << 5)
318 #define XDEV_COMP_MODE (0xa << 5)
319 #define XDEV_RESUME (0xf << 5)
320 /* true: port has power (see HCC_PPC) */
321 #define PORT_POWER (1 << 9)
322 /* bits 10:13 indicate device speed:
323 * 0 - undefined speed - port hasn't be initialized by a reset yet
324 * 1 - full speed
325 * 2 - low speed
326 * 3 - high speed
327 * 4 - super speed
328 * 5-15 reserved
329 */
330 #define DEV_SPEED_MASK (0xf << 10)
331 #define XDEV_FS (0x1 << 10)
332 #define XDEV_LS (0x2 << 10)
333 #define XDEV_HS (0x3 << 10)
334 #define XDEV_SS (0x4 << 10)
335 #define XDEV_SSP (0x5 << 10)
336 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
337 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
338 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
339 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
340 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
341 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
342 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
343 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
344
345 /* Bits 20:23 in the Slot Context are the speed for the device */
346 #define SLOT_SPEED_FS (XDEV_FS << 10)
347 #define SLOT_SPEED_LS (XDEV_LS << 10)
348 #define SLOT_SPEED_HS (XDEV_HS << 10)
349 #define SLOT_SPEED_SS (XDEV_SS << 10)
350 /* Port Indicator Control */
351 #define PORT_LED_OFF (0 << 14)
352 #define PORT_LED_AMBER (1 << 14)
353 #define PORT_LED_GREEN (2 << 14)
354 #define PORT_LED_MASK (3 << 14)
355 /* Port Link State Write Strobe - set this when changing link state */
356 #define PORT_LINK_STROBE (1 << 16)
357 /* true: connect status change */
358 #define PORT_CSC (1 << 17)
359 /* true: port enable change */
360 #define PORT_PEC (1 << 18)
361 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
362 * into an enabled state, and the device into the default state. A "warm" reset
363 * also resets the link, forcing the device through the link training sequence.
364 * SW can also look at the Port Reset register to see when warm reset is done.
365 */
366 #define PORT_WRC (1 << 19)
367 /* true: over-current change */
368 #define PORT_OCC (1 << 20)
369 /* true: reset change - 1 to 0 transition of PORT_RESET */
370 #define PORT_RC (1 << 21)
371 /* port link status change - set on some port link state transitions:
372 * Transition Reason
373 * ------------------------------------------------------------------------------
374 * - U3 to Resume Wakeup signaling from a device
375 * - Resume to Recovery to U0 USB 3.0 device resume
376 * - Resume to U0 USB 2.0 device resume
377 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
378 * - U3 to U0 Software resume of USB 2.0 device complete
379 * - U2 to U0 L1 resume of USB 2.1 device complete
380 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
381 * - U0 to disabled L1 entry error with USB 2.1 device
382 * - Any state to inactive Error on USB 3.0 port
383 */
384 #define PORT_PLC (1 << 22)
385 /* port configure error change - port failed to configure its link partner */
386 #define PORT_CEC (1 << 23)
387 #define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
388 PORT_RC | PORT_PLC | PORT_CEC)
389
390
391 /* Cold Attach Status - xHC can set this bit to report device attached during
392 * Sx state. Warm port reset should be perfomed to clear this bit and move port
393 * to connected state.
394 */
395 #define PORT_CAS (1 << 24)
396 /* wake on connect (enable) */
397 #define PORT_WKCONN_E (1 << 25)
398 /* wake on disconnect (enable) */
399 #define PORT_WKDISC_E (1 << 26)
400 /* wake on over-current (enable) */
401 #define PORT_WKOC_E (1 << 27)
402 /* bits 28:29 reserved */
403 /* true: device is non-removable - for USB 3.0 roothub emulation */
404 #define PORT_DEV_REMOVE (1 << 30)
405 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
406 #define PORT_WR (1 << 31)
407
408 /* We mark duplicate entries with -1 */
409 #define DUPLICATE_ENTRY ((u8)(-1))
410
411 /* Port Power Management Status and Control - port_power_base bitmasks */
412 /* Inactivity timer value for transitions into U1, in microseconds.
413 * Timeout can be up to 127us. 0xFF means an infinite timeout.
414 */
415 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
416 #define PORT_U1_TIMEOUT_MASK 0xff
417 /* Inactivity timer value for transitions into U2 */
418 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
419 #define PORT_U2_TIMEOUT_MASK (0xff << 8)
420 /* Bits 24:31 for port testing */
421
422 /* USB2 Protocol PORTSPMSC */
423 #define PORT_L1S_MASK 7
424 #define PORT_L1S_SUCCESS 1
425 #define PORT_RWE (1 << 3)
426 #define PORT_HIRD(p) (((p) & 0xf) << 4)
427 #define PORT_HIRD_MASK (0xf << 4)
428 #define PORT_L1DS_MASK (0xff << 8)
429 #define PORT_L1DS(p) (((p) & 0xff) << 8)
430 #define PORT_HLE (1 << 16)
431
432 /* USB3 Protocol PORTLI Port Link Information */
433 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
434 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
435
436 /* USB2 Protocol PORTHLPMC */
437 #define PORT_HIRDM(p)((p) & 3)
438 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
439 #define PORT_BESLD(p)(((p) & 0xf) << 10)
440
441 /* use 512 microseconds as USB2 LPM L1 default timeout. */
442 #define XHCI_L1_TIMEOUT 512
443
444 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
445 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
446 * by other operating systems.
447 *
448 * XHCI 1.0 errata 8/14/12 Table 13 notes:
449 * "Software should choose xHC BESL/BESLD field values that do not violate a
450 * device's resume latency requirements,
451 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
452 * or not program values < '4' if BLC = '0' and a BESL device is attached.
453 */
454 #define XHCI_DEFAULT_BESL 4
455
456 /**
457 * struct xhci_intr_reg - Interrupt Register Set
458 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
459 * interrupts and check for pending interrupts.
460 * @irq_control: IMOD - Interrupt Moderation Register.
461 * Used to throttle interrupts.
462 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
463 * @erst_base: ERST base address.
464 * @erst_dequeue: Event ring dequeue pointer.
465 *
466 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
467 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
468 * multiple segments of the same size. The HC places events on the ring and
469 * "updates the Cycle bit in the TRBs to indicate to software the current
470 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
471 * updates the dequeue pointer.
472 */
473 struct xhci_intr_reg {
474 __le32 irq_pending;
475 __le32 irq_control;
476 __le32 erst_size;
477 __le32 rsvd;
478 __le64 erst_base;
479 __le64 erst_dequeue;
480 };
481
482 /* irq_pending bitmasks */
483 #define ER_IRQ_PENDING(p) ((p) & 0x1)
484 /* bits 2:31 need to be preserved */
485 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
486 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
487 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
488 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
489
490 /* irq_control bitmasks */
491 /* Minimum interval between interrupts (in 250ns intervals). The interval
492 * between interrupts will be longer if there are no events on the event ring.
493 * Default is 4000 (1 ms).
494 */
495 #define ER_IRQ_INTERVAL_MASK (0xffff)
496 /* Counter used to count down the time to the next interrupt - HW use only */
497 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
498
499 /* erst_size bitmasks */
500 /* Preserve bits 16:31 of erst_size */
501 #define ERST_SIZE_MASK (0xffff << 16)
502
503 /* erst_dequeue bitmasks */
504 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
505 * where the current dequeue pointer lies. This is an optional HW hint.
506 */
507 #define ERST_DESI_MASK (0x7)
508 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
509 * a work queue (or delayed service routine)?
510 */
511 #define ERST_EHB (1 << 3)
512 #define ERST_PTR_MASK (0xf)
513
514 /**
515 * struct xhci_run_regs
516 * @microframe_index:
517 * MFINDEX - current microframe number
518 *
519 * Section 5.5 Host Controller Runtime Registers:
520 * "Software should read and write these registers using only Dword (32 bit)
521 * or larger accesses"
522 */
523 struct xhci_run_regs {
524 __le32 microframe_index;
525 __le32 rsvd[7];
526 struct xhci_intr_reg ir_set[128];
527 };
528
529 /**
530 * struct doorbell_array
531 *
532 * Bits 0 - 7: Endpoint target
533 * Bits 8 - 15: RsvdZ
534 * Bits 16 - 31: Stream ID
535 *
536 * Section 5.6
537 */
538 struct xhci_doorbell_array {
539 __le32 doorbell[256];
540 };
541
542 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
543 #define DB_VALUE_HOST 0x00000000
544
545 /**
546 * struct xhci_protocol_caps
547 * @revision: major revision, minor revision, capability ID,
548 * and next capability pointer.
549 * @name_string: Four ASCII characters to say which spec this xHC
550 * follows, typically "USB ".
551 * @port_info: Port offset, count, and protocol-defined information.
552 */
553 struct xhci_protocol_caps {
554 u32 revision;
555 u32 name_string;
556 u32 port_info;
557 };
558
559 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
560 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
561 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
562 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
563 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
564
565 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
566 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
567 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
568 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
569 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
570 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
571
572 #define PLT_MASK (0x03 << 6)
573 #define PLT_SYM (0x00 << 6)
574 #define PLT_ASYM_RX (0x02 << 6)
575 #define PLT_ASYM_TX (0x03 << 6)
576
577 /**
578 * struct xhci_container_ctx
579 * @type: Type of context. Used to calculated offsets to contained contexts.
580 * @size: Size of the context data
581 * @bytes: The raw context data given to HW
582 * @dma: dma address of the bytes
583 *
584 * Represents either a Device or Input context. Holds a pointer to the raw
585 * memory used for the context (bytes) and dma address of it (dma).
586 */
587 struct xhci_container_ctx {
588 unsigned type;
589 #define XHCI_CTX_TYPE_DEVICE 0x1
590 #define XHCI_CTX_TYPE_INPUT 0x2
591
592 int size;
593
594 u8 *bytes;
595 dma_addr_t dma;
596 };
597
598 /**
599 * struct xhci_slot_ctx
600 * @dev_info: Route string, device speed, hub info, and last valid endpoint
601 * @dev_info2: Max exit latency for device number, root hub port number
602 * @tt_info: tt_info is used to construct split transaction tokens
603 * @dev_state: slot state and device address
604 *
605 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
606 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
607 * reserved at the end of the slot context for HC internal use.
608 */
609 struct xhci_slot_ctx {
610 __le32 dev_info;
611 __le32 dev_info2;
612 __le32 tt_info;
613 __le32 dev_state;
614 /* offset 0x10 to 0x1f reserved for HC internal use */
615 __le32 reserved[4];
616 };
617
618 /* dev_info bitmasks */
619 /* Route String - 0:19 */
620 #define ROUTE_STRING_MASK (0xfffff)
621 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
622 #define DEV_SPEED (0xf << 20)
623 /* bit 24 reserved */
624 /* Is this LS/FS device connected through a HS hub? - bit 25 */
625 #define DEV_MTT (0x1 << 25)
626 /* Set if the device is a hub - bit 26 */
627 #define DEV_HUB (0x1 << 26)
628 /* Index of the last valid endpoint context in this device context - 27:31 */
629 #define LAST_CTX_MASK (0x1f << 27)
630 #define LAST_CTX(p) ((p) << 27)
631 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
632 #define SLOT_FLAG (1 << 0)
633 #define EP0_FLAG (1 << 1)
634
635 /* dev_info2 bitmasks */
636 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
637 #define MAX_EXIT (0xffff)
638 /* Root hub port number that is needed to access the USB device */
639 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
640 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
641 /* Maximum number of ports under a hub device */
642 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
643
644 /* tt_info bitmasks */
645 /*
646 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
647 * The Slot ID of the hub that isolates the high speed signaling from
648 * this low or full-speed device. '0' if attached to root hub port.
649 */
650 #define TT_SLOT (0xff)
651 /*
652 * The number of the downstream facing port of the high-speed hub
653 * '0' if the device is not low or full speed.
654 */
655 #define TT_PORT (0xff << 8)
656 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
657
658 /* dev_state bitmasks */
659 /* USB device address - assigned by the HC */
660 #define DEV_ADDR_MASK (0xff)
661 /* bits 8:26 reserved */
662 /* Slot state */
663 #define SLOT_STATE (0x1f << 27)
664 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
665
666 #define SLOT_STATE_DISABLED 0
667 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
668 #define SLOT_STATE_DEFAULT 1
669 #define SLOT_STATE_ADDRESSED 2
670 #define SLOT_STATE_CONFIGURED 3
671
672 /**
673 * struct xhci_ep_ctx
674 * @ep_info: endpoint state, streams, mult, and interval information.
675 * @ep_info2: information on endpoint type, max packet size, max burst size,
676 * error count, and whether the HC will force an event for all
677 * transactions.
678 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
679 * defines one stream, this points to the endpoint transfer ring.
680 * Otherwise, it points to a stream context array, which has a
681 * ring pointer for each flow.
682 * @tx_info:
683 * Average TRB lengths for the endpoint ring and
684 * max payload within an Endpoint Service Interval Time (ESIT).
685 *
686 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
687 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
688 * reserved at the end of the endpoint context for HC internal use.
689 */
690 struct xhci_ep_ctx {
691 __le32 ep_info;
692 __le32 ep_info2;
693 __le64 deq;
694 __le32 tx_info;
695 /* offset 0x14 - 0x1f reserved for HC internal use */
696 __le32 reserved[3];
697 };
698
699 /* ep_info bitmasks */
700 /*
701 * Endpoint State - bits 0:2
702 * 0 - disabled
703 * 1 - running
704 * 2 - halted due to halt condition - ok to manipulate endpoint ring
705 * 3 - stopped
706 * 4 - TRB error
707 * 5-7 - reserved
708 */
709 #define EP_STATE_MASK (0x7)
710 #define EP_STATE_DISABLED 0
711 #define EP_STATE_RUNNING 1
712 #define EP_STATE_HALTED 2
713 #define EP_STATE_STOPPED 3
714 #define EP_STATE_ERROR 4
715 /* Mult - Max number of burtst within an interval, in EP companion desc. */
716 #define EP_MULT(p) (((p) & 0x3) << 8)
717 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
718 /* bits 10:14 are Max Primary Streams */
719 /* bit 15 is Linear Stream Array */
720 /* Interval - period between requests to an endpoint - 125u increments. */
721 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
722 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
723 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
724 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
725 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
726 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
727 #define EP_HAS_LSA (1 << 15)
728
729 /* ep_info2 bitmasks */
730 /*
731 * Force Event - generate transfer events for all TRBs for this endpoint
732 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
733 */
734 #define FORCE_EVENT (0x1)
735 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
736 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
737 #define EP_TYPE(p) ((p) << 3)
738 #define ISOC_OUT_EP 1
739 #define BULK_OUT_EP 2
740 #define INT_OUT_EP 3
741 #define CTRL_EP 4
742 #define ISOC_IN_EP 5
743 #define BULK_IN_EP 6
744 #define INT_IN_EP 7
745 /* bit 6 reserved */
746 /* bit 7 is Host Initiate Disable - for disabling stream selection */
747 #define MAX_BURST(p) (((p)&0xff) << 8)
748 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
749 #define MAX_PACKET(p) (((p)&0xffff) << 16)
750 #define MAX_PACKET_MASK (0xffff << 16)
751 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
752
753 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
754 * USB2.0 spec 9.6.6.
755 */
756 #define GET_MAX_PACKET(p) ((p) & 0x7ff)
757
758 /* tx_info bitmasks */
759 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
760 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
761 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
762
763 /* deq bitmasks */
764 #define EP_CTX_CYCLE_MASK (1 << 0)
765 #define SCTX_DEQ_MASK (~0xfL)
766
767
768 /**
769 * struct xhci_input_control_context
770 * Input control context; see section 6.2.5.
771 *
772 * @drop_context: set the bit of the endpoint context you want to disable
773 * @add_context: set the bit of the endpoint context you want to enable
774 */
775 struct xhci_input_control_ctx {
776 __le32 drop_flags;
777 __le32 add_flags;
778 __le32 rsvd2[6];
779 };
780
781 #define EP_IS_ADDED(ctrl_ctx, i) \
782 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
783 #define EP_IS_DROPPED(ctrl_ctx, i) \
784 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
785
786 /* Represents everything that is needed to issue a command on the command ring.
787 * It's useful to pre-allocate these for commands that cannot fail due to
788 * out-of-memory errors, like freeing streams.
789 */
790 struct xhci_command {
791 /* Input context for changing device state */
792 struct xhci_container_ctx *in_ctx;
793 u32 status;
794 /* If completion is null, no one is waiting on this command
795 * and the structure can be freed after the command completes.
796 */
797 struct completion *completion;
798 union xhci_trb *command_trb;
799 struct list_head cmd_list;
800 };
801
802 /* drop context bitmasks */
803 #define DROP_EP(x) (0x1 << x)
804 /* add context bitmasks */
805 #define ADD_EP(x) (0x1 << x)
806
807 struct xhci_stream_ctx {
808 /* 64-bit stream ring address, cycle state, and stream type */
809 __le64 stream_ring;
810 /* offset 0x14 - 0x1f reserved for HC internal use */
811 __le32 reserved[2];
812 };
813
814 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
815 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
816 /* Secondary stream array type, dequeue pointer is to a transfer ring */
817 #define SCT_SEC_TR 0
818 /* Primary stream array type, dequeue pointer is to a transfer ring */
819 #define SCT_PRI_TR 1
820 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
821 #define SCT_SSA_8 2
822 #define SCT_SSA_16 3
823 #define SCT_SSA_32 4
824 #define SCT_SSA_64 5
825 #define SCT_SSA_128 6
826 #define SCT_SSA_256 7
827
828 /* Assume no secondary streams for now */
829 struct xhci_stream_info {
830 struct xhci_ring **stream_rings;
831 /* Number of streams, including stream 0 (which drivers can't use) */
832 unsigned int num_streams;
833 /* The stream context array may be bigger than
834 * the number of streams the driver asked for
835 */
836 struct xhci_stream_ctx *stream_ctx_array;
837 unsigned int num_stream_ctxs;
838 dma_addr_t ctx_array_dma;
839 /* For mapping physical TRB addresses to segments in stream rings */
840 struct radix_tree_root trb_address_map;
841 struct xhci_command *free_streams_command;
842 };
843
844 #define SMALL_STREAM_ARRAY_SIZE 256
845 #define MEDIUM_STREAM_ARRAY_SIZE 1024
846
847 /* Some Intel xHCI host controllers need software to keep track of the bus
848 * bandwidth. Keep track of endpoint info here. Each root port is allocated
849 * the full bus bandwidth. We must also treat TTs (including each port under a
850 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
851 * (DMI) also limits the total bandwidth (across all domains) that can be used.
852 */
853 struct xhci_bw_info {
854 /* ep_interval is zero-based */
855 unsigned int ep_interval;
856 /* mult and num_packets are one-based */
857 unsigned int mult;
858 unsigned int num_packets;
859 unsigned int max_packet_size;
860 unsigned int max_esit_payload;
861 unsigned int type;
862 };
863
864 /* "Block" sizes in bytes the hardware uses for different device speeds.
865 * The logic in this part of the hardware limits the number of bits the hardware
866 * can use, so must represent bandwidth in a less precise manner to mimic what
867 * the scheduler hardware computes.
868 */
869 #define FS_BLOCK 1
870 #define HS_BLOCK 4
871 #define SS_BLOCK 16
872 #define DMI_BLOCK 32
873
874 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
875 * with each byte transferred. SuperSpeed devices have an initial overhead to
876 * set up bursts. These are in blocks, see above. LS overhead has already been
877 * translated into FS blocks.
878 */
879 #define DMI_OVERHEAD 8
880 #define DMI_OVERHEAD_BURST 4
881 #define SS_OVERHEAD 8
882 #define SS_OVERHEAD_BURST 32
883 #define HS_OVERHEAD 26
884 #define FS_OVERHEAD 20
885 #define LS_OVERHEAD 128
886 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
887 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
888 * of overhead associated with split transfers crossing microframe boundaries.
889 * 31 blocks is pure protocol overhead.
890 */
891 #define TT_HS_OVERHEAD (31 + 94)
892 #define TT_DMI_OVERHEAD (25 + 12)
893
894 /* Bandwidth limits in blocks */
895 #define FS_BW_LIMIT 1285
896 #define TT_BW_LIMIT 1320
897 #define HS_BW_LIMIT 1607
898 #define SS_BW_LIMIT_IN 3906
899 #define DMI_BW_LIMIT_IN 3906
900 #define SS_BW_LIMIT_OUT 3906
901 #define DMI_BW_LIMIT_OUT 3906
902
903 /* Percentage of bus bandwidth reserved for non-periodic transfers */
904 #define FS_BW_RESERVED 10
905 #define HS_BW_RESERVED 20
906 #define SS_BW_RESERVED 10
907
908 struct xhci_virt_ep {
909 struct xhci_ring *ring;
910 /* Related to endpoints that are configured to use stream IDs only */
911 struct xhci_stream_info *stream_info;
912 /* Temporary storage in case the configure endpoint command fails and we
913 * have to restore the device state to the previous state
914 */
915 struct xhci_ring *new_ring;
916 unsigned int ep_state;
917 #define SET_DEQ_PENDING (1 << 0)
918 #define EP_HALTED (1 << 1) /* For stall handling */
919 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */
920 /* Transitioning the endpoint to using streams, don't enqueue URBs */
921 #define EP_GETTING_STREAMS (1 << 3)
922 #define EP_HAS_STREAMS (1 << 4)
923 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
924 #define EP_GETTING_NO_STREAMS (1 << 5)
925 /* ---- Related to URB cancellation ---- */
926 struct list_head cancelled_td_list;
927 struct xhci_td *stopped_td;
928 unsigned int stopped_stream;
929 /* Watchdog timer for stop endpoint command to cancel URBs */
930 struct timer_list stop_cmd_timer;
931 int stop_cmds_pending;
932 struct xhci_hcd *xhci;
933 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
934 * command. We'll need to update the ring's dequeue segment and dequeue
935 * pointer after the command completes.
936 */
937 struct xhci_segment *queued_deq_seg;
938 union xhci_trb *queued_deq_ptr;
939 /*
940 * Sometimes the xHC can not process isochronous endpoint ring quickly
941 * enough, and it will miss some isoc tds on the ring and generate
942 * a Missed Service Error Event.
943 * Set skip flag when receive a Missed Service Error Event and
944 * process the missed tds on the endpoint ring.
945 */
946 bool skip;
947 /* Bandwidth checking storage */
948 struct xhci_bw_info bw_info;
949 struct list_head bw_endpoint_list;
950 /* Isoch Frame ID checking storage */
951 int next_frame_id;
952 };
953
954 enum xhci_overhead_type {
955 LS_OVERHEAD_TYPE = 0,
956 FS_OVERHEAD_TYPE,
957 HS_OVERHEAD_TYPE,
958 };
959
960 struct xhci_interval_bw {
961 unsigned int num_packets;
962 /* Sorted by max packet size.
963 * Head of the list is the greatest max packet size.
964 */
965 struct list_head endpoints;
966 /* How many endpoints of each speed are present. */
967 unsigned int overhead[3];
968 };
969
970 #define XHCI_MAX_INTERVAL 16
971
972 struct xhci_interval_bw_table {
973 unsigned int interval0_esit_payload;
974 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
975 /* Includes reserved bandwidth for async endpoints */
976 unsigned int bw_used;
977 unsigned int ss_bw_in;
978 unsigned int ss_bw_out;
979 };
980
981
982 struct xhci_virt_device {
983 struct usb_device *udev;
984 /*
985 * Commands to the hardware are passed an "input context" that
986 * tells the hardware what to change in its data structures.
987 * The hardware will return changes in an "output context" that
988 * software must allocate for the hardware. We need to keep
989 * track of input and output contexts separately because
990 * these commands might fail and we don't trust the hardware.
991 */
992 struct xhci_container_ctx *out_ctx;
993 /* Used for addressing devices and configuration changes */
994 struct xhci_container_ctx *in_ctx;
995 /* Rings saved to ensure old alt settings can be re-instated */
996 struct xhci_ring **ring_cache;
997 int num_rings_cached;
998 #define XHCI_MAX_RINGS_CACHED 31
999 struct xhci_virt_ep eps[31];
1000 struct completion cmd_completion;
1001 u8 fake_port;
1002 u8 real_port;
1003 struct xhci_interval_bw_table *bw_table;
1004 struct xhci_tt_bw_info *tt_info;
1005 /* The current max exit latency for the enabled USB3 link states. */
1006 u16 current_mel;
1007 };
1008
1009 /*
1010 * For each roothub, keep track of the bandwidth information for each periodic
1011 * interval.
1012 *
1013 * If a high speed hub is attached to the roothub, each TT associated with that
1014 * hub is a separate bandwidth domain. The interval information for the
1015 * endpoints on the devices under that TT will appear in the TT structure.
1016 */
1017 struct xhci_root_port_bw_info {
1018 struct list_head tts;
1019 unsigned int num_active_tts;
1020 struct xhci_interval_bw_table bw_table;
1021 };
1022
1023 struct xhci_tt_bw_info {
1024 struct list_head tt_list;
1025 int slot_id;
1026 int ttport;
1027 struct xhci_interval_bw_table bw_table;
1028 int active_eps;
1029 };
1030
1031
1032 /**
1033 * struct xhci_device_context_array
1034 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
1035 */
1036 struct xhci_device_context_array {
1037 /* 64-bit device addresses; we only write 32-bit addresses */
1038 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1039 /* private xHCD pointers */
1040 dma_addr_t dma;
1041 };
1042 /* TODO: write function to set the 64-bit device DMA address */
1043 /*
1044 * TODO: change this to be dynamically sized at HC mem init time since the HC
1045 * might not be able to handle the maximum number of devices possible.
1046 */
1047
1048
1049 struct xhci_transfer_event {
1050 /* 64-bit buffer address, or immediate data */
1051 __le64 buffer;
1052 __le32 transfer_len;
1053 /* This field is interpreted differently based on the type of TRB */
1054 __le32 flags;
1055 };
1056
1057 /* Transfer event TRB length bit mask */
1058 /* bits 0:23 */
1059 #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1060
1061 /** Transfer Event bit fields **/
1062 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1063
1064 /* Completion Code - only applicable for some types of TRBs */
1065 #define COMP_CODE_MASK (0xff << 24)
1066 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1067 #define COMP_SUCCESS 1
1068 /* Data Buffer Error */
1069 #define COMP_DB_ERR 2
1070 /* Babble Detected Error */
1071 #define COMP_BABBLE 3
1072 /* USB Transaction Error */
1073 #define COMP_TX_ERR 4
1074 /* TRB Error - some TRB field is invalid */
1075 #define COMP_TRB_ERR 5
1076 /* Stall Error - USB device is stalled */
1077 #define COMP_STALL 6
1078 /* Resource Error - HC doesn't have memory for that device configuration */
1079 #define COMP_ENOMEM 7
1080 /* Bandwidth Error - not enough room in schedule for this dev config */
1081 #define COMP_BW_ERR 8
1082 /* No Slots Available Error - HC ran out of device slots */
1083 #define COMP_ENOSLOTS 9
1084 /* Invalid Stream Type Error */
1085 #define COMP_STREAM_ERR 10
1086 /* Slot Not Enabled Error - doorbell rung for disabled device slot */
1087 #define COMP_EBADSLT 11
1088 /* Endpoint Not Enabled Error */
1089 #define COMP_EBADEP 12
1090 /* Short Packet */
1091 #define COMP_SHORT_TX 13
1092 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
1093 #define COMP_UNDERRUN 14
1094 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
1095 #define COMP_OVERRUN 15
1096 /* Virtual Function Event Ring Full Error */
1097 #define COMP_VF_FULL 16
1098 /* Parameter Error - Context parameter is invalid */
1099 #define COMP_EINVAL 17
1100 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
1101 #define COMP_BW_OVER 18
1102 /* Context State Error - illegal context state transition requested */
1103 #define COMP_CTX_STATE 19
1104 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
1105 #define COMP_PING_ERR 20
1106 /* Event Ring is full */
1107 #define COMP_ER_FULL 21
1108 /* Incompatible Device Error */
1109 #define COMP_DEV_ERR 22
1110 /* Missed Service Error - HC couldn't service an isoc ep within interval */
1111 #define COMP_MISSED_INT 23
1112 /* Successfully stopped command ring */
1113 #define COMP_CMD_STOP 24
1114 /* Successfully aborted current command and stopped command ring */
1115 #define COMP_CMD_ABORT 25
1116 /* Stopped - transfer was terminated by a stop endpoint command */
1117 #define COMP_STOP 26
1118 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */
1119 #define COMP_STOP_INVAL 27
1120 /* Same as COMP_EP_STOPPED, but a short packet detected */
1121 #define COMP_STOP_SHORT 28
1122 /* Max Exit Latency Too Large Error */
1123 #define COMP_MEL_ERR 29
1124 /* TRB type 30 reserved */
1125 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
1126 #define COMP_BUFF_OVER 31
1127 /* Event Lost Error - xHC has an "internal event overrun condition" */
1128 #define COMP_ISSUES 32
1129 /* Undefined Error - reported when other error codes don't apply */
1130 #define COMP_UNKNOWN 33
1131 /* Invalid Stream ID Error */
1132 #define COMP_STRID_ERR 34
1133 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
1134 #define COMP_2ND_BW_ERR 35
1135 /* Split Transaction Error */
1136 #define COMP_SPLIT_ERR 36
1137
1138 struct xhci_link_trb {
1139 /* 64-bit segment pointer*/
1140 __le64 segment_ptr;
1141 __le32 intr_target;
1142 __le32 control;
1143 };
1144
1145 /* control bitfields */
1146 #define LINK_TOGGLE (0x1<<1)
1147
1148 /* Command completion event TRB */
1149 struct xhci_event_cmd {
1150 /* Pointer to command TRB, or the value passed by the event data trb */
1151 __le64 cmd_trb;
1152 __le32 status;
1153 __le32 flags;
1154 };
1155
1156 /* flags bitmasks */
1157
1158 /* Address device - disable SetAddress */
1159 #define TRB_BSR (1<<9)
1160 enum xhci_setup_dev {
1161 SETUP_CONTEXT_ONLY,
1162 SETUP_CONTEXT_ADDRESS,
1163 };
1164
1165 /* bits 16:23 are the virtual function ID */
1166 /* bits 24:31 are the slot ID */
1167 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1168 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1169
1170 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1171 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1172 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1173
1174 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1175 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1176 #define LAST_EP_INDEX 30
1177
1178 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1179 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1180 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1181 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1182
1183
1184 /* Port Status Change Event TRB fields */
1185 /* Port ID - bits 31:24 */
1186 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1187
1188 /* Normal TRB fields */
1189 /* transfer_len bitmasks - bits 0:16 */
1190 #define TRB_LEN(p) ((p) & 0x1ffff)
1191 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1192 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1193 /* Interrupter Target - which MSI-X vector to target the completion event at */
1194 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1195 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1196 #define TRB_TBC(p) (((p) & 0x3) << 7)
1197 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1198
1199 /* Cycle bit - indicates TRB ownership by HC or HCD */
1200 #define TRB_CYCLE (1<<0)
1201 /*
1202 * Force next event data TRB to be evaluated before task switch.
1203 * Used to pass OS data back after a TD completes.
1204 */
1205 #define TRB_ENT (1<<1)
1206 /* Interrupt on short packet */
1207 #define TRB_ISP (1<<2)
1208 /* Set PCIe no snoop attribute */
1209 #define TRB_NO_SNOOP (1<<3)
1210 /* Chain multiple TRBs into a TD */
1211 #define TRB_CHAIN (1<<4)
1212 /* Interrupt on completion */
1213 #define TRB_IOC (1<<5)
1214 /* The buffer pointer contains immediate data */
1215 #define TRB_IDT (1<<6)
1216
1217 /* Block Event Interrupt */
1218 #define TRB_BEI (1<<9)
1219
1220 /* Control transfer TRB specific fields */
1221 #define TRB_DIR_IN (1<<16)
1222 #define TRB_TX_TYPE(p) ((p) << 16)
1223 #define TRB_DATA_OUT 2
1224 #define TRB_DATA_IN 3
1225
1226 /* Isochronous TRB specific fields */
1227 #define TRB_SIA (1<<31)
1228 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1229
1230 struct xhci_generic_trb {
1231 __le32 field[4];
1232 };
1233
1234 union xhci_trb {
1235 struct xhci_link_trb link;
1236 struct xhci_transfer_event trans_event;
1237 struct xhci_event_cmd event_cmd;
1238 struct xhci_generic_trb generic;
1239 };
1240
1241 /* TRB bit mask */
1242 #define TRB_TYPE_BITMASK (0xfc00)
1243 #define TRB_TYPE(p) ((p) << 10)
1244 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1245 /* TRB type IDs */
1246 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1247 #define TRB_NORMAL 1
1248 /* setup stage for control transfers */
1249 #define TRB_SETUP 2
1250 /* data stage for control transfers */
1251 #define TRB_DATA 3
1252 /* status stage for control transfers */
1253 #define TRB_STATUS 4
1254 /* isoc transfers */
1255 #define TRB_ISOC 5
1256 /* TRB for linking ring segments */
1257 #define TRB_LINK 6
1258 #define TRB_EVENT_DATA 7
1259 /* Transfer Ring No-op (not for the command ring) */
1260 #define TRB_TR_NOOP 8
1261 /* Command TRBs */
1262 /* Enable Slot Command */
1263 #define TRB_ENABLE_SLOT 9
1264 /* Disable Slot Command */
1265 #define TRB_DISABLE_SLOT 10
1266 /* Address Device Command */
1267 #define TRB_ADDR_DEV 11
1268 /* Configure Endpoint Command */
1269 #define TRB_CONFIG_EP 12
1270 /* Evaluate Context Command */
1271 #define TRB_EVAL_CONTEXT 13
1272 /* Reset Endpoint Command */
1273 #define TRB_RESET_EP 14
1274 /* Stop Transfer Ring Command */
1275 #define TRB_STOP_RING 15
1276 /* Set Transfer Ring Dequeue Pointer Command */
1277 #define TRB_SET_DEQ 16
1278 /* Reset Device Command */
1279 #define TRB_RESET_DEV 17
1280 /* Force Event Command (opt) */
1281 #define TRB_FORCE_EVENT 18
1282 /* Negotiate Bandwidth Command (opt) */
1283 #define TRB_NEG_BANDWIDTH 19
1284 /* Set Latency Tolerance Value Command (opt) */
1285 #define TRB_SET_LT 20
1286 /* Get port bandwidth Command */
1287 #define TRB_GET_BW 21
1288 /* Force Header Command - generate a transaction or link management packet */
1289 #define TRB_FORCE_HEADER 22
1290 /* No-op Command - not for transfer rings */
1291 #define TRB_CMD_NOOP 23
1292 /* TRB IDs 24-31 reserved */
1293 /* Event TRBS */
1294 /* Transfer Event */
1295 #define TRB_TRANSFER 32
1296 /* Command Completion Event */
1297 #define TRB_COMPLETION 33
1298 /* Port Status Change Event */
1299 #define TRB_PORT_STATUS 34
1300 /* Bandwidth Request Event (opt) */
1301 #define TRB_BANDWIDTH_EVENT 35
1302 /* Doorbell Event (opt) */
1303 #define TRB_DOORBELL 36
1304 /* Host Controller Event */
1305 #define TRB_HC_EVENT 37
1306 /* Device Notification Event - device sent function wake notification */
1307 #define TRB_DEV_NOTE 38
1308 /* MFINDEX Wrap Event - microframe counter wrapped */
1309 #define TRB_MFINDEX_WRAP 39
1310 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1311
1312 /* Nec vendor-specific command completion event. */
1313 #define TRB_NEC_CMD_COMP 48
1314 /* Get NEC firmware revision. */
1315 #define TRB_NEC_GET_FW 49
1316
1317 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1318 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1319 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1320 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1321 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1322 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1323
1324 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1325 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1326
1327 /*
1328 * TRBS_PER_SEGMENT must be a multiple of 4,
1329 * since the command ring is 64-byte aligned.
1330 * It must also be greater than 16.
1331 */
1332 #define TRBS_PER_SEGMENT 256
1333 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1334 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1335 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1336 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1337 /* TRB buffer pointers can't cross 64KB boundaries */
1338 #define TRB_MAX_BUFF_SHIFT 16
1339 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1340
1341 struct xhci_segment {
1342 union xhci_trb *trbs;
1343 /* private to HCD */
1344 struct xhci_segment *next;
1345 dma_addr_t dma;
1346 };
1347
1348 struct xhci_td {
1349 struct list_head td_list;
1350 struct list_head cancelled_td_list;
1351 struct urb *urb;
1352 struct xhci_segment *start_seg;
1353 union xhci_trb *first_trb;
1354 union xhci_trb *last_trb;
1355 /* actual_length of the URB has already been set */
1356 bool urb_length_set;
1357 };
1358
1359 /* xHCI command default timeout value */
1360 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1361
1362 /* command descriptor */
1363 struct xhci_cd {
1364 struct xhci_command *command;
1365 union xhci_trb *cmd_trb;
1366 };
1367
1368 struct xhci_dequeue_state {
1369 struct xhci_segment *new_deq_seg;
1370 union xhci_trb *new_deq_ptr;
1371 int new_cycle_state;
1372 };
1373
1374 enum xhci_ring_type {
1375 TYPE_CTRL = 0,
1376 TYPE_ISOC,
1377 TYPE_BULK,
1378 TYPE_INTR,
1379 TYPE_STREAM,
1380 TYPE_COMMAND,
1381 TYPE_EVENT,
1382 };
1383
1384 struct xhci_ring {
1385 struct xhci_segment *first_seg;
1386 struct xhci_segment *last_seg;
1387 union xhci_trb *enqueue;
1388 struct xhci_segment *enq_seg;
1389 unsigned int enq_updates;
1390 union xhci_trb *dequeue;
1391 struct xhci_segment *deq_seg;
1392 unsigned int deq_updates;
1393 struct list_head td_list;
1394 /*
1395 * Write the cycle state into the TRB cycle field to give ownership of
1396 * the TRB to the host controller (if we are the producer), or to check
1397 * if we own the TRB (if we are the consumer). See section 4.9.1.
1398 */
1399 u32 cycle_state;
1400 unsigned int stream_id;
1401 unsigned int num_segs;
1402 unsigned int num_trbs_free;
1403 unsigned int num_trbs_free_temp;
1404 enum xhci_ring_type type;
1405 bool last_td_was_short;
1406 struct radix_tree_root *trb_address_map;
1407 };
1408
1409 struct xhci_erst_entry {
1410 /* 64-bit event ring segment address */
1411 __le64 seg_addr;
1412 __le32 seg_size;
1413 /* Set to zero */
1414 __le32 rsvd;
1415 };
1416
1417 struct xhci_erst {
1418 struct xhci_erst_entry *entries;
1419 unsigned int num_entries;
1420 /* xhci->event_ring keeps track of segment dma addresses */
1421 dma_addr_t erst_dma_addr;
1422 /* Num entries the ERST can contain */
1423 unsigned int erst_size;
1424 };
1425
1426 struct xhci_scratchpad {
1427 u64 *sp_array;
1428 dma_addr_t sp_dma;
1429 void **sp_buffers;
1430 dma_addr_t *sp_dma_buffers;
1431 };
1432
1433 struct urb_priv {
1434 int length;
1435 int td_cnt;
1436 struct xhci_td *td[0];
1437 };
1438
1439 /*
1440 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1441 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1442 * meaning 64 ring segments.
1443 * Initial allocated size of the ERST, in number of entries */
1444 #define ERST_NUM_SEGS 1
1445 /* Initial allocated size of the ERST, in number of entries */
1446 #define ERST_SIZE 64
1447 /* Initial number of event segment rings allocated */
1448 #define ERST_ENTRIES 1
1449 /* Poll every 60 seconds */
1450 #define POLL_TIMEOUT 60
1451 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1452 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1453 /* XXX: Make these module parameters */
1454
1455 struct s3_save {
1456 u32 command;
1457 u32 dev_nt;
1458 u64 dcbaa_ptr;
1459 u32 config_reg;
1460 u32 irq_pending;
1461 u32 irq_control;
1462 u32 erst_size;
1463 u64 erst_base;
1464 u64 erst_dequeue;
1465 };
1466
1467 /* Use for lpm */
1468 struct dev_info {
1469 u32 dev_id;
1470 struct list_head list;
1471 };
1472
1473 struct xhci_bus_state {
1474 unsigned long bus_suspended;
1475 unsigned long next_statechange;
1476
1477 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1478 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1479 u32 port_c_suspend;
1480 u32 suspended_ports;
1481 u32 port_remote_wakeup;
1482 unsigned long resume_done[USB_MAXCHILDREN];
1483 /* which ports have started to resume */
1484 unsigned long resuming_ports;
1485 /* Which ports are waiting on RExit to U0 transition. */
1486 unsigned long rexit_ports;
1487 struct completion rexit_done[USB_MAXCHILDREN];
1488 };
1489
1490
1491 /*
1492 * It can take up to 20 ms to transition from RExit to U0 on the
1493 * Intel Lynx Point LP xHCI host.
1494 */
1495 #define XHCI_MAX_REXIT_TIMEOUT_MS 20
1496
hcd_index(struct usb_hcd * hcd)1497 static inline unsigned int hcd_index(struct usb_hcd *hcd)
1498 {
1499 if (hcd->speed >= HCD_USB3)
1500 return 0;
1501 else
1502 return 1;
1503 }
1504
1505 struct xhci_hub {
1506 u8 maj_rev;
1507 u8 min_rev;
1508 u32 *psi; /* array of protocol speed ID entries */
1509 u8 psi_count;
1510 u8 psi_uid_count;
1511 };
1512
1513 /* There is one xhci_hcd structure per controller */
1514 struct xhci_hcd {
1515 struct usb_hcd *main_hcd;
1516 struct usb_hcd *shared_hcd;
1517 /* glue to PCI and HCD framework */
1518 struct xhci_cap_regs __iomem *cap_regs;
1519 struct xhci_op_regs __iomem *op_regs;
1520 struct xhci_run_regs __iomem *run_regs;
1521 struct xhci_doorbell_array __iomem *dba;
1522 /* Our HCD's current interrupter register set */
1523 struct xhci_intr_reg __iomem *ir_set;
1524
1525 /* Cached register copies of read-only HC data */
1526 __u32 hcs_params1;
1527 __u32 hcs_params2;
1528 __u32 hcs_params3;
1529 __u32 hcc_params;
1530 __u32 hcc_params2;
1531
1532 spinlock_t lock;
1533
1534 /* packed release number */
1535 u8 sbrn;
1536 u16 hci_version;
1537 u8 max_slots;
1538 u8 max_interrupters;
1539 u8 max_ports;
1540 u8 isoc_threshold;
1541 int event_ring_max;
1542 int addr_64;
1543 /* 4KB min, 128MB max */
1544 int page_size;
1545 /* Valid values are 12 to 20, inclusive */
1546 int page_shift;
1547 /* msi-x vectors */
1548 int msix_count;
1549 struct msix_entry *msix_entries;
1550 /* optional clock */
1551 struct clk *clk;
1552 /* data structures */
1553 struct xhci_device_context_array *dcbaa;
1554 struct xhci_ring *cmd_ring;
1555 unsigned int cmd_ring_state;
1556 #define CMD_RING_STATE_RUNNING (1 << 0)
1557 #define CMD_RING_STATE_ABORTED (1 << 1)
1558 #define CMD_RING_STATE_STOPPED (1 << 2)
1559 struct list_head cmd_list;
1560 unsigned int cmd_ring_reserved_trbs;
1561 struct delayed_work cmd_timer;
1562 struct completion cmd_ring_stop_completion;
1563 struct xhci_command *current_cmd;
1564 struct xhci_ring *event_ring;
1565 struct xhci_erst erst;
1566 /* Scratchpad */
1567 struct xhci_scratchpad *scratchpad;
1568 /* Store LPM test failed devices' information */
1569 struct list_head lpm_failed_devs;
1570
1571 /* slot enabling and address device helpers */
1572 /* these are not thread safe so use mutex */
1573 struct mutex mutex;
1574 struct completion addr_dev;
1575 int slot_id;
1576 /* For USB 3.0 LPM enable/disable. */
1577 struct xhci_command *lpm_command;
1578 /* Internal mirror of the HW's dcbaa */
1579 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1580 /* For keeping track of bandwidth domains per roothub. */
1581 struct xhci_root_port_bw_info *rh_bw;
1582
1583 /* DMA pools */
1584 struct dma_pool *device_pool;
1585 struct dma_pool *segment_pool;
1586 struct dma_pool *small_streams_pool;
1587 struct dma_pool *medium_streams_pool;
1588
1589 /* Host controller watchdog timer structures */
1590 unsigned int xhc_state;
1591
1592 u32 command;
1593 struct s3_save s3;
1594 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1595 *
1596 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1597 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1598 * that sees this status (other than the timer that set it) should stop touching
1599 * hardware immediately. Interrupt handlers should return immediately when
1600 * they see this status (any time they drop and re-acquire xhci->lock).
1601 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1602 * putting the TD on the canceled list, etc.
1603 *
1604 * There are no reports of xHCI host controllers that display this issue.
1605 */
1606 #define XHCI_STATE_DYING (1 << 0)
1607 #define XHCI_STATE_HALTED (1 << 1)
1608 #define XHCI_STATE_REMOVING (1 << 2)
1609 /* Statistics */
1610 int error_bitmask;
1611 unsigned int quirks;
1612 #define XHCI_LINK_TRB_QUIRK (1 << 0)
1613 #define XHCI_RESET_EP_QUIRK (1 << 1)
1614 #define XHCI_NEC_HOST (1 << 2)
1615 #define XHCI_AMD_PLL_FIX (1 << 3)
1616 #define XHCI_SPURIOUS_SUCCESS (1 << 4)
1617 /*
1618 * Certain Intel host controllers have a limit to the number of endpoint
1619 * contexts they can handle. Ideally, they would signal that they can't handle
1620 * anymore endpoint contexts by returning a Resource Error for the Configure
1621 * Endpoint command, but they don't. Instead they expect software to keep track
1622 * of the number of active endpoints for them, across configure endpoint
1623 * commands, reset device commands, disable slot commands, and address device
1624 * commands.
1625 */
1626 #define XHCI_EP_LIMIT_QUIRK (1 << 5)
1627 #define XHCI_BROKEN_MSI (1 << 6)
1628 #define XHCI_RESET_ON_RESUME (1 << 7)
1629 #define XHCI_SW_BW_CHECKING (1 << 8)
1630 #define XHCI_AMD_0x96_HOST (1 << 9)
1631 #define XHCI_TRUST_TX_LENGTH (1 << 10)
1632 #define XHCI_LPM_SUPPORT (1 << 11)
1633 #define XHCI_INTEL_HOST (1 << 12)
1634 #define XHCI_SPURIOUS_REBOOT (1 << 13)
1635 #define XHCI_COMP_MODE_QUIRK (1 << 14)
1636 #define XHCI_AVOID_BEI (1 << 15)
1637 #define XHCI_PLAT (1 << 16)
1638 #define XHCI_SLOW_SUSPEND (1 << 17)
1639 #define XHCI_SPURIOUS_WAKEUP (1 << 18)
1640 /* For controllers with a broken beyond repair streams implementation */
1641 #define XHCI_BROKEN_STREAMS (1 << 19)
1642 #define XHCI_PME_STUCK_QUIRK (1 << 20)
1643 #define XHCI_MISSING_CAS (1 << 24)
1644 unsigned int num_active_eps;
1645 unsigned int limit_active_eps;
1646 /* There are two roothubs to keep track of bus suspend info for */
1647 struct xhci_bus_state bus_state[2];
1648 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1649 u8 *port_array;
1650 /* Array of pointers to USB 3.0 PORTSC registers */
1651 __le32 __iomem **usb3_ports;
1652 unsigned int num_usb3_ports;
1653 /* Array of pointers to USB 2.0 PORTSC registers */
1654 __le32 __iomem **usb2_ports;
1655 struct xhci_hub usb2_rhub;
1656 struct xhci_hub usb3_rhub;
1657 unsigned int num_usb2_ports;
1658 /* support xHCI 0.96 spec USB2 software LPM */
1659 unsigned sw_lpm_support:1;
1660 /* support xHCI 1.0 spec USB2 hardware LPM */
1661 unsigned hw_lpm_support:1;
1662 /* cached usb2 extened protocol capabilites */
1663 u32 *ext_caps;
1664 unsigned int num_ext_caps;
1665 /* Compliance Mode Recovery Data */
1666 struct timer_list comp_mode_recovery_timer;
1667 u32 port_status_u0;
1668 /* Compliance Mode Timer Triggered every 2 seconds */
1669 #define COMP_MODE_RCVRY_MSECS 2000
1670 };
1671
1672 /* Platform specific overrides to generic XHCI hc_driver ops */
1673 struct xhci_driver_overrides {
1674 size_t extra_priv_size;
1675 int (*reset)(struct usb_hcd *hcd);
1676 int (*start)(struct usb_hcd *hcd);
1677 };
1678
1679 #define XHCI_CFC_DELAY 10
1680
1681 /* convert between an HCD pointer and the corresponding EHCI_HCD */
hcd_to_xhci(struct usb_hcd * hcd)1682 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1683 {
1684 struct usb_hcd *primary_hcd;
1685
1686 if (usb_hcd_is_primary_hcd(hcd))
1687 primary_hcd = hcd;
1688 else
1689 primary_hcd = hcd->primary_hcd;
1690
1691 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1692 }
1693
xhci_to_hcd(struct xhci_hcd * xhci)1694 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1695 {
1696 return xhci->main_hcd;
1697 }
1698
1699 #define xhci_dbg(xhci, fmt, args...) \
1700 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1701 #define xhci_err(xhci, fmt, args...) \
1702 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1703 #define xhci_warn(xhci, fmt, args...) \
1704 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1705 #define xhci_warn_ratelimited(xhci, fmt, args...) \
1706 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1707 #define xhci_info(xhci, fmt, args...) \
1708 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1709
1710 /*
1711 * Registers should always be accessed with double word or quad word accesses.
1712 *
1713 * Some xHCI implementations may support 64-bit address pointers. Registers
1714 * with 64-bit address pointers should be written to with dword accesses by
1715 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1716 * xHCI implementations that do not support 64-bit address pointers will ignore
1717 * the high dword, and write order is irrelevant.
1718 */
xhci_read_64(const struct xhci_hcd * xhci,__le64 __iomem * regs)1719 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1720 __le64 __iomem *regs)
1721 {
1722 return lo_hi_readq(regs);
1723 }
xhci_write_64(struct xhci_hcd * xhci,const u64 val,__le64 __iomem * regs)1724 static inline void xhci_write_64(struct xhci_hcd *xhci,
1725 const u64 val, __le64 __iomem *regs)
1726 {
1727 lo_hi_writeq(val, regs);
1728 }
1729
xhci_link_trb_quirk(struct xhci_hcd * xhci)1730 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1731 {
1732 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1733 }
1734
1735 /* xHCI debugging */
1736 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1737 void xhci_print_registers(struct xhci_hcd *xhci);
1738 void xhci_dbg_regs(struct xhci_hcd *xhci);
1739 void xhci_print_run_regs(struct xhci_hcd *xhci);
1740 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1741 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1742 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1743 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1744 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1745 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1746 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1747 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1748 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1749 struct xhci_container_ctx *ctx);
1750 void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1751 unsigned int slot_id, unsigned int ep_index,
1752 struct xhci_virt_ep *ep);
1753 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1754 const char *fmt, ...);
1755
1756 /* xHCI memory management */
1757 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1758 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1759 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1760 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1761 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1762 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1763 struct usb_device *udev);
1764 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1765 unsigned int xhci_get_endpoint_address(unsigned int ep_index);
1766 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1767 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1768 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1769 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1770 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
1771 struct xhci_bw_info *ep_bw,
1772 struct xhci_interval_bw_table *bw_table,
1773 struct usb_device *udev,
1774 struct xhci_virt_ep *virt_ep,
1775 struct xhci_tt_bw_info *tt_info);
1776 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1777 struct xhci_virt_device *virt_dev,
1778 int old_active_eps);
1779 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1780 void xhci_update_bw_info(struct xhci_hcd *xhci,
1781 struct xhci_container_ctx *in_ctx,
1782 struct xhci_input_control_ctx *ctrl_ctx,
1783 struct xhci_virt_device *virt_dev);
1784 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1785 struct xhci_container_ctx *in_ctx,
1786 struct xhci_container_ctx *out_ctx,
1787 unsigned int ep_index);
1788 void xhci_slot_copy(struct xhci_hcd *xhci,
1789 struct xhci_container_ctx *in_ctx,
1790 struct xhci_container_ctx *out_ctx);
1791 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1792 struct usb_device *udev, struct usb_host_endpoint *ep,
1793 gfp_t mem_flags);
1794 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1795 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1796 unsigned int num_trbs, gfp_t flags);
1797 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1798 struct xhci_virt_device *virt_dev,
1799 unsigned int ep_index);
1800 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1801 unsigned int num_stream_ctxs,
1802 unsigned int num_streams, gfp_t flags);
1803 void xhci_free_stream_info(struct xhci_hcd *xhci,
1804 struct xhci_stream_info *stream_info);
1805 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1806 struct xhci_ep_ctx *ep_ctx,
1807 struct xhci_stream_info *stream_info);
1808 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
1809 struct xhci_virt_ep *ep);
1810 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1811 struct xhci_virt_device *virt_dev, bool drop_control_ep);
1812 struct xhci_ring *xhci_dma_to_transfer_ring(
1813 struct xhci_virt_ep *ep,
1814 u64 address);
1815 struct xhci_ring *xhci_stream_id_to_ring(
1816 struct xhci_virt_device *dev,
1817 unsigned int ep_index,
1818 unsigned int stream_id);
1819 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1820 bool allocate_in_ctx, bool allocate_completion,
1821 gfp_t mem_flags);
1822 void xhci_urb_free_priv(struct urb_priv *urb_priv);
1823 void xhci_free_command(struct xhci_hcd *xhci,
1824 struct xhci_command *command);
1825
1826 /* xHCI host controller glue */
1827 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1828 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec);
1829 void xhci_quiesce(struct xhci_hcd *xhci);
1830 int xhci_halt(struct xhci_hcd *xhci);
1831 int xhci_reset(struct xhci_hcd *xhci);
1832 int xhci_init(struct usb_hcd *hcd);
1833 int xhci_run(struct usb_hcd *hcd);
1834 void xhci_stop(struct usb_hcd *hcd);
1835 void xhci_shutdown(struct usb_hcd *hcd);
1836 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1837 void xhci_shutdown(struct usb_hcd *hcd);
1838 void xhci_init_driver(struct hc_driver *drv,
1839 const struct xhci_driver_overrides *over);
1840
1841 #ifdef CONFIG_PM
1842 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
1843 int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1844 #else
1845 #define xhci_suspend NULL
1846 #define xhci_resume NULL
1847 #endif
1848
1849 int xhci_get_frame(struct usb_hcd *hcd);
1850 irqreturn_t xhci_irq(struct usb_hcd *hcd);
1851 irqreturn_t xhci_msi_irq(int irq, void *hcd);
1852 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1853 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1854 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1855 struct xhci_virt_device *virt_dev,
1856 struct usb_device *hdev,
1857 struct usb_tt *tt, gfp_t mem_flags);
1858 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1859 struct usb_host_endpoint **eps, unsigned int num_eps,
1860 unsigned int num_streams, gfp_t mem_flags);
1861 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1862 struct usb_host_endpoint **eps, unsigned int num_eps,
1863 gfp_t mem_flags);
1864 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1865 int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev);
1866 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev);
1867 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
1868 struct usb_device *udev, int enable);
1869 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1870 struct usb_tt *tt, gfp_t mem_flags);
1871 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1872 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1873 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1874 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1875 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1876 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1877 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1878 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1879
1880 /* xHCI ring, segment, TRB, and TD functions */
1881 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1882 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1883 struct xhci_segment *start_seg, union xhci_trb *start_trb,
1884 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
1885 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1886 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1887 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
1888 u32 trb_type, u32 slot_id);
1889 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1890 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
1891 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
1892 u32 field1, u32 field2, u32 field3, u32 field4);
1893 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
1894 int slot_id, unsigned int ep_index, int suspend);
1895 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1896 int slot_id, unsigned int ep_index);
1897 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1898 int slot_id, unsigned int ep_index);
1899 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1900 int slot_id, unsigned int ep_index);
1901 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1902 struct urb *urb, int slot_id, unsigned int ep_index);
1903 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
1904 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
1905 bool command_must_succeed);
1906 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
1907 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
1908 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
1909 int slot_id, unsigned int ep_index);
1910 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1911 u32 slot_id);
1912 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1913 unsigned int slot_id, unsigned int ep_index,
1914 unsigned int stream_id, struct xhci_td *cur_td,
1915 struct xhci_dequeue_state *state);
1916 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1917 unsigned int slot_id, unsigned int ep_index,
1918 unsigned int stream_id,
1919 struct xhci_dequeue_state *deq_state);
1920 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1921 unsigned int ep_index, struct xhci_td *td);
1922 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1923 unsigned int slot_id, unsigned int ep_index,
1924 struct xhci_dequeue_state *deq_state);
1925 void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1926 void xhci_handle_command_timeout(struct work_struct *work);
1927
1928 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1929 unsigned int ep_index, unsigned int stream_id);
1930 void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
1931
1932 /* xHCI roothub code */
1933 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1934 int port_id, u32 link_state);
1935 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
1936 struct usb_device *udev, enum usb3_link_state state);
1937 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
1938 struct usb_device *udev, enum usb3_link_state state);
1939 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1940 int port_id, u32 port_bit);
1941 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1942 char *buf, u16 wLength);
1943 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1944 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
1945
1946 #ifdef CONFIG_PM
1947 int xhci_bus_suspend(struct usb_hcd *hcd);
1948 int xhci_bus_resume(struct usb_hcd *hcd);
1949 #else
1950 #define xhci_bus_suspend NULL
1951 #define xhci_bus_resume NULL
1952 #endif /* CONFIG_PM */
1953
1954 u32 xhci_port_state_to_neutral(u32 state);
1955 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1956 u16 port);
1957 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1958
1959 /* xHCI contexts */
1960 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
1961 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1962 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1963
1964 #endif /* __LINUX_XHCI_HCD_H */
1965