| /drivers/clk/hisilicon/ |
| D | clk-hi3620.c | 298 struct clk_mmc *mclk = to_mmc(hw); in mmc_clk_determine_rate() local
337 struct clk_mmc *mclk = to_mmc(hw); in mmc_clk_set_timing() local
401 struct clk_mmc *mclk = to_mmc(hw); in mmc_clk_prepare() local
428 struct clk_mmc *mclk; in hisi_register_clk_mmc() local
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| /drivers/staging/iio/frequency/ |
| D | ad9834.h | 56 unsigned int mclk; member
91 unsigned int mclk; member
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| D | ad9832.h | 80 unsigned long mclk; member
117 unsigned long mclk; member
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| D | ad9832.c | 25 static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout) in ad9832_calc_freqreg()
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| D | ad9834.c | 28 static unsigned int ad9834_calc_freqreg(unsigned long mclk, unsigned long fout) in ad9834_calc_freqreg()
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| /drivers/media/dvb-frontends/ |
| D | stv0900_sw.c | 309 u32 mclk, in stv0900_get_symbol_rate()
337 u32 mclk, u32 srate, in stv0900_set_symbol_rate()
361 u32 mclk, u32 srate, in stv0900_set_max_symbol_rate()
389 u32 mclk, u32 srate, in stv0900_set_min_symbol_rate()
1139 static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk, in stv0900_get_carr_freq()
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| D | m88rs2000.c | 116 u32 mclk; in m88rs2000_get_mclk() local
134 u32 mclk; in m88rs2000_set_carrieroffset() local
164 u32 mclk; in m88rs2000_set_symbolrate() local
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| D | stv6110.h | 44 u32 mclk; member
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| D | stv0299.h | 71 u32 mclk; member
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| D | stb0899_drv.c | 566 u32 mclk = 0, div = 0; in stb0899_get_mclk() local
842 u32 mclk, tx_freq = 22000;/* count = 0, i; */ in stb0899_diseqc_init() local
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| D | stv6110.c | 42 u32 mclk; member
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| D | stv0900_core.c | 287 u32 mclk = 90000000, div = 0, ad_div = 0; in stv0900_get_mclk_freq() local
299 static enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *intp, u32 mclk) in stv0900_set_mclk()
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| /drivers/mfd/ |
| D | sm501.c | 392 unsigned long mclk; member
408 unsigned long mclk, in sm501_calc_clock()
453 unsigned long mclk; in sm501_calc_pll() local
491 unsigned long mclk; in sm501_select_clock() local
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| /drivers/gpu/drm/radeon/ |
| D | radeon_clocks.c | 68 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local
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| D | ci_dpm.c | 799 u32 sclk, mclk; in ci_apply_state_adjust_rules() local
2283 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, in ci_populate_mvdd_value()
2374 u32 mclk, in ci_populate_phase_value_based_on_mclk()
2500 u32 mclk, in ci_populate_memory_timing_parameters()
2766 SMU7_Discrete_MemoryLevel *mclk, in ci_calculate_mclk_params()
3839 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; in ci_find_dpm_states_clocks_in_dpm_table() local
3876 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; in ci_populate_and_upload_sclk_mclk_dpm_levels() local
5589 u32 sclk, mclk; in ci_parse_power_table() local
5904 u32 mclk = ci_get_average_mclk_freq(rdev); in ci_dpm_debugfs_print_current_performance_level() local
5939 u32 mclk = ci_get_average_mclk_freq(rdev); in ci_dpm_get_current_mclk() local
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| D | cypress_dpm.c | 423 u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) in cypress_get_strobe_mode_settings()
475 RV7XX_SMC_MCLK_VALUE *mclk, in cypress_populate_mclk_value()
652 u32 mclk, in cypress_populate_mvdd_value()
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| D | rv740_dpm.c | 189 RV7XX_SMC_MCLK_VALUE *mclk) in rv740_populate_mclk_value()
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| D | rv730_dpm.c | 121 LPRV7XX_SMC_MCLK_VALUE mclk) in rv730_populate_mclk_value()
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| D | rv6xx_dpm.h | 81 u32 mclk; member
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| D | si_dpm.c | 2996 u32 mclk, sclk; in si_apply_state_adjust_rules() local
3910 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) in si_get_strobe_mode_settings()
4181 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, in si_populate_mvdd_value()
4261 u16 voltage, u32 sclk, u32 mclk, in si_populate_phase_shedding_value()
4926 SISLANDS_SMC_MCLK_VALUE *mclk, in si_populate_mclk_value()
6932 u32 sclk, mclk; in si_parse_power_table() local
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | ci_dpm.c | 916 u32 sclk, mclk; in ci_apply_state_adjust_rules() local
2414 static int ci_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk, in ci_populate_mvdd_value()
2505 u32 mclk, in ci_populate_phase_value_based_on_mclk()
2630 u32 mclk, in ci_populate_memory_timing_parameters()
2896 SMU7_Discrete_MemoryLevel *mclk, in ci_calculate_mclk_params()
3977 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; in ci_find_dpm_states_clocks_in_dpm_table() local
4014 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; in ci_populate_and_upload_sclk_mclk_dpm_levels() local
5736 u32 sclk, mclk; in ci_parse_power_table() local
6092 u32 mclk = ci_get_average_mclk_freq(adev); in ci_dpm_debugfs_print_current_performance_level() local
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| D | amdgpu_atombios.h | 96 u32 mclk[MAX_AC_TIMING_ENTRIES]; member
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| /drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | ramgt215.c | 456 gt215_ram_lock_pll(struct gt215_ramfuc *fuc, struct gt215_clk_info *mclk) in gt215_ram_lock_pll()
500 struct gt215_clk_info mclk; in gt215_ram_calc() local
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| /drivers/spi/ |
| D | spi-sun4i.c | 80 struct clk *mclk; member
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| D | spi-sun6i.c | 85 struct clk *mclk; member
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