• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /*
2  * DMA C definitions and help macros
3  *
4  */
5 
6 #ifndef dma_h
7 #define dma_h
8 
9 /* registers */ /* Really needed, since both are listed in sw.list? */
10 #include <arch/hwregs/dma_defs.h>
11 
12 
13 /* descriptors */
14 
15 // ------------------------------------------------------------ dma_descr_group
16 typedef struct dma_descr_group {
17   struct dma_descr_group       *next;
18   unsigned                      eol        : 1;
19   unsigned                      tol        : 1;
20   unsigned                      bol        : 1;
21   unsigned                                 : 1;
22   unsigned                      intr       : 1;
23   unsigned                                 : 2;
24   unsigned                      en         : 1;
25   unsigned                                 : 7;
26   unsigned                      dis        : 1;
27   unsigned                      md         : 16;
28   struct dma_descr_group       *up;
29   union {
30     struct dma_descr_context   *context;
31     struct dma_descr_group     *group;
32   }                             down;
33 } dma_descr_group;
34 
35 // ---------------------------------------------------------- dma_descr_context
36 typedef struct dma_descr_context {
37   struct dma_descr_context     *next;
38   unsigned                      eol        : 1;
39   unsigned                                 : 3;
40   unsigned                      intr       : 1;
41   unsigned                                 : 1;
42   unsigned                      store_mode : 1;
43   unsigned                      en         : 1;
44   unsigned                                 : 7;
45   unsigned                      dis        : 1;
46   unsigned                      md0        : 16;
47   unsigned                      md1;
48   unsigned                      md2;
49   unsigned                      md3;
50   unsigned                      md4;
51   struct dma_descr_data        *saved_data;
52   char                         *saved_data_buf;
53 } dma_descr_context;
54 
55 // ------------------------------------------------------------- dma_descr_data
56 typedef struct dma_descr_data {
57   struct dma_descr_data        *next;
58   char                         *buf;
59   unsigned                      eol        : 1;
60   unsigned                                 : 2;
61   unsigned                      out_eop    : 1;
62   unsigned                      intr       : 1;
63   unsigned                      wait       : 1;
64   unsigned                                 : 2;
65   unsigned                                 : 3;
66   unsigned                      in_eop     : 1;
67   unsigned                                 : 4;
68   unsigned                      md         : 16;
69   char                         *after;
70 } dma_descr_data;
71 
72 // --------------------------------------------------------------------- macros
73 
74 // enable DMA channel
75 #define DMA_ENABLE( inst ) \
76    do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\
77         e.en = regk_dma_yes; \
78         REG_WR( dma, inst, rw_cfg, e); } while( 0 )
79 
80 // reset DMA channel
81 #define DMA_RESET( inst ) \
82    do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\
83         r.en = regk_dma_no; \
84         REG_WR( dma, inst, rw_cfg, r); } while( 0 )
85 
86 // stop DMA channel
87 #define DMA_STOP( inst ) \
88    do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\
89         s.stop = regk_dma_yes; \
90         REG_WR( dma, inst, rw_cfg, s); } while( 0 )
91 
92 // continue DMA channel operation
93 #define DMA_CONTINUE( inst ) \
94    do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\
95         c.stop = regk_dma_no; \
96         REG_WR( dma, inst, rw_cfg, c); } while( 0 )
97 
98 // give stream command
99 #define DMA_WR_CMD( inst, cmd_par ) \
100    do { reg_dma_rw_stream_cmd __x = {0}; \
101 	do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \
102 	__x.cmd = (cmd_par); \
103 	REG_WR(dma, inst, rw_stream_cmd, __x); \
104    } while (0)
105 
106 // load: g,c,d:burst
107 #define DMA_START_GROUP( inst, group_descr ) \
108    do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \
109         DMA_WR_CMD( inst, regk_dma_load_g ); \
110         DMA_WR_CMD( inst, regk_dma_load_c ); \
111         DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
112       } while( 0 )
113 
114 // load: c,d:burst
115 #define DMA_START_CONTEXT( inst, ctx_descr ) \
116    do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \
117         DMA_WR_CMD( inst, regk_dma_load_c ); \
118         DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
119       } while( 0 )
120 
121 // if the DMA is at the end of the data list, the last data descr is reloaded
122 #define DMA_CONTINUE_DATA( inst ) \
123 do { reg_dma_rw_cmd c = {0}; \
124      c.cont_data = regk_dma_yes;\
125      REG_WR( dma, inst, rw_cmd, c ); } while( 0 )
126 
127 #endif
128