1 /*
2 * Copyright 2010 Matt Turner.
3 * Copyright 2012 Red Hat
4 *
5 * This file is subject to the terms and conditions of the GNU General
6 * Public License version 2. See the file COPYING in the main
7 * directory of this archive for more details.
8 *
9 * Authors: Matthew Garrett
10 * Matt Turner
11 * Dave Airlie
12 */
13
14 #include <linux/delay.h>
15
16 #include <drm/drmP.h>
17 #include <drm/drm_crtc_helper.h>
18 #include <drm/drm_plane_helper.h>
19
20 #include "mgag200_drv.h"
21
22 #define MGAG200_LUT_SIZE 256
23
24 /*
25 * This file contains setup code for the CRTC.
26 */
27
mga_crtc_load_lut(struct drm_crtc * crtc)28 static void mga_crtc_load_lut(struct drm_crtc *crtc)
29 {
30 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
31 struct drm_device *dev = crtc->dev;
32 struct mga_device *mdev = dev->dev_private;
33 struct drm_framebuffer *fb = crtc->primary->fb;
34 int i;
35
36 if (!crtc->enabled)
37 return;
38
39 WREG8(DAC_INDEX + MGA1064_INDEX, 0);
40
41 if (fb && fb->bits_per_pixel == 16) {
42 int inc = (fb->depth == 15) ? 8 : 4;
43 u8 r, b;
44 for (i = 0; i < MGAG200_LUT_SIZE; i += inc) {
45 if (fb->depth == 16) {
46 if (i > (MGAG200_LUT_SIZE >> 1)) {
47 r = b = 0;
48 } else {
49 r = mga_crtc->lut_r[i << 1];
50 b = mga_crtc->lut_b[i << 1];
51 }
52 } else {
53 r = mga_crtc->lut_r[i];
54 b = mga_crtc->lut_b[i];
55 }
56 /* VGA registers */
57 WREG8(DAC_INDEX + MGA1064_COL_PAL, r);
58 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
59 WREG8(DAC_INDEX + MGA1064_COL_PAL, b);
60 }
61 return;
62 }
63 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
64 /* VGA registers */
65 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_r[i]);
66 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
67 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_b[i]);
68 }
69 }
70
mga_wait_vsync(struct mga_device * mdev)71 static inline void mga_wait_vsync(struct mga_device *mdev)
72 {
73 unsigned long timeout = jiffies + HZ/10;
74 unsigned int status = 0;
75
76 do {
77 status = RREG32(MGAREG_Status);
78 } while ((status & 0x08) && time_before(jiffies, timeout));
79 timeout = jiffies + HZ/10;
80 status = 0;
81 do {
82 status = RREG32(MGAREG_Status);
83 } while (!(status & 0x08) && time_before(jiffies, timeout));
84 }
85
mga_wait_busy(struct mga_device * mdev)86 static inline void mga_wait_busy(struct mga_device *mdev)
87 {
88 unsigned long timeout = jiffies + HZ;
89 unsigned int status = 0;
90 do {
91 status = RREG8(MGAREG_Status + 2);
92 } while ((status & 0x01) && time_before(jiffies, timeout));
93 }
94
95 /*
96 * The core passes the desired mode to the CRTC code to see whether any
97 * CRTC-specific modifications need to be made to it. We're in a position
98 * to just pass that straight through, so this does nothing
99 */
mga_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)100 static bool mga_crtc_mode_fixup(struct drm_crtc *crtc,
101 const struct drm_display_mode *mode,
102 struct drm_display_mode *adjusted_mode)
103 {
104 return true;
105 }
106
107 #define P_ARRAY_SIZE 9
108
mga_g200se_set_plls(struct mga_device * mdev,long clock)109 static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
110 {
111 unsigned int vcomax, vcomin, pllreffreq;
112 unsigned int delta, tmpdelta, permitteddelta;
113 unsigned int testp, testm, testn;
114 unsigned int p, m, n;
115 unsigned int computed;
116 unsigned int pvalues_e4[P_ARRAY_SIZE] = {16, 14, 12, 10, 8, 6, 4, 2, 1};
117 unsigned int fvv;
118 unsigned int i;
119
120 if (mdev->unique_rev_id <= 0x03) {
121
122 m = n = p = 0;
123 vcomax = 320000;
124 vcomin = 160000;
125 pllreffreq = 25000;
126
127 delta = 0xffffffff;
128 permitteddelta = clock * 5 / 1000;
129
130 for (testp = 8; testp > 0; testp /= 2) {
131 if (clock * testp > vcomax)
132 continue;
133 if (clock * testp < vcomin)
134 continue;
135
136 for (testn = 17; testn < 256; testn++) {
137 for (testm = 1; testm < 32; testm++) {
138 computed = (pllreffreq * testn) /
139 (testm * testp);
140 if (computed > clock)
141 tmpdelta = computed - clock;
142 else
143 tmpdelta = clock - computed;
144 if (tmpdelta < delta) {
145 delta = tmpdelta;
146 m = testm - 1;
147 n = testn - 1;
148 p = testp - 1;
149 }
150 }
151 }
152 }
153 } else {
154
155
156 m = n = p = 0;
157 vcomax = 1600000;
158 vcomin = 800000;
159 pllreffreq = 25000;
160
161 if (clock < 25000)
162 clock = 25000;
163
164 clock = clock * 2;
165
166 delta = 0xFFFFFFFF;
167 /* Permited delta is 0.5% as VESA Specification */
168 permitteddelta = clock * 5 / 1000;
169
170 for (i = 0 ; i < P_ARRAY_SIZE ; i++) {
171 testp = pvalues_e4[i];
172
173 if ((clock * testp) > vcomax)
174 continue;
175 if ((clock * testp) < vcomin)
176 continue;
177
178 for (testn = 50; testn <= 256; testn++) {
179 for (testm = 1; testm <= 32; testm++) {
180 computed = (pllreffreq * testn) /
181 (testm * testp);
182 if (computed > clock)
183 tmpdelta = computed - clock;
184 else
185 tmpdelta = clock - computed;
186
187 if (tmpdelta < delta) {
188 delta = tmpdelta;
189 m = testm - 1;
190 n = testn - 1;
191 p = testp - 1;
192 }
193 }
194 }
195 }
196
197 fvv = pllreffreq * (n + 1) / (m + 1);
198 fvv = (fvv - 800000) / 50000;
199
200 if (fvv > 15)
201 fvv = 15;
202
203 p |= (fvv << 4);
204 m |= 0x80;
205
206 clock = clock / 2;
207 }
208
209 if (delta > permitteddelta) {
210 printk(KERN_WARNING "PLL delta too large\n");
211 return 1;
212 }
213
214 WREG_DAC(MGA1064_PIX_PLLC_M, m);
215 WREG_DAC(MGA1064_PIX_PLLC_N, n);
216 WREG_DAC(MGA1064_PIX_PLLC_P, p);
217
218 if (mdev->unique_rev_id >= 0x04) {
219 WREG_DAC(0x1a, 0x09);
220 msleep(20);
221 WREG_DAC(0x1a, 0x01);
222
223 }
224
225 return 0;
226 }
227
mga_g200wb_set_plls(struct mga_device * mdev,long clock)228 static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
229 {
230 unsigned int vcomax, vcomin, pllreffreq;
231 unsigned int delta, tmpdelta;
232 unsigned int testp, testm, testn, testp2;
233 unsigned int p, m, n;
234 unsigned int computed;
235 int i, j, tmpcount, vcount;
236 bool pll_locked = false;
237 u8 tmp;
238
239 m = n = p = 0;
240
241 delta = 0xffffffff;
242
243 if (mdev->type == G200_EW3) {
244
245 vcomax = 800000;
246 vcomin = 400000;
247 pllreffreq = 25000;
248
249 for (testp = 1; testp < 8; testp++) {
250 for (testp2 = 1; testp2 < 8; testp2++) {
251 if (testp < testp2)
252 continue;
253 if ((clock * testp * testp2) > vcomax)
254 continue;
255 if ((clock * testp * testp2) < vcomin)
256 continue;
257 for (testm = 1; testm < 26; testm++) {
258 for (testn = 32; testn < 2048 ; testn++) {
259 computed = (pllreffreq * testn) /
260 (testm * testp * testp2);
261 if (computed > clock)
262 tmpdelta = computed - clock;
263 else
264 tmpdelta = clock - computed;
265 if (tmpdelta < delta) {
266 delta = tmpdelta;
267 m = ((testn & 0x100) >> 1) |
268 (testm);
269 n = (testn & 0xFF);
270 p = ((testn & 0x600) >> 3) |
271 (testp2 << 3) |
272 (testp);
273 }
274 }
275 }
276 }
277 }
278 } else {
279
280 vcomax = 550000;
281 vcomin = 150000;
282 pllreffreq = 48000;
283
284 for (testp = 1; testp < 9; testp++) {
285 if (clock * testp > vcomax)
286 continue;
287 if (clock * testp < vcomin)
288 continue;
289
290 for (testm = 1; testm < 17; testm++) {
291 for (testn = 1; testn < 151; testn++) {
292 computed = (pllreffreq * testn) /
293 (testm * testp);
294 if (computed > clock)
295 tmpdelta = computed - clock;
296 else
297 tmpdelta = clock - computed;
298 if (tmpdelta < delta) {
299 delta = tmpdelta;
300 n = testn - 1;
301 m = (testm - 1) |
302 ((n >> 1) & 0x80);
303 p = testp - 1;
304 }
305 }
306 }
307 }
308 }
309
310 for (i = 0; i <= 32 && pll_locked == false; i++) {
311 if (i > 0) {
312 WREG8(MGAREG_CRTC_INDEX, 0x1e);
313 tmp = RREG8(MGAREG_CRTC_DATA);
314 if (tmp < 0xff)
315 WREG8(MGAREG_CRTC_DATA, tmp+1);
316 }
317
318 /* set pixclkdis to 1 */
319 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
320 tmp = RREG8(DAC_DATA);
321 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
322 WREG8(DAC_DATA, tmp);
323
324 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
325 tmp = RREG8(DAC_DATA);
326 tmp |= MGA1064_REMHEADCTL_CLKDIS;
327 WREG8(DAC_DATA, tmp);
328
329 /* select PLL Set C */
330 tmp = RREG8(MGAREG_MEM_MISC_READ);
331 tmp |= 0x3 << 2;
332 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
333
334 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
335 tmp = RREG8(DAC_DATA);
336 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
337 WREG8(DAC_DATA, tmp);
338
339 udelay(500);
340
341 /* reset the PLL */
342 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
343 tmp = RREG8(DAC_DATA);
344 tmp &= ~0x04;
345 WREG8(DAC_DATA, tmp);
346
347 udelay(50);
348
349 /* program pixel pll register */
350 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
351 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
352 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
353
354 udelay(50);
355
356 /* turn pll on */
357 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
358 tmp = RREG8(DAC_DATA);
359 tmp |= 0x04;
360 WREG_DAC(MGA1064_VREF_CTL, tmp);
361
362 udelay(500);
363
364 /* select the pixel pll */
365 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
366 tmp = RREG8(DAC_DATA);
367 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
368 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
369 WREG8(DAC_DATA, tmp);
370
371 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
372 tmp = RREG8(DAC_DATA);
373 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
374 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
375 WREG8(DAC_DATA, tmp);
376
377 /* reset dotclock rate bit */
378 WREG8(MGAREG_SEQ_INDEX, 1);
379 tmp = RREG8(MGAREG_SEQ_DATA);
380 tmp &= ~0x8;
381 WREG8(MGAREG_SEQ_DATA, tmp);
382
383 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
384 tmp = RREG8(DAC_DATA);
385 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
386 WREG8(DAC_DATA, tmp);
387
388 vcount = RREG8(MGAREG_VCOUNT);
389
390 for (j = 0; j < 30 && pll_locked == false; j++) {
391 tmpcount = RREG8(MGAREG_VCOUNT);
392 if (tmpcount < vcount)
393 vcount = 0;
394 if ((tmpcount - vcount) > 2)
395 pll_locked = true;
396 else
397 udelay(5);
398 }
399 }
400 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
401 tmp = RREG8(DAC_DATA);
402 tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
403 WREG_DAC(MGA1064_REMHEADCTL, tmp);
404 return 0;
405 }
406
mga_g200ev_set_plls(struct mga_device * mdev,long clock)407 static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
408 {
409 unsigned int vcomax, vcomin, pllreffreq;
410 unsigned int delta, tmpdelta;
411 unsigned int testp, testm, testn;
412 unsigned int p, m, n;
413 unsigned int computed;
414 u8 tmp;
415
416 m = n = p = 0;
417 vcomax = 550000;
418 vcomin = 150000;
419 pllreffreq = 50000;
420
421 delta = 0xffffffff;
422
423 for (testp = 16; testp > 0; testp--) {
424 if (clock * testp > vcomax)
425 continue;
426 if (clock * testp < vcomin)
427 continue;
428
429 for (testn = 1; testn < 257; testn++) {
430 for (testm = 1; testm < 17; testm++) {
431 computed = (pllreffreq * testn) /
432 (testm * testp);
433 if (computed > clock)
434 tmpdelta = computed - clock;
435 else
436 tmpdelta = clock - computed;
437 if (tmpdelta < delta) {
438 delta = tmpdelta;
439 n = testn - 1;
440 m = testm - 1;
441 p = testp - 1;
442 }
443 }
444 }
445 }
446
447 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
448 tmp = RREG8(DAC_DATA);
449 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
450 WREG8(DAC_DATA, tmp);
451
452 tmp = RREG8(MGAREG_MEM_MISC_READ);
453 tmp |= 0x3 << 2;
454 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
455
456 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
457 tmp = RREG8(DAC_DATA);
458 WREG8(DAC_DATA, tmp & ~0x40);
459
460 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
461 tmp = RREG8(DAC_DATA);
462 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
463 WREG8(DAC_DATA, tmp);
464
465 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
466 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
467 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
468
469 udelay(50);
470
471 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
472 tmp = RREG8(DAC_DATA);
473 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
474 WREG8(DAC_DATA, tmp);
475
476 udelay(500);
477
478 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
479 tmp = RREG8(DAC_DATA);
480 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
481 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
482 WREG8(DAC_DATA, tmp);
483
484 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
485 tmp = RREG8(DAC_DATA);
486 WREG8(DAC_DATA, tmp | 0x40);
487
488 tmp = RREG8(MGAREG_MEM_MISC_READ);
489 tmp |= (0x3 << 2);
490 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
491
492 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
493 tmp = RREG8(DAC_DATA);
494 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
495 WREG8(DAC_DATA, tmp);
496
497 return 0;
498 }
499
mga_g200eh_set_plls(struct mga_device * mdev,long clock)500 static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
501 {
502 unsigned int vcomax, vcomin, pllreffreq;
503 unsigned int delta, tmpdelta;
504 unsigned int testp, testm, testn;
505 unsigned int p, m, n;
506 unsigned int computed;
507 int i, j, tmpcount, vcount;
508 u8 tmp;
509 bool pll_locked = false;
510
511 m = n = p = 0;
512 vcomax = 800000;
513 vcomin = 400000;
514 pllreffreq = 33333;
515
516 delta = 0xffffffff;
517
518 for (testp = 16; testp > 0; testp >>= 1) {
519 if (clock * testp > vcomax)
520 continue;
521 if (clock * testp < vcomin)
522 continue;
523
524 for (testm = 1; testm < 33; testm++) {
525 for (testn = 17; testn < 257; testn++) {
526 computed = (pllreffreq * testn) /
527 (testm * testp);
528 if (computed > clock)
529 tmpdelta = computed - clock;
530 else
531 tmpdelta = clock - computed;
532 if (tmpdelta < delta) {
533 delta = tmpdelta;
534 n = testn - 1;
535 m = (testm - 1);
536 p = testp - 1;
537 }
538 if ((clock * testp) >= 600000)
539 p |= 0x80;
540 }
541 }
542 }
543 for (i = 0; i <= 32 && pll_locked == false; i++) {
544 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
545 tmp = RREG8(DAC_DATA);
546 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
547 WREG8(DAC_DATA, tmp);
548
549 tmp = RREG8(MGAREG_MEM_MISC_READ);
550 tmp |= 0x3 << 2;
551 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
552
553 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
554 tmp = RREG8(DAC_DATA);
555 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
556 WREG8(DAC_DATA, tmp);
557
558 udelay(500);
559
560 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
561 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
562 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
563
564 udelay(500);
565
566 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
567 tmp = RREG8(DAC_DATA);
568 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
569 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
570 WREG8(DAC_DATA, tmp);
571
572 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
573 tmp = RREG8(DAC_DATA);
574 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
575 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
576 WREG8(DAC_DATA, tmp);
577
578 vcount = RREG8(MGAREG_VCOUNT);
579
580 for (j = 0; j < 30 && pll_locked == false; j++) {
581 tmpcount = RREG8(MGAREG_VCOUNT);
582 if (tmpcount < vcount)
583 vcount = 0;
584 if ((tmpcount - vcount) > 2)
585 pll_locked = true;
586 else
587 udelay(5);
588 }
589 }
590
591 return 0;
592 }
593
mga_g200er_set_plls(struct mga_device * mdev,long clock)594 static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
595 {
596 unsigned int vcomax, vcomin, pllreffreq;
597 unsigned int delta, tmpdelta;
598 int testr, testn, testm, testo;
599 unsigned int p, m, n;
600 unsigned int computed, vco;
601 int tmp;
602 const unsigned int m_div_val[] = { 1, 2, 4, 8 };
603
604 m = n = p = 0;
605 vcomax = 1488000;
606 vcomin = 1056000;
607 pllreffreq = 48000;
608
609 delta = 0xffffffff;
610
611 for (testr = 0; testr < 4; testr++) {
612 if (delta == 0)
613 break;
614 for (testn = 5; testn < 129; testn++) {
615 if (delta == 0)
616 break;
617 for (testm = 3; testm >= 0; testm--) {
618 if (delta == 0)
619 break;
620 for (testo = 5; testo < 33; testo++) {
621 vco = pllreffreq * (testn + 1) /
622 (testr + 1);
623 if (vco < vcomin)
624 continue;
625 if (vco > vcomax)
626 continue;
627 computed = vco / (m_div_val[testm] * (testo + 1));
628 if (computed > clock)
629 tmpdelta = computed - clock;
630 else
631 tmpdelta = clock - computed;
632 if (tmpdelta < delta) {
633 delta = tmpdelta;
634 m = testm | (testo << 3);
635 n = testn;
636 p = testr | (testr << 3);
637 }
638 }
639 }
640 }
641 }
642
643 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
644 tmp = RREG8(DAC_DATA);
645 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
646 WREG8(DAC_DATA, tmp);
647
648 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
649 tmp = RREG8(DAC_DATA);
650 tmp |= MGA1064_REMHEADCTL_CLKDIS;
651 WREG8(DAC_DATA, tmp);
652
653 tmp = RREG8(MGAREG_MEM_MISC_READ);
654 tmp |= (0x3<<2) | 0xc0;
655 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
656
657 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
658 tmp = RREG8(DAC_DATA);
659 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
660 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
661 WREG8(DAC_DATA, tmp);
662
663 udelay(500);
664
665 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
666 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
667 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
668
669 udelay(50);
670
671 return 0;
672 }
673
mga_crtc_set_plls(struct mga_device * mdev,long clock)674 static int mga_crtc_set_plls(struct mga_device *mdev, long clock)
675 {
676 switch(mdev->type) {
677 case G200_SE_A:
678 case G200_SE_B:
679 return mga_g200se_set_plls(mdev, clock);
680 break;
681 case G200_WB:
682 case G200_EW3:
683 return mga_g200wb_set_plls(mdev, clock);
684 break;
685 case G200_EV:
686 return mga_g200ev_set_plls(mdev, clock);
687 break;
688 case G200_EH:
689 return mga_g200eh_set_plls(mdev, clock);
690 break;
691 case G200_ER:
692 return mga_g200er_set_plls(mdev, clock);
693 break;
694 }
695 return 0;
696 }
697
mga_g200wb_prepare(struct drm_crtc * crtc)698 static void mga_g200wb_prepare(struct drm_crtc *crtc)
699 {
700 struct mga_device *mdev = crtc->dev->dev_private;
701 u8 tmp;
702 int iter_max;
703
704 /* 1- The first step is to warn the BMC of an upcoming mode change.
705 * We are putting the misc<0> to output.*/
706
707 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
708 tmp = RREG8(DAC_DATA);
709 tmp |= 0x10;
710 WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
711
712 /* we are putting a 1 on the misc<0> line */
713 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
714 tmp = RREG8(DAC_DATA);
715 tmp |= 0x10;
716 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
717
718 /* 2- Second step to mask and further scan request
719 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
720 */
721 WREG8(DAC_INDEX, MGA1064_SPAREREG);
722 tmp = RREG8(DAC_DATA);
723 tmp |= 0x80;
724 WREG_DAC(MGA1064_SPAREREG, tmp);
725
726 /* 3a- the third step is to verifu if there is an active scan
727 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
728 */
729 iter_max = 300;
730 while (!(tmp & 0x1) && iter_max) {
731 WREG8(DAC_INDEX, MGA1064_SPAREREG);
732 tmp = RREG8(DAC_DATA);
733 udelay(1000);
734 iter_max--;
735 }
736
737 /* 3b- this step occurs only if the remove is actually scanning
738 * we are waiting for the end of the frame which is a 1 on
739 * remvsyncsts (XSPAREREG<1>)
740 */
741 if (iter_max) {
742 iter_max = 300;
743 while ((tmp & 0x2) && iter_max) {
744 WREG8(DAC_INDEX, MGA1064_SPAREREG);
745 tmp = RREG8(DAC_DATA);
746 udelay(1000);
747 iter_max--;
748 }
749 }
750 }
751
mga_g200wb_commit(struct drm_crtc * crtc)752 static void mga_g200wb_commit(struct drm_crtc *crtc)
753 {
754 u8 tmp;
755 struct mga_device *mdev = crtc->dev->dev_private;
756
757 /* 1- The first step is to ensure that the vrsten and hrsten are set */
758 WREG8(MGAREG_CRTCEXT_INDEX, 1);
759 tmp = RREG8(MGAREG_CRTCEXT_DATA);
760 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
761
762 /* 2- second step is to assert the rstlvl2 */
763 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
764 tmp = RREG8(DAC_DATA);
765 tmp |= 0x8;
766 WREG8(DAC_DATA, tmp);
767
768 /* wait 10 us */
769 udelay(10);
770
771 /* 3- deassert rstlvl2 */
772 tmp &= ~0x08;
773 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
774 WREG8(DAC_DATA, tmp);
775
776 /* 4- remove mask of scan request */
777 WREG8(DAC_INDEX, MGA1064_SPAREREG);
778 tmp = RREG8(DAC_DATA);
779 tmp &= ~0x80;
780 WREG8(DAC_DATA, tmp);
781
782 /* 5- put back a 0 on the misc<0> line */
783 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
784 tmp = RREG8(DAC_DATA);
785 tmp &= ~0x10;
786 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
787 }
788
789 /*
790 This is how the framebuffer base address is stored in g200 cards:
791 * Assume @offset is the gpu_addr variable of the framebuffer object
792 * Then addr is the number of _pixels_ (not bytes) from the start of
793 VRAM to the first pixel we want to display. (divided by 2 for 32bit
794 framebuffers)
795 * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
796 addr<20> -> CRTCEXT0<6>
797 addr<19-16> -> CRTCEXT0<3-0>
798 addr<15-8> -> CRTCC<7-0>
799 addr<7-0> -> CRTCD<7-0>
800 CRTCEXT0 has to be programmed last to trigger an update and make the
801 new addr variable take effect.
802 */
mga_set_start_address(struct drm_crtc * crtc,unsigned offset)803 static void mga_set_start_address(struct drm_crtc *crtc, unsigned offset)
804 {
805 struct mga_device *mdev = crtc->dev->dev_private;
806 u32 addr;
807 int count;
808 u8 crtcext0;
809
810 while (RREG8(0x1fda) & 0x08);
811 while (!(RREG8(0x1fda) & 0x08));
812
813 count = RREG8(MGAREG_VCOUNT) + 2;
814 while (RREG8(MGAREG_VCOUNT) < count);
815
816 WREG8(MGAREG_CRTCEXT_INDEX, 0);
817 crtcext0 = RREG8(MGAREG_CRTCEXT_DATA);
818 crtcext0 &= 0xB0;
819 addr = offset / 8;
820 /* Can't store addresses any higher than that...
821 but we also don't have more than 16MB of memory, so it should be fine. */
822 WARN_ON(addr > 0x1fffff);
823 crtcext0 |= (!!(addr & (1<<20)))<<6;
824 WREG_CRT(0x0d, (u8)(addr & 0xff));
825 WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff);
826 WREG_ECRT(0x0, ((u8)(addr >> 16) & 0xf) | crtcext0);
827 }
828
829
830 /* ast is different - we will force move buffers out of VRAM */
mga_crtc_do_set_base(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,int atomic)831 static int mga_crtc_do_set_base(struct drm_crtc *crtc,
832 struct drm_framebuffer *fb,
833 int x, int y, int atomic)
834 {
835 struct mga_device *mdev = crtc->dev->dev_private;
836 struct drm_gem_object *obj;
837 struct mga_framebuffer *mga_fb;
838 struct mgag200_bo *bo;
839 int ret;
840 u64 gpu_addr;
841
842 /* push the previous fb to system ram */
843 if (!atomic && fb) {
844 mga_fb = to_mga_framebuffer(fb);
845 obj = mga_fb->obj;
846 bo = gem_to_mga_bo(obj);
847 ret = mgag200_bo_reserve(bo, false);
848 if (ret)
849 return ret;
850 mgag200_bo_push_sysram(bo);
851 mgag200_bo_unreserve(bo);
852 }
853
854 mga_fb = to_mga_framebuffer(crtc->primary->fb);
855 obj = mga_fb->obj;
856 bo = gem_to_mga_bo(obj);
857
858 ret = mgag200_bo_reserve(bo, false);
859 if (ret)
860 return ret;
861
862 ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
863 if (ret) {
864 mgag200_bo_unreserve(bo);
865 return ret;
866 }
867
868 if (&mdev->mfbdev->mfb == mga_fb) {
869 /* if pushing console in kmap it */
870 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
871 if (ret)
872 DRM_ERROR("failed to kmap fbcon\n");
873
874 }
875 mgag200_bo_unreserve(bo);
876
877 mga_set_start_address(crtc, (u32)gpu_addr);
878
879 return 0;
880 }
881
mga_crtc_mode_set_base(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * old_fb)882 static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
883 struct drm_framebuffer *old_fb)
884 {
885 return mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
886 }
887
mga_crtc_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,int x,int y,struct drm_framebuffer * old_fb)888 static int mga_crtc_mode_set(struct drm_crtc *crtc,
889 struct drm_display_mode *mode,
890 struct drm_display_mode *adjusted_mode,
891 int x, int y, struct drm_framebuffer *old_fb)
892 {
893 struct drm_device *dev = crtc->dev;
894 struct mga_device *mdev = dev->dev_private;
895 int hdisplay, hsyncstart, hsyncend, htotal;
896 int vdisplay, vsyncstart, vsyncend, vtotal;
897 int pitch;
898 int option = 0, option2 = 0;
899 int i;
900 unsigned char misc = 0;
901 unsigned char ext_vga[6];
902 u8 bppshift;
903
904 static unsigned char dacvalue[] = {
905 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
906 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
907 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
908 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
909 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
910 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
911 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
912 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
913 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
914 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
915 };
916
917 bppshift = mdev->bpp_shifts[(crtc->primary->fb->bits_per_pixel >> 3) - 1];
918
919 switch (mdev->type) {
920 case G200_SE_A:
921 case G200_SE_B:
922 dacvalue[MGA1064_VREF_CTL] = 0x03;
923 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
924 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
925 MGA1064_MISC_CTL_VGA8 |
926 MGA1064_MISC_CTL_DAC_RAM_CS;
927 if (mdev->has_sdram)
928 option = 0x40049120;
929 else
930 option = 0x4004d120;
931 option2 = 0x00008000;
932 break;
933 case G200_WB:
934 case G200_EW3:
935 dacvalue[MGA1064_VREF_CTL] = 0x07;
936 option = 0x41049120;
937 option2 = 0x0000b000;
938 break;
939 case G200_EV:
940 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
941 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
942 MGA1064_MISC_CTL_DAC_RAM_CS;
943 option = 0x00000120;
944 option2 = 0x0000b000;
945 break;
946 case G200_EH:
947 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
948 MGA1064_MISC_CTL_DAC_RAM_CS;
949 option = 0x00000120;
950 option2 = 0x0000b000;
951 break;
952 case G200_ER:
953 break;
954 }
955
956 switch (crtc->primary->fb->bits_per_pixel) {
957 case 8:
958 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits;
959 break;
960 case 16:
961 if (crtc->primary->fb->depth == 15)
962 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits;
963 else
964 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits;
965 break;
966 case 24:
967 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits;
968 break;
969 case 32:
970 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits;
971 break;
972 }
973
974 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
975 misc |= 0x40;
976 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
977 misc |= 0x80;
978
979
980 for (i = 0; i < sizeof(dacvalue); i++) {
981 if ((i <= 0x17) ||
982 (i == 0x1b) ||
983 (i == 0x1c) ||
984 ((i >= 0x1f) && (i <= 0x29)) ||
985 ((i >= 0x30) && (i <= 0x37)))
986 continue;
987 if (IS_G200_SE(mdev) &&
988 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
989 continue;
990 if ((mdev->type == G200_EV ||
991 mdev->type == G200_WB ||
992 mdev->type == G200_EH ||
993 mdev->type == G200_EW3) &&
994 (i >= 0x44) && (i <= 0x4e))
995 continue;
996
997 WREG_DAC(i, dacvalue[i]);
998 }
999
1000 if (mdev->type == G200_ER)
1001 WREG_DAC(0x90, 0);
1002
1003 if (option)
1004 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
1005 if (option2)
1006 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
1007
1008 WREG_SEQ(2, 0xf);
1009 WREG_SEQ(3, 0);
1010 WREG_SEQ(4, 0xe);
1011
1012 pitch = crtc->primary->fb->pitches[0] / (crtc->primary->fb->bits_per_pixel / 8);
1013 if (crtc->primary->fb->bits_per_pixel == 24)
1014 pitch = (pitch * 3) >> (4 - bppshift);
1015 else
1016 pitch = pitch >> (4 - bppshift);
1017
1018 hdisplay = mode->hdisplay / 8 - 1;
1019 hsyncstart = mode->hsync_start / 8 - 1;
1020 hsyncend = mode->hsync_end / 8 - 1;
1021 htotal = mode->htotal / 8 - 1;
1022
1023 /* Work around hardware quirk */
1024 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
1025 htotal++;
1026
1027 vdisplay = mode->vdisplay - 1;
1028 vsyncstart = mode->vsync_start - 1;
1029 vsyncend = mode->vsync_end - 1;
1030 vtotal = mode->vtotal - 2;
1031
1032 WREG_GFX(0, 0);
1033 WREG_GFX(1, 0);
1034 WREG_GFX(2, 0);
1035 WREG_GFX(3, 0);
1036 WREG_GFX(4, 0);
1037 WREG_GFX(5, 0x40);
1038 WREG_GFX(6, 0x5);
1039 WREG_GFX(7, 0xf);
1040 WREG_GFX(8, 0xf);
1041
1042 WREG_CRT(0, htotal - 4);
1043 WREG_CRT(1, hdisplay);
1044 WREG_CRT(2, hdisplay);
1045 WREG_CRT(3, (htotal & 0x1F) | 0x80);
1046 WREG_CRT(4, hsyncstart);
1047 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
1048 WREG_CRT(6, vtotal & 0xFF);
1049 WREG_CRT(7, ((vtotal & 0x100) >> 8) |
1050 ((vdisplay & 0x100) >> 7) |
1051 ((vsyncstart & 0x100) >> 6) |
1052 ((vdisplay & 0x100) >> 5) |
1053 ((vdisplay & 0x100) >> 4) | /* linecomp */
1054 ((vtotal & 0x200) >> 4)|
1055 ((vdisplay & 0x200) >> 3) |
1056 ((vsyncstart & 0x200) >> 2));
1057 WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
1058 ((vdisplay & 0x200) >> 3));
1059 WREG_CRT(10, 0);
1060 WREG_CRT(11, 0);
1061 WREG_CRT(12, 0);
1062 WREG_CRT(13, 0);
1063 WREG_CRT(14, 0);
1064 WREG_CRT(15, 0);
1065 WREG_CRT(16, vsyncstart & 0xFF);
1066 WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
1067 WREG_CRT(18, vdisplay & 0xFF);
1068 WREG_CRT(19, pitch & 0xFF);
1069 WREG_CRT(20, 0);
1070 WREG_CRT(21, vdisplay & 0xFF);
1071 WREG_CRT(22, (vtotal + 1) & 0xFF);
1072 WREG_CRT(23, 0xc3);
1073 WREG_CRT(24, vdisplay & 0xFF);
1074
1075 ext_vga[0] = 0;
1076 ext_vga[5] = 0;
1077
1078 /* TODO interlace */
1079
1080 ext_vga[0] |= (pitch & 0x300) >> 4;
1081 ext_vga[1] = (((htotal - 4) & 0x100) >> 8) |
1082 ((hdisplay & 0x100) >> 7) |
1083 ((hsyncstart & 0x100) >> 6) |
1084 (htotal & 0x40);
1085 ext_vga[2] = ((vtotal & 0xc00) >> 10) |
1086 ((vdisplay & 0x400) >> 8) |
1087 ((vdisplay & 0xc00) >> 7) |
1088 ((vsyncstart & 0xc00) >> 5) |
1089 ((vdisplay & 0x400) >> 3);
1090 if (crtc->primary->fb->bits_per_pixel == 24)
1091 ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80;
1092 else
1093 ext_vga[3] = ((1 << bppshift) - 1) | 0x80;
1094 ext_vga[4] = 0;
1095 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1096 ext_vga[1] |= 0x88;
1097
1098 /* Set pixel clocks */
1099 misc = 0x2d;
1100 WREG8(MGA_MISC_OUT, misc);
1101
1102 mga_crtc_set_plls(mdev, mode->clock);
1103
1104 for (i = 0; i < 6; i++) {
1105 WREG_ECRT(i, ext_vga[i]);
1106 }
1107
1108 if (mdev->type == G200_ER)
1109 WREG_ECRT(0x24, 0x5);
1110
1111 if (mdev->type == G200_EW3)
1112 WREG_ECRT(0x34, 0x5);
1113
1114 if (mdev->type == G200_EV) {
1115 WREG_ECRT(6, 0);
1116 }
1117
1118 WREG_ECRT(0, ext_vga[0]);
1119 /* Enable mga pixel clock */
1120 misc = 0x2d;
1121
1122 WREG8(MGA_MISC_OUT, misc);
1123
1124 if (adjusted_mode)
1125 memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode));
1126
1127 mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
1128
1129 /* reset tagfifo */
1130 if (mdev->type == G200_ER) {
1131 u32 mem_ctl = RREG32(MGAREG_MEMCTL);
1132 u8 seq1;
1133
1134 /* screen off */
1135 WREG8(MGAREG_SEQ_INDEX, 0x01);
1136 seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20;
1137 WREG8(MGAREG_SEQ_DATA, seq1);
1138
1139 WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000);
1140 udelay(1000);
1141 WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000);
1142
1143 WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20);
1144 }
1145
1146
1147 if (IS_G200_SE(mdev)) {
1148 if (mdev->unique_rev_id >= 0x02) {
1149 u8 hi_pri_lvl;
1150 u32 bpp;
1151 u32 mb;
1152
1153 if (crtc->primary->fb->bits_per_pixel > 16)
1154 bpp = 32;
1155 else if (crtc->primary->fb->bits_per_pixel > 8)
1156 bpp = 16;
1157 else
1158 bpp = 8;
1159
1160 mb = (mode->clock * bpp) / 1000;
1161 if (mb > 3100)
1162 hi_pri_lvl = 0;
1163 else if (mb > 2600)
1164 hi_pri_lvl = 1;
1165 else if (mb > 1900)
1166 hi_pri_lvl = 2;
1167 else if (mb > 1160)
1168 hi_pri_lvl = 3;
1169 else if (mb > 440)
1170 hi_pri_lvl = 4;
1171 else
1172 hi_pri_lvl = 5;
1173
1174 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1175 WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl);
1176 } else {
1177 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1178 if (mdev->unique_rev_id >= 0x01)
1179 WREG8(MGAREG_CRTCEXT_DATA, 0x03);
1180 else
1181 WREG8(MGAREG_CRTCEXT_DATA, 0x04);
1182 }
1183 }
1184 return 0;
1185 }
1186
1187 #if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */
1188 static int mga_suspend(struct drm_crtc *crtc)
1189 {
1190 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1191 struct drm_device *dev = crtc->dev;
1192 struct mga_device *mdev = dev->dev_private;
1193 struct pci_dev *pdev = dev->pdev;
1194 int option;
1195
1196 if (mdev->suspended)
1197 return 0;
1198
1199 WREG_SEQ(1, 0x20);
1200 WREG_ECRT(1, 0x30);
1201 /* Disable the pixel clock */
1202 WREG_DAC(0x1a, 0x05);
1203 /* Power down the DAC */
1204 WREG_DAC(0x1e, 0x18);
1205 /* Power down the pixel PLL */
1206 WREG_DAC(0x1a, 0x0d);
1207
1208 /* Disable PLLs and clocks */
1209 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1210 option &= ~(0x1F8024);
1211 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1212 pci_set_power_state(pdev, PCI_D3hot);
1213 pci_disable_device(pdev);
1214
1215 mdev->suspended = true;
1216
1217 return 0;
1218 }
1219
1220 static int mga_resume(struct drm_crtc *crtc)
1221 {
1222 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1223 struct drm_device *dev = crtc->dev;
1224 struct mga_device *mdev = dev->dev_private;
1225 struct pci_dev *pdev = dev->pdev;
1226 int option;
1227
1228 if (!mdev->suspended)
1229 return 0;
1230
1231 pci_set_power_state(pdev, PCI_D0);
1232 pci_enable_device(pdev);
1233
1234 /* Disable sysclk */
1235 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1236 option &= ~(0x4);
1237 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1238
1239 mdev->suspended = false;
1240
1241 return 0;
1242 }
1243
1244 #endif
1245
mga_crtc_dpms(struct drm_crtc * crtc,int mode)1246 static void mga_crtc_dpms(struct drm_crtc *crtc, int mode)
1247 {
1248 struct drm_device *dev = crtc->dev;
1249 struct mga_device *mdev = dev->dev_private;
1250 u8 seq1 = 0, crtcext1 = 0;
1251
1252 switch (mode) {
1253 case DRM_MODE_DPMS_ON:
1254 seq1 = 0;
1255 crtcext1 = 0;
1256 mga_crtc_load_lut(crtc);
1257 break;
1258 case DRM_MODE_DPMS_STANDBY:
1259 seq1 = 0x20;
1260 crtcext1 = 0x10;
1261 break;
1262 case DRM_MODE_DPMS_SUSPEND:
1263 seq1 = 0x20;
1264 crtcext1 = 0x20;
1265 break;
1266 case DRM_MODE_DPMS_OFF:
1267 seq1 = 0x20;
1268 crtcext1 = 0x30;
1269 break;
1270 }
1271
1272 #if 0
1273 if (mode == DRM_MODE_DPMS_OFF) {
1274 mga_suspend(crtc);
1275 }
1276 #endif
1277 WREG8(MGAREG_SEQ_INDEX, 0x01);
1278 seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20;
1279 mga_wait_vsync(mdev);
1280 mga_wait_busy(mdev);
1281 WREG8(MGAREG_SEQ_DATA, seq1);
1282 msleep(20);
1283 WREG8(MGAREG_CRTCEXT_INDEX, 0x01);
1284 crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30;
1285 WREG8(MGAREG_CRTCEXT_DATA, crtcext1);
1286
1287 #if 0
1288 if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) {
1289 mga_resume(crtc);
1290 drm_helper_resume_force_mode(dev);
1291 }
1292 #endif
1293 }
1294
1295 /*
1296 * This is called before a mode is programmed. A typical use might be to
1297 * enable DPMS during the programming to avoid seeing intermediate stages,
1298 * but that's not relevant to us
1299 */
mga_crtc_prepare(struct drm_crtc * crtc)1300 static void mga_crtc_prepare(struct drm_crtc *crtc)
1301 {
1302 struct drm_device *dev = crtc->dev;
1303 struct mga_device *mdev = dev->dev_private;
1304 u8 tmp;
1305
1306 /* mga_resume(crtc);*/
1307
1308 WREG8(MGAREG_CRTC_INDEX, 0x11);
1309 tmp = RREG8(MGAREG_CRTC_DATA);
1310 WREG_CRT(0x11, tmp | 0x80);
1311
1312 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1313 WREG_SEQ(0, 1);
1314 msleep(50);
1315 WREG_SEQ(1, 0x20);
1316 msleep(20);
1317 } else {
1318 WREG8(MGAREG_SEQ_INDEX, 0x1);
1319 tmp = RREG8(MGAREG_SEQ_DATA);
1320
1321 /* start sync reset */
1322 WREG_SEQ(0, 1);
1323 WREG_SEQ(1, tmp | 0x20);
1324 }
1325
1326 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1327 mga_g200wb_prepare(crtc);
1328
1329 WREG_CRT(17, 0);
1330 }
1331
1332 /*
1333 * This is called after a mode is programmed. It should reverse anything done
1334 * by the prepare function
1335 */
mga_crtc_commit(struct drm_crtc * crtc)1336 static void mga_crtc_commit(struct drm_crtc *crtc)
1337 {
1338 struct drm_device *dev = crtc->dev;
1339 struct mga_device *mdev = dev->dev_private;
1340 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1341 u8 tmp;
1342
1343 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1344 mga_g200wb_commit(crtc);
1345
1346 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1347 msleep(50);
1348 WREG_SEQ(1, 0x0);
1349 msleep(20);
1350 WREG_SEQ(0, 0x3);
1351 } else {
1352 WREG8(MGAREG_SEQ_INDEX, 0x1);
1353 tmp = RREG8(MGAREG_SEQ_DATA);
1354
1355 tmp &= ~0x20;
1356 WREG_SEQ(0x1, tmp);
1357 WREG_SEQ(0, 3);
1358 }
1359 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1360 }
1361
1362 /*
1363 * The core can pass us a set of gamma values to program. We actually only
1364 * use this for 8-bit mode so can't perform smooth fades on deeper modes,
1365 * but it's a requirement that we provide the function
1366 */
mga_crtc_gamma_set(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,uint32_t start,uint32_t size)1367 static void mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1368 u16 *blue, uint32_t start, uint32_t size)
1369 {
1370 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1371 int end = (start + size > MGAG200_LUT_SIZE) ? MGAG200_LUT_SIZE : start + size;
1372 int i;
1373
1374 for (i = start; i < end; i++) {
1375 mga_crtc->lut_r[i] = red[i] >> 8;
1376 mga_crtc->lut_g[i] = green[i] >> 8;
1377 mga_crtc->lut_b[i] = blue[i] >> 8;
1378 }
1379 mga_crtc_load_lut(crtc);
1380 }
1381
1382 /* Simple cleanup function */
mga_crtc_destroy(struct drm_crtc * crtc)1383 static void mga_crtc_destroy(struct drm_crtc *crtc)
1384 {
1385 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1386
1387 drm_crtc_cleanup(crtc);
1388 kfree(mga_crtc);
1389 }
1390
mga_crtc_disable(struct drm_crtc * crtc)1391 static void mga_crtc_disable(struct drm_crtc *crtc)
1392 {
1393 int ret;
1394 DRM_DEBUG_KMS("\n");
1395 mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1396 if (crtc->primary->fb) {
1397 struct mga_framebuffer *mga_fb = to_mga_framebuffer(crtc->primary->fb);
1398 struct drm_gem_object *obj = mga_fb->obj;
1399 struct mgag200_bo *bo = gem_to_mga_bo(obj);
1400 ret = mgag200_bo_reserve(bo, false);
1401 if (ret)
1402 return;
1403 mgag200_bo_push_sysram(bo);
1404 mgag200_bo_unreserve(bo);
1405 }
1406 crtc->primary->fb = NULL;
1407 }
1408
1409 /* These provide the minimum set of functions required to handle a CRTC */
1410 static const struct drm_crtc_funcs mga_crtc_funcs = {
1411 .cursor_set = mga_crtc_cursor_set,
1412 .cursor_move = mga_crtc_cursor_move,
1413 .gamma_set = mga_crtc_gamma_set,
1414 .set_config = drm_crtc_helper_set_config,
1415 .destroy = mga_crtc_destroy,
1416 };
1417
1418 static const struct drm_crtc_helper_funcs mga_helper_funcs = {
1419 .disable = mga_crtc_disable,
1420 .dpms = mga_crtc_dpms,
1421 .mode_fixup = mga_crtc_mode_fixup,
1422 .mode_set = mga_crtc_mode_set,
1423 .mode_set_base = mga_crtc_mode_set_base,
1424 .prepare = mga_crtc_prepare,
1425 .commit = mga_crtc_commit,
1426 .load_lut = mga_crtc_load_lut,
1427 };
1428
1429 /* CRTC setup */
mga_crtc_init(struct mga_device * mdev)1430 static void mga_crtc_init(struct mga_device *mdev)
1431 {
1432 struct mga_crtc *mga_crtc;
1433 int i;
1434
1435 mga_crtc = kzalloc(sizeof(struct mga_crtc) +
1436 (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)),
1437 GFP_KERNEL);
1438
1439 if (mga_crtc == NULL)
1440 return;
1441
1442 drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs);
1443
1444 drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE);
1445 mdev->mode_info.crtc = mga_crtc;
1446
1447 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
1448 mga_crtc->lut_r[i] = i;
1449 mga_crtc->lut_g[i] = i;
1450 mga_crtc->lut_b[i] = i;
1451 }
1452
1453 drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs);
1454 }
1455
1456 /** Sets the color ramps on behalf of fbcon */
mga_crtc_fb_gamma_set(struct drm_crtc * crtc,u16 red,u16 green,u16 blue,int regno)1457 void mga_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
1458 u16 blue, int regno)
1459 {
1460 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1461
1462 mga_crtc->lut_r[regno] = red >> 8;
1463 mga_crtc->lut_g[regno] = green >> 8;
1464 mga_crtc->lut_b[regno] = blue >> 8;
1465 }
1466
1467 /** Gets the color ramps on behalf of fbcon */
mga_crtc_fb_gamma_get(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,int regno)1468 void mga_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
1469 u16 *blue, int regno)
1470 {
1471 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1472
1473 *red = (u16)mga_crtc->lut_r[regno] << 8;
1474 *green = (u16)mga_crtc->lut_g[regno] << 8;
1475 *blue = (u16)mga_crtc->lut_b[regno] << 8;
1476 }
1477
1478 /*
1479 * The encoder comes after the CRTC in the output pipeline, but before
1480 * the connector. It's responsible for ensuring that the digital
1481 * stream is appropriately converted into the output format. Setup is
1482 * very simple in this case - all we have to do is inform qemu of the
1483 * colour depth in order to ensure that it displays appropriately
1484 */
1485
1486 /*
1487 * These functions are analagous to those in the CRTC code, but are intended
1488 * to handle any encoder-specific limitations
1489 */
mga_encoder_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1490 static bool mga_encoder_mode_fixup(struct drm_encoder *encoder,
1491 const struct drm_display_mode *mode,
1492 struct drm_display_mode *adjusted_mode)
1493 {
1494 return true;
1495 }
1496
mga_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1497 static void mga_encoder_mode_set(struct drm_encoder *encoder,
1498 struct drm_display_mode *mode,
1499 struct drm_display_mode *adjusted_mode)
1500 {
1501
1502 }
1503
mga_encoder_dpms(struct drm_encoder * encoder,int state)1504 static void mga_encoder_dpms(struct drm_encoder *encoder, int state)
1505 {
1506 return;
1507 }
1508
mga_encoder_prepare(struct drm_encoder * encoder)1509 static void mga_encoder_prepare(struct drm_encoder *encoder)
1510 {
1511 }
1512
mga_encoder_commit(struct drm_encoder * encoder)1513 static void mga_encoder_commit(struct drm_encoder *encoder)
1514 {
1515 }
1516
mga_encoder_destroy(struct drm_encoder * encoder)1517 static void mga_encoder_destroy(struct drm_encoder *encoder)
1518 {
1519 struct mga_encoder *mga_encoder = to_mga_encoder(encoder);
1520 drm_encoder_cleanup(encoder);
1521 kfree(mga_encoder);
1522 }
1523
1524 static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = {
1525 .dpms = mga_encoder_dpms,
1526 .mode_fixup = mga_encoder_mode_fixup,
1527 .mode_set = mga_encoder_mode_set,
1528 .prepare = mga_encoder_prepare,
1529 .commit = mga_encoder_commit,
1530 };
1531
1532 static const struct drm_encoder_funcs mga_encoder_encoder_funcs = {
1533 .destroy = mga_encoder_destroy,
1534 };
1535
mga_encoder_init(struct drm_device * dev)1536 static struct drm_encoder *mga_encoder_init(struct drm_device *dev)
1537 {
1538 struct drm_encoder *encoder;
1539 struct mga_encoder *mga_encoder;
1540
1541 mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL);
1542 if (!mga_encoder)
1543 return NULL;
1544
1545 encoder = &mga_encoder->base;
1546 encoder->possible_crtcs = 0x1;
1547
1548 drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs,
1549 DRM_MODE_ENCODER_DAC);
1550 drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs);
1551
1552 return encoder;
1553 }
1554
1555
mga_vga_get_modes(struct drm_connector * connector)1556 static int mga_vga_get_modes(struct drm_connector *connector)
1557 {
1558 struct mga_connector *mga_connector = to_mga_connector(connector);
1559 struct edid *edid;
1560 int ret = 0;
1561
1562 edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
1563 if (edid) {
1564 drm_mode_connector_update_edid_property(connector, edid);
1565 ret = drm_add_edid_modes(connector, edid);
1566 kfree(edid);
1567 }
1568 return ret;
1569 }
1570
mga_vga_calculate_mode_bandwidth(struct drm_display_mode * mode,int bits_per_pixel)1571 static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode,
1572 int bits_per_pixel)
1573 {
1574 uint32_t total_area, divisor;
1575 int64_t active_area, pixels_per_second, bandwidth;
1576 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
1577
1578 divisor = 1024;
1579
1580 if (!mode->htotal || !mode->vtotal || !mode->clock)
1581 return 0;
1582
1583 active_area = mode->hdisplay * mode->vdisplay;
1584 total_area = mode->htotal * mode->vtotal;
1585
1586 pixels_per_second = active_area * mode->clock * 1000;
1587 do_div(pixels_per_second, total_area);
1588
1589 bandwidth = pixels_per_second * bytes_per_pixel * 100;
1590 do_div(bandwidth, divisor);
1591
1592 return (uint32_t)(bandwidth);
1593 }
1594
1595 #define MODE_BANDWIDTH MODE_BAD
1596
mga_vga_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1597 static int mga_vga_mode_valid(struct drm_connector *connector,
1598 struct drm_display_mode *mode)
1599 {
1600 struct drm_device *dev = connector->dev;
1601 struct mga_device *mdev = (struct mga_device*)dev->dev_private;
1602 int bpp = 32;
1603
1604 if (IS_G200_SE(mdev)) {
1605 if (mdev->unique_rev_id == 0x01) {
1606 if (mode->hdisplay > 1600)
1607 return MODE_VIRTUAL_X;
1608 if (mode->vdisplay > 1200)
1609 return MODE_VIRTUAL_Y;
1610 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1611 > (24400 * 1024))
1612 return MODE_BANDWIDTH;
1613 } else if (mdev->unique_rev_id == 0x02) {
1614 if (mode->hdisplay > 1920)
1615 return MODE_VIRTUAL_X;
1616 if (mode->vdisplay > 1200)
1617 return MODE_VIRTUAL_Y;
1618 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1619 > (30100 * 1024))
1620 return MODE_BANDWIDTH;
1621 }
1622 } else if (mdev->type == G200_WB) {
1623 if (mode->hdisplay > 1280)
1624 return MODE_VIRTUAL_X;
1625 if (mode->vdisplay > 1024)
1626 return MODE_VIRTUAL_Y;
1627 if (mga_vga_calculate_mode_bandwidth(mode,
1628 bpp > (31877 * 1024)))
1629 return MODE_BANDWIDTH;
1630 } else if (mdev->type == G200_EV &&
1631 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1632 > (32700 * 1024))) {
1633 return MODE_BANDWIDTH;
1634 } else if (mdev->type == G200_EH &&
1635 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1636 > (37500 * 1024))) {
1637 return MODE_BANDWIDTH;
1638 } else if (mdev->type == G200_ER &&
1639 (mga_vga_calculate_mode_bandwidth(mode,
1640 bpp) > (55000 * 1024))) {
1641 return MODE_BANDWIDTH;
1642 }
1643
1644 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 ||
1645 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) {
1646 return MODE_H_ILLEGAL;
1647 }
1648
1649 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1650 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1651 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1652 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1653 return MODE_BAD;
1654 }
1655
1656 /* Validate the mode input by the user */
1657 if (connector->cmdline_mode.specified) {
1658 if (connector->cmdline_mode.bpp_specified)
1659 bpp = connector->cmdline_mode.bpp;
1660 }
1661
1662 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) {
1663 if (connector->cmdline_mode.specified)
1664 connector->cmdline_mode.specified = false;
1665 return MODE_BAD;
1666 }
1667
1668 return MODE_OK;
1669 }
1670
mga_connector_best_encoder(struct drm_connector * connector)1671 static struct drm_encoder *mga_connector_best_encoder(struct drm_connector
1672 *connector)
1673 {
1674 int enc_id = connector->encoder_ids[0];
1675 /* pick the encoder ids */
1676 if (enc_id)
1677 return drm_encoder_find(connector->dev, enc_id);
1678 return NULL;
1679 }
1680
mga_vga_detect(struct drm_connector * connector,bool force)1681 static enum drm_connector_status mga_vga_detect(struct drm_connector
1682 *connector, bool force)
1683 {
1684 return connector_status_connected;
1685 }
1686
mga_connector_destroy(struct drm_connector * connector)1687 static void mga_connector_destroy(struct drm_connector *connector)
1688 {
1689 struct mga_connector *mga_connector = to_mga_connector(connector);
1690 mgag200_i2c_destroy(mga_connector->i2c);
1691 drm_connector_cleanup(connector);
1692 kfree(connector);
1693 }
1694
1695 struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
1696 .get_modes = mga_vga_get_modes,
1697 .mode_valid = mga_vga_mode_valid,
1698 .best_encoder = mga_connector_best_encoder,
1699 };
1700
1701 struct drm_connector_funcs mga_vga_connector_funcs = {
1702 .dpms = drm_helper_connector_dpms,
1703 .detect = mga_vga_detect,
1704 .fill_modes = drm_helper_probe_single_connector_modes,
1705 .destroy = mga_connector_destroy,
1706 };
1707
mga_vga_init(struct drm_device * dev)1708 static struct drm_connector *mga_vga_init(struct drm_device *dev)
1709 {
1710 struct drm_connector *connector;
1711 struct mga_connector *mga_connector;
1712
1713 mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL);
1714 if (!mga_connector)
1715 return NULL;
1716
1717 connector = &mga_connector->base;
1718
1719 drm_connector_init(dev, connector,
1720 &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1721
1722 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1723
1724 drm_connector_register(connector);
1725
1726 mga_connector->i2c = mgag200_i2c_create(dev);
1727 if (!mga_connector->i2c)
1728 DRM_ERROR("failed to add ddc bus\n");
1729
1730 return connector;
1731 }
1732
1733
mgag200_modeset_init(struct mga_device * mdev)1734 int mgag200_modeset_init(struct mga_device *mdev)
1735 {
1736 struct drm_encoder *encoder;
1737 struct drm_connector *connector;
1738 int ret;
1739
1740 mdev->mode_info.mode_config_initialized = true;
1741
1742 mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
1743 mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
1744
1745 mdev->dev->mode_config.fb_base = mdev->mc.vram_base;
1746
1747 mga_crtc_init(mdev);
1748
1749 encoder = mga_encoder_init(mdev->dev);
1750 if (!encoder) {
1751 DRM_ERROR("mga_encoder_init failed\n");
1752 return -1;
1753 }
1754
1755 connector = mga_vga_init(mdev->dev);
1756 if (!connector) {
1757 DRM_ERROR("mga_vga_init failed\n");
1758 return -1;
1759 }
1760
1761 drm_mode_connector_attach_encoder(connector, encoder);
1762
1763 ret = mgag200_fbdev_init(mdev);
1764 if (ret) {
1765 DRM_ERROR("mga_fbdev_init failed\n");
1766 return ret;
1767 }
1768
1769 return 0;
1770 }
1771
mgag200_modeset_fini(struct mga_device * mdev)1772 void mgag200_modeset_fini(struct mga_device *mdev)
1773 {
1774
1775 }
1776