1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 David Daney
7 */
8
9 #include <linux/sched.h>
10
11 #include <asm/processor.h>
12 #include <asm/watch.h>
13
14 /*
15 * Install the watch registers for the current thread. A maximum of
16 * four registers are installed although the machine may have more.
17 */
mips_install_watch_registers(struct task_struct * t)18 void mips_install_watch_registers(struct task_struct *t)
19 {
20 struct mips3264_watch_reg_state *watches = &t->thread.watch.mips3264;
21 switch (current_cpu_data.watch_reg_use_cnt) {
22 default:
23 BUG();
24 case 4:
25 write_c0_watchlo3(watches->watchlo[3]);
26 /* Write 1 to the I, R, and W bits to clear them, and
27 1 to G so all ASIDs are trapped. */
28 write_c0_watchhi3(0x40000007 | watches->watchhi[3]);
29 case 3:
30 write_c0_watchlo2(watches->watchlo[2]);
31 write_c0_watchhi2(0x40000007 | watches->watchhi[2]);
32 case 2:
33 write_c0_watchlo1(watches->watchlo[1]);
34 write_c0_watchhi1(0x40000007 | watches->watchhi[1]);
35 case 1:
36 write_c0_watchlo0(watches->watchlo[0]);
37 write_c0_watchhi0(0x40000007 | watches->watchhi[0]);
38 }
39 }
40
41 /*
42 * Read back the watchhi registers so the user space debugger has
43 * access to the I, R, and W bits. A maximum of four registers are
44 * read although the machine may have more.
45 */
mips_read_watch_registers(void)46 void mips_read_watch_registers(void)
47 {
48 struct mips3264_watch_reg_state *watches =
49 ¤t->thread.watch.mips3264;
50 switch (current_cpu_data.watch_reg_use_cnt) {
51 default:
52 BUG();
53 case 4:
54 watches->watchhi[3] = (read_c0_watchhi3() & 0x0fff);
55 case 3:
56 watches->watchhi[2] = (read_c0_watchhi2() & 0x0fff);
57 case 2:
58 watches->watchhi[1] = (read_c0_watchhi1() & 0x0fff);
59 case 1:
60 watches->watchhi[0] = (read_c0_watchhi0() & 0x0fff);
61 }
62 if (current_cpu_data.watch_reg_use_cnt == 1 &&
63 (watches->watchhi[0] & 7) == 0) {
64 /* Pathological case of release 1 architecture that
65 * doesn't set the condition bits. We assume that
66 * since we got here, the watch condition was met and
67 * signal that the conditions requested in watchlo
68 * were met. */
69 watches->watchhi[0] |= (watches->watchlo[0] & 7);
70 }
71 }
72
73 /*
74 * Disable all watch registers. Although only four registers are
75 * installed, all are cleared to eliminate the possibility of endless
76 * looping in the watch handler.
77 */
mips_clear_watch_registers(void)78 void mips_clear_watch_registers(void)
79 {
80 switch (current_cpu_data.watch_reg_count) {
81 default:
82 BUG();
83 case 8:
84 write_c0_watchlo7(0);
85 case 7:
86 write_c0_watchlo6(0);
87 case 6:
88 write_c0_watchlo5(0);
89 case 5:
90 write_c0_watchlo4(0);
91 case 4:
92 write_c0_watchlo3(0);
93 case 3:
94 write_c0_watchlo2(0);
95 case 2:
96 write_c0_watchlo1(0);
97 case 1:
98 write_c0_watchlo0(0);
99 }
100 }
101
mips_probe_watch_registers(struct cpuinfo_mips * c)102 void mips_probe_watch_registers(struct cpuinfo_mips *c)
103 {
104 unsigned int t;
105
106 if ((c->options & MIPS_CPU_WATCH) == 0)
107 return;
108 /*
109 * Check which of the I,R and W bits are supported, then
110 * disable the register.
111 */
112 write_c0_watchlo0(7);
113 back_to_back_c0_hazard();
114 t = read_c0_watchlo0();
115 write_c0_watchlo0(0);
116 c->watch_reg_masks[0] = t & 7;
117
118 /* Write the mask bits and read them back to determine which
119 * can be used. */
120 c->watch_reg_count = 1;
121 c->watch_reg_use_cnt = 1;
122 t = read_c0_watchhi0();
123 write_c0_watchhi0(t | 0xff8);
124 back_to_back_c0_hazard();
125 t = read_c0_watchhi0();
126 c->watch_reg_masks[0] |= (t & 0xff8);
127 if ((t & 0x80000000) == 0)
128 return;
129
130 write_c0_watchlo1(7);
131 back_to_back_c0_hazard();
132 t = read_c0_watchlo1();
133 write_c0_watchlo1(0);
134 c->watch_reg_masks[1] = t & 7;
135
136 c->watch_reg_count = 2;
137 c->watch_reg_use_cnt = 2;
138 t = read_c0_watchhi1();
139 write_c0_watchhi1(t | 0xff8);
140 back_to_back_c0_hazard();
141 t = read_c0_watchhi1();
142 c->watch_reg_masks[1] |= (t & 0xff8);
143 if ((t & 0x80000000) == 0)
144 return;
145
146 write_c0_watchlo2(7);
147 back_to_back_c0_hazard();
148 t = read_c0_watchlo2();
149 write_c0_watchlo2(0);
150 c->watch_reg_masks[2] = t & 7;
151
152 c->watch_reg_count = 3;
153 c->watch_reg_use_cnt = 3;
154 t = read_c0_watchhi2();
155 write_c0_watchhi2(t | 0xff8);
156 back_to_back_c0_hazard();
157 t = read_c0_watchhi2();
158 c->watch_reg_masks[2] |= (t & 0xff8);
159 if ((t & 0x80000000) == 0)
160 return;
161
162 write_c0_watchlo3(7);
163 back_to_back_c0_hazard();
164 t = read_c0_watchlo3();
165 write_c0_watchlo3(0);
166 c->watch_reg_masks[3] = t & 7;
167
168 c->watch_reg_count = 4;
169 c->watch_reg_use_cnt = 4;
170 t = read_c0_watchhi3();
171 write_c0_watchhi3(t | 0xff8);
172 back_to_back_c0_hazard();
173 t = read_c0_watchhi3();
174 c->watch_reg_masks[3] |= (t & 0xff8);
175 if ((t & 0x80000000) == 0)
176 return;
177
178 /* We use at most 4, but probe and report up to 8. */
179 c->watch_reg_count = 5;
180 t = read_c0_watchhi4();
181 if ((t & 0x80000000) == 0)
182 return;
183
184 c->watch_reg_count = 6;
185 t = read_c0_watchhi5();
186 if ((t & 0x80000000) == 0)
187 return;
188
189 c->watch_reg_count = 7;
190 t = read_c0_watchhi6();
191 if ((t & 0x80000000) == 0)
192 return;
193
194 c->watch_reg_count = 8;
195 }
196