1 #ifndef _ASM_X86_AMD_NB_H 2 #define _ASM_X86_AMD_NB_H 3 4 #include <linux/ioport.h> 5 #include <linux/pci.h> 6 7 struct amd_nb_bus_dev_range { 8 u8 bus; 9 u8 dev_base; 10 u8 dev_limit; 11 }; 12 13 extern const struct pci_device_id amd_nb_misc_ids[]; 14 extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[]; 15 16 extern bool early_is_amd_nb(u32 value); 17 extern struct resource *amd_get_mmconfig_range(struct resource *res); 18 extern int amd_cache_northbridges(void); 19 extern void amd_flush_garts(void); 20 extern int amd_numa_init(void); 21 extern int amd_get_subcaches(int); 22 extern int amd_set_subcaches(int, unsigned long); 23 24 struct amd_l3_cache { 25 unsigned indices; 26 u8 subcaches[4]; 27 }; 28 29 struct threshold_block { 30 unsigned int block; 31 unsigned int bank; 32 unsigned int cpu; 33 u32 address; 34 u16 interrupt_enable; 35 bool interrupt_capable; 36 u16 threshold_limit; 37 struct kobject kobj; 38 struct list_head miscj; 39 }; 40 41 struct threshold_bank { 42 struct kobject *kobj; 43 struct threshold_block *blocks; 44 45 /* initialized to the number of CPUs on the node sharing this bank */ 46 atomic_t cpus; 47 }; 48 49 struct amd_northbridge { 50 struct pci_dev *misc; 51 struct pci_dev *link; 52 struct amd_l3_cache l3_cache; 53 struct threshold_bank *bank4; 54 }; 55 56 struct amd_northbridge_info { 57 u16 num; 58 u64 flags; 59 struct amd_northbridge *nb; 60 }; 61 extern struct amd_northbridge_info amd_northbridges; 62 63 #define AMD_NB_GART BIT(0) 64 #define AMD_NB_L3_INDEX_DISABLE BIT(1) 65 #define AMD_NB_L3_PARTITIONING BIT(2) 66 67 #ifdef CONFIG_AMD_NB 68 amd_nb_num(void)69static inline u16 amd_nb_num(void) 70 { 71 return amd_northbridges.num; 72 } 73 amd_nb_has_feature(unsigned feature)74static inline bool amd_nb_has_feature(unsigned feature) 75 { 76 return ((amd_northbridges.flags & feature) == feature); 77 } 78 node_to_amd_nb(int node)79static inline struct amd_northbridge *node_to_amd_nb(int node) 80 { 81 return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL; 82 } 83 amd_pci_dev_to_node_id(struct pci_dev * pdev)84static inline u16 amd_pci_dev_to_node_id(struct pci_dev *pdev) 85 { 86 struct pci_dev *misc; 87 int i; 88 89 for (i = 0; i != amd_nb_num(); i++) { 90 misc = node_to_amd_nb(i)->misc; 91 92 if (pci_domain_nr(misc->bus) == pci_domain_nr(pdev->bus) && 93 PCI_SLOT(misc->devfn) == PCI_SLOT(pdev->devfn)) 94 return i; 95 } 96 97 WARN(1, "Unable to find AMD Northbridge id for %s\n", pci_name(pdev)); 98 return 0; 99 } 100 amd_gart_present(void)101static inline bool amd_gart_present(void) 102 { 103 /* GART present only on Fam15h, upto model 0fh */ 104 if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 || 105 (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10)) 106 return true; 107 108 return false; 109 } 110 111 #else 112 113 #define amd_nb_num(x) 0 114 #define amd_nb_has_feature(x) false 115 #define node_to_amd_nb(x) NULL 116 #define amd_gart_present(x) false 117 118 #endif 119 120 121 #endif /* _ASM_X86_AMD_NB_H */ 122