1 #ifndef _ASM_X86_PGTABLE_DEFS_H
2 #define _ASM_X86_PGTABLE_DEFS_H
3
4 #include <linux/const.h>
5 #include <asm/page_types.h>
6
7 #define FIRST_USER_ADDRESS 0UL
8
9 #define _PAGE_BIT_PRESENT 0 /* is present */
10 #define _PAGE_BIT_RW 1 /* writeable */
11 #define _PAGE_BIT_USER 2 /* userspace addressable */
12 #define _PAGE_BIT_PWT 3 /* page write through */
13 #define _PAGE_BIT_PCD 4 /* page cache disabled */
14 #define _PAGE_BIT_ACCESSED 5 /* was accessed (raised by CPU) */
15 #define _PAGE_BIT_DIRTY 6 /* was written to (raised by CPU) */
16 #define _PAGE_BIT_PSE 7 /* 4 MB (or 2MB) page */
17 #define _PAGE_BIT_PAT 7 /* on 4KB pages */
18 #define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */
19 #define _PAGE_BIT_SOFTW1 9 /* available for programmer */
20 #define _PAGE_BIT_SOFTW2 10 /* " */
21 #define _PAGE_BIT_SOFTW3 11 /* " */
22 #define _PAGE_BIT_PAT_LARGE 12 /* On 2MB or 1GB pages */
23 #define _PAGE_BIT_SPECIAL _PAGE_BIT_SOFTW1
24 #define _PAGE_BIT_CPA_TEST _PAGE_BIT_SOFTW1
25 #define _PAGE_BIT_SPLITTING _PAGE_BIT_SOFTW2 /* only valid on a PSE pmd */
26 #define _PAGE_BIT_HIDDEN _PAGE_BIT_SOFTW3 /* hidden by kmemcheck */
27 #define _PAGE_BIT_SOFT_DIRTY _PAGE_BIT_SOFTW3 /* software dirty tracking */
28 #define _PAGE_BIT_NX 63 /* No execute: only valid after cpuid check */
29
30 /* If _PAGE_BIT_PRESENT is clear, we use these: */
31 /* - if the user mapped it with PROT_NONE; pte_present gives true */
32 #define _PAGE_BIT_PROTNONE _PAGE_BIT_GLOBAL
33
34 #define _PAGE_PRESENT (_AT(pteval_t, 1) << _PAGE_BIT_PRESENT)
35 #define _PAGE_RW (_AT(pteval_t, 1) << _PAGE_BIT_RW)
36 #define _PAGE_USER (_AT(pteval_t, 1) << _PAGE_BIT_USER)
37 #define _PAGE_PWT (_AT(pteval_t, 1) << _PAGE_BIT_PWT)
38 #define _PAGE_PCD (_AT(pteval_t, 1) << _PAGE_BIT_PCD)
39 #define _PAGE_ACCESSED (_AT(pteval_t, 1) << _PAGE_BIT_ACCESSED)
40 #define _PAGE_DIRTY (_AT(pteval_t, 1) << _PAGE_BIT_DIRTY)
41 #define _PAGE_PSE (_AT(pteval_t, 1) << _PAGE_BIT_PSE)
42 #define _PAGE_GLOBAL (_AT(pteval_t, 1) << _PAGE_BIT_GLOBAL)
43 #define _PAGE_SOFTW1 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW1)
44 #define _PAGE_SOFTW2 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW2)
45 #define _PAGE_PAT (_AT(pteval_t, 1) << _PAGE_BIT_PAT)
46 #define _PAGE_PAT_LARGE (_AT(pteval_t, 1) << _PAGE_BIT_PAT_LARGE)
47 #define _PAGE_SPECIAL (_AT(pteval_t, 1) << _PAGE_BIT_SPECIAL)
48 #define _PAGE_CPA_TEST (_AT(pteval_t, 1) << _PAGE_BIT_CPA_TEST)
49 #define _PAGE_SPLITTING (_AT(pteval_t, 1) << _PAGE_BIT_SPLITTING)
50 #define __HAVE_ARCH_PTE_SPECIAL
51
52 #ifdef CONFIG_KMEMCHECK
53 #define _PAGE_HIDDEN (_AT(pteval_t, 1) << _PAGE_BIT_HIDDEN)
54 #else
55 #define _PAGE_HIDDEN (_AT(pteval_t, 0))
56 #endif
57
58 /*
59 * The same hidden bit is used by kmemcheck, but since kmemcheck
60 * works on kernel pages while soft-dirty engine on user space,
61 * they do not conflict with each other.
62 */
63
64 #ifdef CONFIG_MEM_SOFT_DIRTY
65 #define _PAGE_SOFT_DIRTY (_AT(pteval_t, 1) << _PAGE_BIT_SOFT_DIRTY)
66 #else
67 #define _PAGE_SOFT_DIRTY (_AT(pteval_t, 0))
68 #endif
69
70 /*
71 * Tracking soft dirty bit when a page goes to a swap is tricky.
72 * We need a bit which can be stored in pte _and_ not conflict
73 * with swap entry format. On x86 bits 1-4 are *not* involved
74 * into swap entry computation, but bit 7 is used for thp migration,
75 * so we borrow bit 1 for soft dirty tracking.
76 *
77 * Please note that this bit must be treated as swap dirty page
78 * mark if and only if the PTE/PMD has present bit clear!
79 */
80 #ifdef CONFIG_MEM_SOFT_DIRTY
81 #define _PAGE_SWP_SOFT_DIRTY _PAGE_RW
82 #else
83 #define _PAGE_SWP_SOFT_DIRTY (_AT(pteval_t, 0))
84 #endif
85
86 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
87 #define _PAGE_NX (_AT(pteval_t, 1) << _PAGE_BIT_NX)
88 #else
89 #define _PAGE_NX (_AT(pteval_t, 0))
90 #endif
91
92 #define _PAGE_PROTNONE (_AT(pteval_t, 1) << _PAGE_BIT_PROTNONE)
93
94 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
95 _PAGE_ACCESSED | _PAGE_DIRTY)
96 #define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | \
97 _PAGE_DIRTY)
98
99 /* Set of bits not changed in pte_modify */
100 #define _PAGE_CHG_MASK (PTE_PFN_MASK | _PAGE_PCD | _PAGE_PWT | \
101 _PAGE_SPECIAL | _PAGE_ACCESSED | _PAGE_DIRTY | \
102 _PAGE_SOFT_DIRTY)
103 #define _HPAGE_CHG_MASK (_PAGE_CHG_MASK | _PAGE_PSE)
104
105 /* The ASID is the lower 12 bits of CR3 */
106 #define X86_CR3_PCID_ASID_MASK (_AC((1<<12)-1,UL))
107
108 /* Mask for all the PCID-related bits in CR3: */
109 #define X86_CR3_PCID_MASK (X86_CR3_PCID_NOFLUSH | X86_CR3_PCID_ASID_MASK)
110 #define X86_CR3_PCID_ASID_KERN (_AC(0x0,UL))
111
112 #if defined(CONFIG_PAGE_TABLE_ISOLATION) && defined(CONFIG_X86_64)
113 /* Let X86_CR3_PCID_ASID_USER be usable for the X86_CR3_PCID_NOFLUSH bit */
114 #define X86_CR3_PCID_ASID_USER (_AC(0x80,UL))
115
116 #define X86_CR3_PCID_KERN_FLUSH (X86_CR3_PCID_ASID_KERN)
117 #define X86_CR3_PCID_USER_FLUSH (X86_CR3_PCID_ASID_USER)
118 #define X86_CR3_PCID_KERN_NOFLUSH (X86_CR3_PCID_NOFLUSH | X86_CR3_PCID_ASID_KERN)
119 #define X86_CR3_PCID_USER_NOFLUSH (X86_CR3_PCID_NOFLUSH | X86_CR3_PCID_ASID_USER)
120 #else
121 #define X86_CR3_PCID_ASID_USER (_AC(0x0,UL))
122 /*
123 * PCIDs are unsupported on 32-bit and none of these bits can be
124 * set in CR3:
125 */
126 #define X86_CR3_PCID_KERN_FLUSH (0)
127 #define X86_CR3_PCID_USER_FLUSH (0)
128 #define X86_CR3_PCID_KERN_NOFLUSH (0)
129 #define X86_CR3_PCID_USER_NOFLUSH (0)
130 #endif
131
132 /*
133 * The cache modes defined here are used to translate between pure SW usage
134 * and the HW defined cache mode bits and/or PAT entries.
135 *
136 * The resulting bits for PWT, PCD and PAT should be chosen in a way
137 * to have the WB mode at index 0 (all bits clear). This is the default
138 * right now and likely would break too much if changed.
139 */
140 #ifndef __ASSEMBLY__
141 enum page_cache_mode {
142 _PAGE_CACHE_MODE_WB = 0,
143 _PAGE_CACHE_MODE_WC = 1,
144 _PAGE_CACHE_MODE_UC_MINUS = 2,
145 _PAGE_CACHE_MODE_UC = 3,
146 _PAGE_CACHE_MODE_WT = 4,
147 _PAGE_CACHE_MODE_WP = 5,
148 _PAGE_CACHE_MODE_NUM = 8
149 };
150 #endif
151
152 #define _PAGE_CACHE_MASK (_PAGE_PAT | _PAGE_PCD | _PAGE_PWT)
153 #define _PAGE_NOCACHE (cachemode2protval(_PAGE_CACHE_MODE_UC))
154
155 #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
156 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
157 _PAGE_ACCESSED | _PAGE_NX)
158
159 #define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | _PAGE_RW | \
160 _PAGE_USER | _PAGE_ACCESSED)
161 #define PAGE_COPY_NOEXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | \
162 _PAGE_ACCESSED | _PAGE_NX)
163 #define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | \
164 _PAGE_ACCESSED)
165 #define PAGE_COPY PAGE_COPY_NOEXEC
166 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | \
167 _PAGE_ACCESSED | _PAGE_NX)
168 #define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | \
169 _PAGE_ACCESSED)
170
171 #define __PAGE_KERNEL_EXEC \
172 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_GLOBAL)
173 #define __PAGE_KERNEL (__PAGE_KERNEL_EXEC | _PAGE_NX)
174
175 #define __PAGE_KERNEL_RO (__PAGE_KERNEL & ~_PAGE_RW)
176 #define __PAGE_KERNEL_RX (__PAGE_KERNEL_EXEC & ~_PAGE_RW)
177 #define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL | _PAGE_NOCACHE)
178 #define __PAGE_KERNEL_VSYSCALL (__PAGE_KERNEL_RX | _PAGE_USER)
179 #define __PAGE_KERNEL_VVAR (__PAGE_KERNEL_RO | _PAGE_USER)
180 #define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE)
181 #define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE)
182
183 #define __PAGE_KERNEL_IO (__PAGE_KERNEL)
184 #define __PAGE_KERNEL_IO_NOCACHE (__PAGE_KERNEL_NOCACHE)
185
186 #define PAGE_KERNEL __pgprot(__PAGE_KERNEL)
187 #define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO)
188 #define PAGE_KERNEL_EXEC __pgprot(__PAGE_KERNEL_EXEC)
189 #define PAGE_KERNEL_RX __pgprot(__PAGE_KERNEL_RX)
190 #define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE)
191 #define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE)
192 #define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC)
193 #define PAGE_KERNEL_VSYSCALL __pgprot(__PAGE_KERNEL_VSYSCALL)
194 #define PAGE_KERNEL_VVAR __pgprot(__PAGE_KERNEL_VVAR)
195
196 #define PAGE_KERNEL_IO __pgprot(__PAGE_KERNEL_IO)
197 #define PAGE_KERNEL_IO_NOCACHE __pgprot(__PAGE_KERNEL_IO_NOCACHE)
198
199 /* xwr */
200 #define __P000 PAGE_NONE
201 #define __P001 PAGE_READONLY
202 #define __P010 PAGE_COPY
203 #define __P011 PAGE_COPY
204 #define __P100 PAGE_READONLY_EXEC
205 #define __P101 PAGE_READONLY_EXEC
206 #define __P110 PAGE_COPY_EXEC
207 #define __P111 PAGE_COPY_EXEC
208
209 #define __S000 PAGE_NONE
210 #define __S001 PAGE_READONLY
211 #define __S010 PAGE_SHARED
212 #define __S011 PAGE_SHARED
213 #define __S100 PAGE_READONLY_EXEC
214 #define __S101 PAGE_READONLY_EXEC
215 #define __S110 PAGE_SHARED_EXEC
216 #define __S111 PAGE_SHARED_EXEC
217
218 /*
219 * early identity mapping pte attrib macros.
220 */
221 #ifdef CONFIG_X86_64
222 #define __PAGE_KERNEL_IDENT_LARGE_EXEC __PAGE_KERNEL_LARGE_EXEC
223 #else
224 #define PTE_IDENT_ATTR 0x003 /* PRESENT+RW */
225 #define PDE_IDENT_ATTR 0x063 /* PRESENT+RW+DIRTY+ACCESSED */
226 #define PGD_IDENT_ATTR 0x001 /* PRESENT (no other attributes) */
227 #endif
228
229 #ifdef CONFIG_X86_32
230 # include <asm/pgtable_32_types.h>
231 #else
232 # include <asm/pgtable_64_types.h>
233 #endif
234
235 #ifndef __ASSEMBLY__
236
237 #include <linux/types.h>
238
239 /* Extracts the PFN from a (pte|pmd|pud|pgd)val_t of a 4KB page */
240 #define PTE_PFN_MASK ((pteval_t)PHYSICAL_PAGE_MASK)
241
242 /* Extracts the flags from a (pte|pmd|pud|pgd)val_t of a 4KB page */
243 #define PTE_FLAGS_MASK (~PTE_PFN_MASK)
244
245 typedef struct pgprot { pgprotval_t pgprot; } pgprot_t;
246
247 typedef struct { pgdval_t pgd; } pgd_t;
248
native_make_pgd(pgdval_t val)249 static inline pgd_t native_make_pgd(pgdval_t val)
250 {
251 return (pgd_t) { val };
252 }
253
native_pgd_val(pgd_t pgd)254 static inline pgdval_t native_pgd_val(pgd_t pgd)
255 {
256 return pgd.pgd;
257 }
258
pgd_flags(pgd_t pgd)259 static inline pgdval_t pgd_flags(pgd_t pgd)
260 {
261 return native_pgd_val(pgd) & PTE_FLAGS_MASK;
262 }
263
264 #if CONFIG_PGTABLE_LEVELS > 3
265 typedef struct { pudval_t pud; } pud_t;
266
native_make_pud(pmdval_t val)267 static inline pud_t native_make_pud(pmdval_t val)
268 {
269 return (pud_t) { val };
270 }
271
native_pud_val(pud_t pud)272 static inline pudval_t native_pud_val(pud_t pud)
273 {
274 return pud.pud;
275 }
276 #else
277 #include <asm-generic/pgtable-nopud.h>
278
native_pud_val(pud_t pud)279 static inline pudval_t native_pud_val(pud_t pud)
280 {
281 return native_pgd_val(pud.pgd);
282 }
283 #endif
284
285 #if CONFIG_PGTABLE_LEVELS > 2
286 typedef struct { pmdval_t pmd; } pmd_t;
287
native_make_pmd(pmdval_t val)288 static inline pmd_t native_make_pmd(pmdval_t val)
289 {
290 return (pmd_t) { val };
291 }
292
native_pmd_val(pmd_t pmd)293 static inline pmdval_t native_pmd_val(pmd_t pmd)
294 {
295 return pmd.pmd;
296 }
297 #else
298 #include <asm-generic/pgtable-nopmd.h>
299
native_pmd_val(pmd_t pmd)300 static inline pmdval_t native_pmd_val(pmd_t pmd)
301 {
302 return native_pgd_val(pmd.pud.pgd);
303 }
304 #endif
305
pud_pfn_mask(pud_t pud)306 static inline pudval_t pud_pfn_mask(pud_t pud)
307 {
308 if (native_pud_val(pud) & _PAGE_PSE)
309 return PHYSICAL_PUD_PAGE_MASK;
310 else
311 return PTE_PFN_MASK;
312 }
313
pud_flags_mask(pud_t pud)314 static inline pudval_t pud_flags_mask(pud_t pud)
315 {
316 return ~pud_pfn_mask(pud);
317 }
318
pud_flags(pud_t pud)319 static inline pudval_t pud_flags(pud_t pud)
320 {
321 return native_pud_val(pud) & pud_flags_mask(pud);
322 }
323
pmd_pfn_mask(pmd_t pmd)324 static inline pmdval_t pmd_pfn_mask(pmd_t pmd)
325 {
326 if (native_pmd_val(pmd) & _PAGE_PSE)
327 return PHYSICAL_PMD_PAGE_MASK;
328 else
329 return PTE_PFN_MASK;
330 }
331
pmd_flags_mask(pmd_t pmd)332 static inline pmdval_t pmd_flags_mask(pmd_t pmd)
333 {
334 return ~pmd_pfn_mask(pmd);
335 }
336
pmd_flags(pmd_t pmd)337 static inline pmdval_t pmd_flags(pmd_t pmd)
338 {
339 return native_pmd_val(pmd) & pmd_flags_mask(pmd);
340 }
341
native_make_pte(pteval_t val)342 static inline pte_t native_make_pte(pteval_t val)
343 {
344 return (pte_t) { .pte = val };
345 }
346
native_pte_val(pte_t pte)347 static inline pteval_t native_pte_val(pte_t pte)
348 {
349 return pte.pte;
350 }
351
pte_flags(pte_t pte)352 static inline pteval_t pte_flags(pte_t pte)
353 {
354 return native_pte_val(pte) & PTE_FLAGS_MASK;
355 }
356
357 #define pgprot_val(x) ((x).pgprot)
358 #define __pgprot(x) ((pgprot_t) { (x) } )
359
360 extern uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM];
361 extern uint8_t __pte2cachemode_tbl[8];
362
363 #define __pte2cm_idx(cb) \
364 ((((cb) >> (_PAGE_BIT_PAT - 2)) & 4) | \
365 (((cb) >> (_PAGE_BIT_PCD - 1)) & 2) | \
366 (((cb) >> _PAGE_BIT_PWT) & 1))
367 #define __cm_idx2pte(i) \
368 ((((i) & 4) << (_PAGE_BIT_PAT - 2)) | \
369 (((i) & 2) << (_PAGE_BIT_PCD - 1)) | \
370 (((i) & 1) << _PAGE_BIT_PWT))
371
cachemode2protval(enum page_cache_mode pcm)372 static inline unsigned long cachemode2protval(enum page_cache_mode pcm)
373 {
374 if (likely(pcm == 0))
375 return 0;
376 return __cachemode2pte_tbl[pcm];
377 }
cachemode2pgprot(enum page_cache_mode pcm)378 static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)
379 {
380 return __pgprot(cachemode2protval(pcm));
381 }
pgprot2cachemode(pgprot_t pgprot)382 static inline enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)
383 {
384 unsigned long masked;
385
386 masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK;
387 if (likely(masked == 0))
388 return 0;
389 return __pte2cachemode_tbl[__pte2cm_idx(masked)];
390 }
pgprot_4k_2_large(pgprot_t pgprot)391 static inline pgprot_t pgprot_4k_2_large(pgprot_t pgprot)
392 {
393 pgprotval_t val = pgprot_val(pgprot);
394 pgprot_t new;
395
396 pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
397 ((val & _PAGE_PAT) << (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
398 return new;
399 }
pgprot_large_2_4k(pgprot_t pgprot)400 static inline pgprot_t pgprot_large_2_4k(pgprot_t pgprot)
401 {
402 pgprotval_t val = pgprot_val(pgprot);
403 pgprot_t new;
404
405 pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
406 ((val & _PAGE_PAT_LARGE) >>
407 (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
408 return new;
409 }
410
411
412 typedef struct page *pgtable_t;
413
414 extern pteval_t __supported_pte_mask;
415 extern void set_nx(void);
416 extern int nx_enabled;
417
418 #define pgprot_writecombine pgprot_writecombine
419 extern pgprot_t pgprot_writecombine(pgprot_t prot);
420
421 #define pgprot_writethrough pgprot_writethrough
422 extern pgprot_t pgprot_writethrough(pgprot_t prot);
423
424 /* Indicate that x86 has its own track and untrack pfn vma functions */
425 #define __HAVE_PFNMAP_TRACKING
426
427 #define __HAVE_PHYS_MEM_ACCESS_PROT
428 struct file;
429 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
430 unsigned long size, pgprot_t vma_prot);
431 int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
432 unsigned long size, pgprot_t *vma_prot);
433
434 /* Install a pte for a particular vaddr in kernel space. */
435 void set_pte_vaddr(unsigned long vaddr, pte_t pte);
436
437 #ifdef CONFIG_X86_32
438 extern void native_pagetable_init(void);
439 #else
440 #define native_pagetable_init paging_init
441 #endif
442
443 struct seq_file;
444 extern void arch_report_meminfo(struct seq_file *m);
445
446 enum pg_level {
447 PG_LEVEL_NONE,
448 PG_LEVEL_4K,
449 PG_LEVEL_2M,
450 PG_LEVEL_1G,
451 PG_LEVEL_NUM
452 };
453
454 #ifdef CONFIG_PROC_FS
455 extern void update_page_count(int level, unsigned long pages);
456 #else
update_page_count(int level,unsigned long pages)457 static inline void update_page_count(int level, unsigned long pages) { }
458 #endif
459
460 /*
461 * Helper function that returns the kernel pagetable entry controlling
462 * the virtual address 'address'. NULL means no pagetable entry present.
463 * NOTE: the return type is pte_t but if the pmd is PSE then we return it
464 * as a pte too.
465 */
466 extern pte_t *lookup_address(unsigned long address, unsigned int *level);
467 extern pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address,
468 unsigned int *level);
469 extern pmd_t *lookup_pmd_address(unsigned long address);
470 extern phys_addr_t slow_virt_to_phys(void *__address);
471 extern int kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, unsigned long address,
472 unsigned numpages, unsigned long page_flags);
473 void kernel_unmap_pages_in_pgd(pgd_t *root, unsigned long address,
474 unsigned numpages);
475 #endif /* !__ASSEMBLY__ */
476
477 #endif /* _ASM_X86_PGTABLE_DEFS_H */
478