1 #ifndef _SPARC_TRAP_BLOCK_H 2 #define _SPARC_TRAP_BLOCK_H 3 4 #include <asm/hypervisor.h> 5 #include <asm/asi.h> 6 7 #ifndef __ASSEMBLY__ 8 9 /* Trap handling code needs to get at a few critical values upon 10 * trap entry and to process TSB misses. These cannot be in the 11 * per_cpu() area as we really need to lock them into the TLB and 12 * thus make them part of the main kernel image. As a result we 13 * try to make this as small as possible. 14 * 15 * This is padded out and aligned to 64-bytes to avoid false sharing 16 * on SMP. 17 */ 18 19 /* If you modify the size of this structure, please update 20 * TRAP_BLOCK_SZ_SHIFT below. 21 */ 22 struct thread_info; 23 struct trap_per_cpu { 24 /* D-cache line 1: Basic thread information, cpu and device mondo queues */ 25 struct thread_info *thread; 26 unsigned long pgd_paddr; 27 unsigned long cpu_mondo_pa; 28 unsigned long dev_mondo_pa; 29 30 /* D-cache line 2: Error Mondo Queue and kernel buffer pointers */ 31 unsigned long resum_mondo_pa; 32 unsigned long resum_kernel_buf_pa; 33 unsigned long nonresum_mondo_pa; 34 unsigned long nonresum_kernel_buf_pa; 35 36 /* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */ 37 struct hv_fault_status fault_info; 38 39 /* Dcache line 7: Physical addresses of CPU send mondo block and CPU list. */ 40 unsigned long cpu_mondo_block_pa; 41 unsigned long cpu_list_pa; 42 unsigned long tsb_huge; 43 unsigned long tsb_huge_temp; 44 45 /* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size. */ 46 unsigned long irq_worklist_pa; 47 unsigned int cpu_mondo_qmask; 48 unsigned int dev_mondo_qmask; 49 unsigned int resum_qmask; 50 unsigned int nonresum_qmask; 51 unsigned long __per_cpu_base; 52 } __attribute__((aligned(64))); 53 extern struct trap_per_cpu trap_block[NR_CPUS]; 54 void init_cur_cpu_trap(struct thread_info *); 55 void setup_tba(void); 56 extern int ncpus_probed; 57 extern u64 cpu_mondo_counter[NR_CPUS]; 58 59 unsigned long real_hard_smp_processor_id(void); 60 61 struct cpuid_patch_entry { 62 unsigned int addr; 63 unsigned int cheetah_safari[4]; 64 unsigned int cheetah_jbus[4]; 65 unsigned int starfire[4]; 66 unsigned int sun4v[4]; 67 }; 68 extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end; 69 70 struct sun4v_1insn_patch_entry { 71 unsigned int addr; 72 unsigned int insn; 73 }; 74 extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch, 75 __sun4v_1insn_patch_end; 76 77 struct sun4v_2insn_patch_entry { 78 unsigned int addr; 79 unsigned int insns[2]; 80 }; 81 extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch, 82 __sun4v_2insn_patch_end; 83 extern struct sun4v_2insn_patch_entry __sun_m7_2insn_patch, 84 __sun_m7_2insn_patch_end; 85 86 87 #endif /* !(__ASSEMBLY__) */ 88 89 #define TRAP_PER_CPU_THREAD 0x00 90 #define TRAP_PER_CPU_PGD_PADDR 0x08 91 #define TRAP_PER_CPU_CPU_MONDO_PA 0x10 92 #define TRAP_PER_CPU_DEV_MONDO_PA 0x18 93 #define TRAP_PER_CPU_RESUM_MONDO_PA 0x20 94 #define TRAP_PER_CPU_RESUM_KBUF_PA 0x28 95 #define TRAP_PER_CPU_NONRESUM_MONDO_PA 0x30 96 #define TRAP_PER_CPU_NONRESUM_KBUF_PA 0x38 97 #define TRAP_PER_CPU_FAULT_INFO 0x40 98 #define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0 99 #define TRAP_PER_CPU_CPU_LIST_PA 0xc8 100 #define TRAP_PER_CPU_TSB_HUGE 0xd0 101 #define TRAP_PER_CPU_TSB_HUGE_TEMP 0xd8 102 #define TRAP_PER_CPU_IRQ_WORKLIST_PA 0xe0 103 #define TRAP_PER_CPU_CPU_MONDO_QMASK 0xe8 104 #define TRAP_PER_CPU_DEV_MONDO_QMASK 0xec 105 #define TRAP_PER_CPU_RESUM_QMASK 0xf0 106 #define TRAP_PER_CPU_NONRESUM_QMASK 0xf4 107 #define TRAP_PER_CPU_PER_CPU_BASE 0xf8 108 109 #define TRAP_BLOCK_SZ_SHIFT 8 110 111 #include <asm/scratchpad.h> 112 113 #define __GET_CPUID(REG) \ 114 /* Spitfire implementation (default). */ \ 115 661: ldxa [%g0] ASI_UPA_CONFIG, REG; \ 116 srlx REG, 17, REG; \ 117 and REG, 0x1f, REG; \ 118 nop; \ 119 .section .cpuid_patch, "ax"; \ 120 /* Instruction location. */ \ 121 .word 661b; \ 122 /* Cheetah Safari implementation. */ \ 123 ldxa [%g0] ASI_SAFARI_CONFIG, REG; \ 124 srlx REG, 17, REG; \ 125 and REG, 0x3ff, REG; \ 126 nop; \ 127 /* Cheetah JBUS implementation. */ \ 128 ldxa [%g0] ASI_JBUS_CONFIG, REG; \ 129 srlx REG, 17, REG; \ 130 and REG, 0x1f, REG; \ 131 nop; \ 132 /* Starfire implementation. */ \ 133 sethi %hi(0x1fff40000d0 >> 9), REG; \ 134 sllx REG, 9, REG; \ 135 or REG, 0xd0, REG; \ 136 lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\ 137 /* sun4v implementation. */ \ 138 mov SCRATCHPAD_CPUID, REG; \ 139 ldxa [REG] ASI_SCRATCHPAD, REG; \ 140 nop; \ 141 nop; \ 142 .previous; 143 144 #ifdef CONFIG_SMP 145 146 #define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ 147 __GET_CPUID(TMP) \ 148 sethi %hi(trap_block), DEST; \ 149 sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \ 150 or DEST, %lo(trap_block), DEST; \ 151 add DEST, TMP, DEST; \ 152 153 /* Clobbers TMP, current address space PGD phys address into DEST. */ 154 #define TRAP_LOAD_PGD_PHYS(DEST, TMP) \ 155 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ 156 ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST; 157 158 /* Clobbers TMP, loads local processor's IRQ work area into DEST. */ 159 #define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP) \ 160 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ 161 add DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST; 162 163 /* Clobbers TMP, loads DEST with current thread info pointer. */ 164 #define TRAP_LOAD_THREAD_REG(DEST, TMP) \ 165 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ 166 ldx [DEST + TRAP_PER_CPU_THREAD], DEST; 167 168 /* Given the current thread info pointer in THR, load the per-cpu 169 * area base of the current processor into DEST. REG1, REG2, and REG3 are 170 * clobbered. 171 * 172 * You absolutely cannot use DEST as a temporary in this code. The 173 * reason is that traps can happen during execution, and return from 174 * trap will load the fully resolved DEST per-cpu base. This can corrupt 175 * the calculations done by the macro mid-stream. 176 */ 177 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \ 178 lduh [THR + TI_CPU], REG1; \ 179 sethi %hi(trap_block), REG2; \ 180 sllx REG1, TRAP_BLOCK_SZ_SHIFT, REG1; \ 181 or REG2, %lo(trap_block), REG2; \ 182 add REG2, REG1, REG2; \ 183 ldx [REG2 + TRAP_PER_CPU_PER_CPU_BASE], DEST; 184 185 #else 186 187 #define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ 188 sethi %hi(trap_block), DEST; \ 189 or DEST, %lo(trap_block), DEST; \ 190 191 /* Uniprocessor versions, we know the cpuid is zero. */ 192 #define TRAP_LOAD_PGD_PHYS(DEST, TMP) \ 193 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ 194 ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST; 195 196 /* Clobbers TMP, loads local processor's IRQ work area into DEST. */ 197 #define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP) \ 198 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ 199 add DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST; 200 201 #define TRAP_LOAD_THREAD_REG(DEST, TMP) \ 202 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ 203 ldx [DEST + TRAP_PER_CPU_THREAD], DEST; 204 205 /* No per-cpu areas on uniprocessor, so no need to load DEST. */ 206 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) 207 208 #endif /* !(CONFIG_SMP) */ 209 210 #endif /* _SPARC_TRAP_BLOCK_H */ 211