1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2007 Cavium Networks
7 * Copyright (C) 2008, 2009 Wind River Systems
8 * written by Ralf Baechle <ralf@linux-mips.org>
9 */
10 #include <linux/compiler.h>
11 #include <linux/vmalloc.h>
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/console.h>
15 #include <linux/delay.h>
16 #include <linux/export.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/serial.h>
20 #include <linux/smp.h>
21 #include <linux/types.h>
22 #include <linux/string.h> /* for memset */
23 #include <linux/tty.h>
24 #include <linux/time.h>
25 #include <linux/platform_device.h>
26 #include <linux/serial_core.h>
27 #include <linux/serial_8250.h>
28 #include <linux/of_fdt.h>
29 #include <linux/libfdt.h>
30 #include <linux/kexec.h>
31
32 #include <asm/processor.h>
33 #include <asm/reboot.h>
34 #include <asm/smp-ops.h>
35 #include <asm/irq_cpu.h>
36 #include <asm/mipsregs.h>
37 #include <asm/bootinfo.h>
38 #include <asm/sections.h>
39 #include <asm/time.h>
40
41 #include <asm/octeon/octeon.h>
42 #include <asm/octeon/pci-octeon.h>
43 #include <asm/octeon/cvmx-mio-defs.h>
44 #include <asm/octeon/cvmx-rst-defs.h>
45
46 extern struct plat_smp_ops octeon_smp_ops;
47
48 #ifdef CONFIG_PCI
49 extern void pci_console_init(const char *arg);
50 #endif
51
52 static unsigned long long MAX_MEMORY = 512ull << 20;
53
54 DEFINE_SEMAPHORE(octeon_bootbus_sem);
55 EXPORT_SYMBOL(octeon_bootbus_sem);
56
57 struct octeon_boot_descriptor *octeon_boot_desc_ptr;
58
59 struct cvmx_bootinfo *octeon_bootinfo;
60 EXPORT_SYMBOL(octeon_bootinfo);
61
62 static unsigned long long RESERVE_LOW_MEM = 0ull;
63 #ifdef CONFIG_KEXEC
64 #ifdef CONFIG_SMP
65 /*
66 * Wait for relocation code is prepared and send
67 * secondary CPUs to spin until kernel is relocated.
68 */
octeon_kexec_smp_down(void * ignored)69 static void octeon_kexec_smp_down(void *ignored)
70 {
71 int cpu = smp_processor_id();
72
73 local_irq_disable();
74 set_cpu_online(cpu, false);
75 while (!atomic_read(&kexec_ready_to_reboot))
76 cpu_relax();
77
78 asm volatile (
79 " sync \n"
80 " synci ($0) \n");
81
82 relocated_kexec_smp_wait(NULL);
83 }
84 #endif
85
86 #define OCTEON_DDR0_BASE (0x0ULL)
87 #define OCTEON_DDR0_SIZE (0x010000000ULL)
88 #define OCTEON_DDR1_BASE (0x410000000ULL)
89 #define OCTEON_DDR1_SIZE (0x010000000ULL)
90 #define OCTEON_DDR2_BASE (0x020000000ULL)
91 #define OCTEON_DDR2_SIZE (0x3e0000000ULL)
92 #define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL)
93
94 static struct kimage *kimage_ptr;
95
kexec_bootmem_init(uint64_t mem_size,uint32_t low_reserved_bytes)96 static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes)
97 {
98 int64_t addr;
99 struct cvmx_bootmem_desc *bootmem_desc;
100
101 bootmem_desc = cvmx_bootmem_get_desc();
102
103 if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) {
104 mem_size = OCTEON_MAX_PHY_MEM_SIZE;
105 pr_err("Error: requested memory too large,"
106 "truncating to maximum size\n");
107 }
108
109 bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER;
110 bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER;
111
112 addr = (OCTEON_DDR0_BASE + RESERVE_LOW_MEM + low_reserved_bytes);
113 bootmem_desc->head_addr = 0;
114
115 if (mem_size <= OCTEON_DDR0_SIZE) {
116 __cvmx_bootmem_phy_free(addr,
117 mem_size - RESERVE_LOW_MEM -
118 low_reserved_bytes, 0);
119 return;
120 }
121
122 __cvmx_bootmem_phy_free(addr,
123 OCTEON_DDR0_SIZE - RESERVE_LOW_MEM -
124 low_reserved_bytes, 0);
125
126 mem_size -= OCTEON_DDR0_SIZE;
127
128 if (mem_size > OCTEON_DDR1_SIZE) {
129 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0);
130 __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE,
131 mem_size - OCTEON_DDR1_SIZE, 0);
132 } else
133 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0);
134 }
135
octeon_kexec_prepare(struct kimage * image)136 static int octeon_kexec_prepare(struct kimage *image)
137 {
138 int i;
139 char *bootloader = "kexec";
140
141 octeon_boot_desc_ptr->argc = 0;
142 for (i = 0; i < image->nr_segments; i++) {
143 if (!strncmp(bootloader, (char *)image->segment[i].buf,
144 strlen(bootloader))) {
145 /*
146 * convert command line string to array
147 * of parameters (as bootloader does).
148 */
149 int argc = 0, offt;
150 char *str = (char *)image->segment[i].buf;
151 char *ptr = strchr(str, ' ');
152 while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) {
153 *ptr = '\0';
154 if (ptr[1] != ' ') {
155 offt = (int)(ptr - str + 1);
156 octeon_boot_desc_ptr->argv[argc] =
157 image->segment[i].mem + offt;
158 argc++;
159 }
160 ptr = strchr(ptr + 1, ' ');
161 }
162 octeon_boot_desc_ptr->argc = argc;
163 break;
164 }
165 }
166
167 /*
168 * Information about segments will be needed during pre-boot memory
169 * initialization.
170 */
171 kimage_ptr = image;
172 return 0;
173 }
174
octeon_generic_shutdown(void)175 static void octeon_generic_shutdown(void)
176 {
177 int i;
178 #ifdef CONFIG_SMP
179 int cpu;
180 #endif
181 struct cvmx_bootmem_desc *bootmem_desc;
182 void *named_block_array_ptr;
183
184 bootmem_desc = cvmx_bootmem_get_desc();
185 named_block_array_ptr =
186 cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr);
187
188 #ifdef CONFIG_SMP
189 /* disable watchdogs */
190 for_each_online_cpu(cpu)
191 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
192 #else
193 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
194 #endif
195 if (kimage_ptr != kexec_crash_image) {
196 memset(named_block_array_ptr,
197 0x0,
198 CVMX_BOOTMEM_NUM_NAMED_BLOCKS *
199 sizeof(struct cvmx_bootmem_named_block_desc));
200 /*
201 * Mark all memory (except low 0x100000 bytes) as free.
202 * It is the same thing that bootloader does.
203 */
204 kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL,
205 0x100000);
206 /*
207 * Allocate all segments to avoid their corruption during boot.
208 */
209 for (i = 0; i < kimage_ptr->nr_segments; i++)
210 cvmx_bootmem_alloc_address(
211 kimage_ptr->segment[i].memsz + 2*PAGE_SIZE,
212 kimage_ptr->segment[i].mem - PAGE_SIZE,
213 PAGE_SIZE);
214 } else {
215 /*
216 * Do not mark all memory as free. Free only named sections
217 * leaving the rest of memory unchanged.
218 */
219 struct cvmx_bootmem_named_block_desc *ptr =
220 (struct cvmx_bootmem_named_block_desc *)
221 named_block_array_ptr;
222
223 for (i = 0; i < bootmem_desc->named_block_num_blocks; i++)
224 if (ptr[i].size)
225 cvmx_bootmem_free_named(ptr[i].name);
226 }
227 kexec_args[2] = 1UL; /* running on octeon_main_processor */
228 kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
229 #ifdef CONFIG_SMP
230 secondary_kexec_args[2] = 0UL; /* running on secondary cpu */
231 secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
232 #endif
233 }
234
octeon_shutdown(void)235 static void octeon_shutdown(void)
236 {
237 octeon_generic_shutdown();
238 #ifdef CONFIG_SMP
239 smp_call_function(octeon_kexec_smp_down, NULL, 0);
240 smp_wmb();
241 while (num_online_cpus() > 1) {
242 cpu_relax();
243 mdelay(1);
244 }
245 #endif
246 }
247
octeon_crash_shutdown(struct pt_regs * regs)248 static void octeon_crash_shutdown(struct pt_regs *regs)
249 {
250 octeon_generic_shutdown();
251 default_machine_crash_shutdown(regs);
252 }
253
254 #ifdef CONFIG_SMP
octeon_crash_smp_send_stop(void)255 void octeon_crash_smp_send_stop(void)
256 {
257 int cpu;
258
259 /* disable watchdogs */
260 for_each_online_cpu(cpu)
261 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
262 }
263 #endif
264
265 #endif /* CONFIG_KEXEC */
266
267 #ifdef CONFIG_CAVIUM_RESERVE32
268 uint64_t octeon_reserve32_memory;
269 EXPORT_SYMBOL(octeon_reserve32_memory);
270 #endif
271
272 #ifdef CONFIG_KEXEC
273 /* crashkernel cmdline parameter is parsed _after_ memory setup
274 * we also parse it here (workaround for EHB5200) */
275 static uint64_t crashk_size, crashk_base;
276 #endif
277
278 static int octeon_uart;
279
280 extern asmlinkage void handle_int(void);
281
282 /**
283 * Return non zero if we are currently running in the Octeon simulator
284 *
285 * Returns
286 */
octeon_is_simulation(void)287 int octeon_is_simulation(void)
288 {
289 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM;
290 }
291 EXPORT_SYMBOL(octeon_is_simulation);
292
293 /**
294 * Return true if Octeon is in PCI Host mode. This means
295 * Linux can control the PCI bus.
296 *
297 * Returns Non zero if Octeon in host mode.
298 */
octeon_is_pci_host(void)299 int octeon_is_pci_host(void)
300 {
301 #ifdef CONFIG_PCI
302 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST;
303 #else
304 return 0;
305 #endif
306 }
307
308 /**
309 * Get the clock rate of Octeon
310 *
311 * Returns Clock rate in HZ
312 */
octeon_get_clock_rate(void)313 uint64_t octeon_get_clock_rate(void)
314 {
315 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
316
317 return sysinfo->cpu_clock_hz;
318 }
319 EXPORT_SYMBOL(octeon_get_clock_rate);
320
321 static u64 octeon_io_clock_rate;
322
octeon_get_io_clock_rate(void)323 u64 octeon_get_io_clock_rate(void)
324 {
325 return octeon_io_clock_rate;
326 }
327 EXPORT_SYMBOL(octeon_get_io_clock_rate);
328
329
330 /**
331 * Write to the LCD display connected to the bootbus. This display
332 * exists on most Cavium evaluation boards. If it doesn't exist, then
333 * this function doesn't do anything.
334 *
335 * @s: String to write
336 */
octeon_write_lcd(const char * s)337 void octeon_write_lcd(const char *s)
338 {
339 if (octeon_bootinfo->led_display_base_addr) {
340 void __iomem *lcd_address =
341 ioremap_nocache(octeon_bootinfo->led_display_base_addr,
342 8);
343 int i;
344 for (i = 0; i < 8; i++, s++) {
345 if (*s)
346 iowrite8(*s, lcd_address + i);
347 else
348 iowrite8(' ', lcd_address + i);
349 }
350 iounmap(lcd_address);
351 }
352 }
353
354 /**
355 * Return the console uart passed by the bootloader
356 *
357 * Returns uart (0 or 1)
358 */
octeon_get_boot_uart(void)359 int octeon_get_boot_uart(void)
360 {
361 int uart;
362 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
363 uart = 1;
364 #else
365 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
366 1 : 0;
367 #endif
368 return uart;
369 }
370
371 /**
372 * Get the coremask Linux was booted on.
373 *
374 * Returns Core mask
375 */
octeon_get_boot_coremask(void)376 int octeon_get_boot_coremask(void)
377 {
378 return octeon_boot_desc_ptr->core_mask;
379 }
380
381 /**
382 * Check the hardware BIST results for a CPU
383 */
octeon_check_cpu_bist(void)384 void octeon_check_cpu_bist(void)
385 {
386 const int coreid = cvmx_get_core_num();
387 unsigned long long mask;
388 unsigned long long bist_val;
389
390 /* Check BIST results for COP0 registers */
391 mask = 0x1f00000000ull;
392 bist_val = read_octeon_c0_icacheerr();
393 if (bist_val & mask)
394 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
395 coreid, bist_val);
396
397 bist_val = read_octeon_c0_dcacheerr();
398 if (bist_val & 1)
399 pr_err("Core%d L1 Dcache parity error: "
400 "CacheErr(dcache) = 0x%llx\n",
401 coreid, bist_val);
402
403 mask = 0xfc00000000000000ull;
404 bist_val = read_c0_cvmmemctl();
405 if (bist_val & mask)
406 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
407 coreid, bist_val);
408
409 write_octeon_c0_dcacheerr(0);
410 }
411
412 /**
413 * Reboot Octeon
414 *
415 * @command: Command to pass to the bootloader. Currently ignored.
416 */
octeon_restart(char * command)417 static void octeon_restart(char *command)
418 {
419 /* Disable all watchdogs before soft reset. They don't get cleared */
420 #ifdef CONFIG_SMP
421 int cpu;
422 for_each_online_cpu(cpu)
423 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
424 #else
425 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
426 #endif
427
428 mb();
429 while (1)
430 if (OCTEON_IS_OCTEON3())
431 cvmx_write_csr(CVMX_RST_SOFT_RST, 1);
432 else
433 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
434 }
435
436
437 /**
438 * Permanently stop a core.
439 *
440 * @arg: Ignored.
441 */
octeon_kill_core(void * arg)442 static void octeon_kill_core(void *arg)
443 {
444 if (octeon_is_simulation())
445 /* A break instruction causes the simulator stop a core */
446 asm volatile ("break" ::: "memory");
447
448 local_irq_disable();
449 /* Disable watchdog on this core. */
450 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
451 /* Spin in a low power mode. */
452 while (true)
453 asm volatile ("wait" ::: "memory");
454 }
455
456
457 /**
458 * Halt the system
459 */
octeon_halt(void)460 static void octeon_halt(void)
461 {
462 smp_call_function(octeon_kill_core, NULL, 0);
463
464 switch (octeon_bootinfo->board_type) {
465 case CVMX_BOARD_TYPE_NAO38:
466 /* Driving a 1 to GPIO 12 shuts off this board */
467 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
468 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000);
469 break;
470 default:
471 octeon_write_lcd("PowerOff");
472 break;
473 }
474
475 octeon_kill_core(NULL);
476 }
477
478 static char __read_mostly octeon_system_type[80];
479
init_octeon_system_type(void)480 static int __init init_octeon_system_type(void)
481 {
482 snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)",
483 cvmx_board_type_to_string(octeon_bootinfo->board_type),
484 octeon_model_get_string(read_c0_prid()));
485
486 return 0;
487 }
488 early_initcall(init_octeon_system_type);
489
490 /**
491 * Return a string representing the system type
492 *
493 * Returns
494 */
octeon_board_type_string(void)495 const char *octeon_board_type_string(void)
496 {
497 return octeon_system_type;
498 }
499
500 const char *get_system_type(void)
501 __attribute__ ((alias("octeon_board_type_string")));
502
octeon_user_io_init(void)503 void octeon_user_io_init(void)
504 {
505 union octeon_cvmemctl cvmmemctl;
506 union cvmx_iob_fau_timeout fau_timeout;
507 union cvmx_pow_nw_tim nm_tim;
508
509 /* Get the current settings for CP0_CVMMEMCTL_REG */
510 cvmmemctl.u64 = read_c0_cvmmemctl();
511 /* R/W If set, marked write-buffer entries time out the same
512 * as as other entries; if clear, marked write-buffer entries
513 * use the maximum timeout. */
514 cvmmemctl.s.dismarkwblongto = 1;
515 /* R/W If set, a merged store does not clear the write-buffer
516 * entry timeout state. */
517 cvmmemctl.s.dismrgclrwbto = 0;
518 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM
519 * word location for an IOBDMA. The other 8 bits come from the
520 * SCRADDR field of the IOBDMA. */
521 cvmmemctl.s.iobdmascrmsb = 0;
522 /* R/W If set, SYNCWS and SYNCS only order marked stores; if
523 * clear, SYNCWS and SYNCS only order unmarked
524 * stores. SYNCWSMARKED has no effect when DISSYNCWS is
525 * set. */
526 cvmmemctl.s.syncwsmarked = 0;
527 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */
528 cvmmemctl.s.dissyncws = 0;
529 /* R/W If set, no stall happens on write buffer full. */
530 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
531 cvmmemctl.s.diswbfst = 1;
532 else
533 cvmmemctl.s.diswbfst = 0;
534 /* R/W If set (and SX set), supervisor-level loads/stores can
535 * use XKPHYS addresses with <48>==0 */
536 cvmmemctl.s.xkmemenas = 0;
537
538 /* R/W If set (and UX set), user-level loads/stores can use
539 * XKPHYS addresses with VA<48>==0 */
540 cvmmemctl.s.xkmemenau = 0;
541
542 /* R/W If set (and SX set), supervisor-level loads/stores can
543 * use XKPHYS addresses with VA<48>==1 */
544 cvmmemctl.s.xkioenas = 0;
545
546 /* R/W If set (and UX set), user-level loads/stores can use
547 * XKPHYS addresses with VA<48>==1 */
548 cvmmemctl.s.xkioenau = 0;
549
550 /* R/W If set, all stores act as SYNCW (NOMERGE must be set
551 * when this is set) RW, reset to 0. */
552 cvmmemctl.s.allsyncw = 0;
553
554 /* R/W If set, no stores merge, and all stores reach the
555 * coherent bus in order. */
556 cvmmemctl.s.nomerge = 0;
557 /* R/W Selects the bit in the counter used for DID time-outs 0
558 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is
559 * between 1x and 2x this interval. For example, with
560 * DIDTTO=3, expiration interval is between 16K and 32K. */
561 cvmmemctl.s.didtto = 0;
562 /* R/W If set, the (mem) CSR clock never turns off. */
563 cvmmemctl.s.csrckalwys = 0;
564 /* R/W If set, mclk never turns off. */
565 cvmmemctl.s.mclkalwys = 0;
566 /* R/W Selects the bit in the counter used for write buffer
567 * flush time-outs (WBFLT+11) is the bit position in an
568 * internal counter used to determine expiration. The write
569 * buffer expires between 1x and 2x this interval. For
570 * example, with WBFLT = 0, a write buffer expires between 2K
571 * and 4K cycles after the write buffer entry is allocated. */
572 cvmmemctl.s.wbfltime = 0;
573 /* R/W If set, do not put Istream in the L2 cache. */
574 cvmmemctl.s.istrnol2 = 0;
575
576 /*
577 * R/W The write buffer threshold. As per erratum Core-14752
578 * for CN63XX, a sc/scd might fail if the write buffer is
579 * full. Lowering WBTHRESH greatly lowers the chances of the
580 * write buffer ever being full and triggering the erratum.
581 */
582 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
583 cvmmemctl.s.wbthresh = 4;
584 else
585 cvmmemctl.s.wbthresh = 10;
586
587 /* R/W If set, CVMSEG is available for loads/stores in
588 * kernel/debug mode. */
589 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
590 cvmmemctl.s.cvmsegenak = 1;
591 #else
592 cvmmemctl.s.cvmsegenak = 0;
593 #endif
594 /* R/W If set, CVMSEG is available for loads/stores in
595 * supervisor mode. */
596 cvmmemctl.s.cvmsegenas = 0;
597 /* R/W If set, CVMSEG is available for loads/stores in user
598 * mode. */
599 cvmmemctl.s.cvmsegenau = 0;
600
601 write_c0_cvmmemctl(cvmmemctl.u64);
602
603 /* Setup of CVMSEG is done in kernel-entry-init.h */
604 if (smp_processor_id() == 0)
605 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
606 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
607 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
608
609 /* Set a default for the hardware timeouts */
610 fau_timeout.u64 = 0;
611 fau_timeout.s.tout_val = 0xfff;
612 /* Disable tagwait FAU timeout */
613 fau_timeout.s.tout_enb = 0;
614 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64);
615
616 nm_tim.u64 = 0;
617 /* 4096 cycles */
618 nm_tim.s.nw_tim = 3;
619 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64);
620
621 write_octeon_c0_icacheerr(0);
622 write_c0_derraddr1(0);
623 }
624
625 /**
626 * Early entry point for arch setup
627 */
prom_init(void)628 void __init prom_init(void)
629 {
630 struct cvmx_sysinfo *sysinfo;
631 const char *arg;
632 char *p;
633 int i;
634 u64 t;
635 int argc;
636 #ifdef CONFIG_CAVIUM_RESERVE32
637 int64_t addr = -1;
638 #endif
639 /*
640 * The bootloader passes a pointer to the boot descriptor in
641 * $a3, this is available as fw_arg3.
642 */
643 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
644 octeon_bootinfo =
645 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
646 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
647
648 sysinfo = cvmx_sysinfo_get();
649 memset(sysinfo, 0, sizeof(*sysinfo));
650 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
651 sysinfo->phy_mem_desc_ptr =
652 cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
653 sysinfo->core_mask = octeon_bootinfo->core_mask;
654 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
655 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
656 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
657 sysinfo->board_type = octeon_bootinfo->board_type;
658 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
659 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
660 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
661 sizeof(sysinfo->mac_addr_base));
662 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
663 memcpy(sysinfo->board_serial_number,
664 octeon_bootinfo->board_serial_number,
665 sizeof(sysinfo->board_serial_number));
666 sysinfo->compact_flash_common_base_addr =
667 octeon_bootinfo->compact_flash_common_base_addr;
668 sysinfo->compact_flash_attribute_base_addr =
669 octeon_bootinfo->compact_flash_attribute_base_addr;
670 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
671 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
672 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
673
674 if (OCTEON_IS_OCTEON2()) {
675 /* I/O clock runs at a different rate than the CPU. */
676 union cvmx_mio_rst_boot rst_boot;
677 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
678 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
679 } else if (OCTEON_IS_OCTEON3()) {
680 /* I/O clock runs at a different rate than the CPU. */
681 union cvmx_rst_boot rst_boot;
682 rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);
683 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
684 } else {
685 octeon_io_clock_rate = sysinfo->cpu_clock_hz;
686 }
687
688 t = read_c0_cvmctl();
689 if ((t & (1ull << 27)) == 0) {
690 /*
691 * Setup the multiplier save/restore code if
692 * CvmCtl[NOMUL] clear.
693 */
694 void *save;
695 void *save_end;
696 void *restore;
697 void *restore_end;
698 int save_len;
699 int restore_len;
700 int save_max = (char *)octeon_mult_save_end -
701 (char *)octeon_mult_save;
702 int restore_max = (char *)octeon_mult_restore_end -
703 (char *)octeon_mult_restore;
704 if (current_cpu_data.cputype == CPU_CAVIUM_OCTEON3) {
705 save = octeon_mult_save3;
706 save_end = octeon_mult_save3_end;
707 restore = octeon_mult_restore3;
708 restore_end = octeon_mult_restore3_end;
709 } else {
710 save = octeon_mult_save2;
711 save_end = octeon_mult_save2_end;
712 restore = octeon_mult_restore2;
713 restore_end = octeon_mult_restore2_end;
714 }
715 save_len = (char *)save_end - (char *)save;
716 restore_len = (char *)restore_end - (char *)restore;
717 if (!WARN_ON(save_len > save_max ||
718 restore_len > restore_max)) {
719 memcpy(octeon_mult_save, save, save_len);
720 memcpy(octeon_mult_restore, restore, restore_len);
721 }
722 }
723
724 /*
725 * Only enable the LED controller if we're running on a CN38XX, CN58XX,
726 * or CN56XX. The CN30XX and CN31XX don't have an LED controller.
727 */
728 if (!octeon_is_simulation() &&
729 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) {
730 cvmx_write_csr(CVMX_LED_EN, 0);
731 cvmx_write_csr(CVMX_LED_PRT, 0);
732 cvmx_write_csr(CVMX_LED_DBG, 0);
733 cvmx_write_csr(CVMX_LED_PRT_FMT, 0);
734 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
735 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
736 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
737 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
738 cvmx_write_csr(CVMX_LED_EN, 1);
739 }
740 #ifdef CONFIG_CAVIUM_RESERVE32
741 /*
742 * We need to temporarily allocate all memory in the reserve32
743 * region. This makes sure the kernel doesn't allocate this
744 * memory when it is getting memory from the
745 * bootloader. Later, after the memory allocations are
746 * complete, the reserve32 will be freed.
747 *
748 * Allocate memory for RESERVED32 aligned on 2MB boundary. This
749 * is in case we later use hugetlb entries with it.
750 */
751 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
752 0, 0, 2 << 20,
753 "CAVIUM_RESERVE32", 0);
754 if (addr < 0)
755 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
756 else
757 octeon_reserve32_memory = addr;
758 #endif
759
760 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
761 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
762 pr_info("Skipping L2 locking due to reduced L2 cache size\n");
763 } else {
764 uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000;
765 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
766 /* TLB refill */
767 cvmx_l2c_lock_mem_region(ebase, 0x100);
768 #endif
769 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
770 /* General exception */
771 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80);
772 #endif
773 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
774 /* Interrupt handler */
775 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80);
776 #endif
777 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
778 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100);
779 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80);
780 #endif
781 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
782 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480);
783 #endif
784 }
785 #endif
786
787 octeon_check_cpu_bist();
788
789 octeon_uart = octeon_get_boot_uart();
790
791 #ifdef CONFIG_SMP
792 octeon_write_lcd("LinuxSMP");
793 #else
794 octeon_write_lcd("Linux");
795 #endif
796
797 octeon_setup_delays();
798
799 /*
800 * BIST should always be enabled when doing a soft reset. L2
801 * Cache locking for instance is not cleared unless BIST is
802 * enabled. Unfortunately due to a chip errata G-200 for
803 * Cn38XX and CN31XX, BIST msut be disabled on these parts.
804 */
805 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
806 OCTEON_IS_MODEL(OCTEON_CN31XX))
807 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);
808 else
809 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);
810
811 /* Default to 64MB in the simulator to speed things up */
812 if (octeon_is_simulation())
813 MAX_MEMORY = 64ull << 20;
814
815 arg = strstr(arcs_cmdline, "mem=");
816 if (arg) {
817 MAX_MEMORY = memparse(arg + 4, &p);
818 if (MAX_MEMORY == 0)
819 MAX_MEMORY = 32ull << 30;
820 if (*p == '@')
821 RESERVE_LOW_MEM = memparse(p + 1, &p);
822 }
823
824 arcs_cmdline[0] = 0;
825 argc = octeon_boot_desc_ptr->argc;
826 for (i = 0; i < argc; i++) {
827 const char *arg =
828 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
829 if ((strncmp(arg, "MEM=", 4) == 0) ||
830 (strncmp(arg, "mem=", 4) == 0)) {
831 MAX_MEMORY = memparse(arg + 4, &p);
832 if (MAX_MEMORY == 0)
833 MAX_MEMORY = 32ull << 30;
834 if (*p == '@')
835 RESERVE_LOW_MEM = memparse(p + 1, &p);
836 #ifdef CONFIG_KEXEC
837 } else if (strncmp(arg, "crashkernel=", 12) == 0) {
838 crashk_size = memparse(arg+12, &p);
839 if (*p == '@')
840 crashk_base = memparse(p+1, &p);
841 strcat(arcs_cmdline, " ");
842 strcat(arcs_cmdline, arg);
843 /*
844 * To do: switch parsing to new style, something like:
845 * parse_crashkernel(arg, sysinfo->system_dram_size,
846 * &crashk_size, &crashk_base);
847 */
848 #endif
849 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
850 sizeof(arcs_cmdline) - 1) {
851 strcat(arcs_cmdline, " ");
852 strcat(arcs_cmdline, arg);
853 }
854 }
855
856 if (strstr(arcs_cmdline, "console=") == NULL) {
857 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
858 strcat(arcs_cmdline, " console=ttyS0,115200");
859 #else
860 if (octeon_uart == 1)
861 strcat(arcs_cmdline, " console=ttyS1,115200");
862 else
863 strcat(arcs_cmdline, " console=ttyS0,115200");
864 #endif
865 }
866
867 mips_hpt_frequency = octeon_get_clock_rate();
868
869 octeon_init_cvmcount();
870
871 _machine_restart = octeon_restart;
872 _machine_halt = octeon_halt;
873
874 #ifdef CONFIG_KEXEC
875 _machine_kexec_shutdown = octeon_shutdown;
876 _machine_crash_shutdown = octeon_crash_shutdown;
877 _machine_kexec_prepare = octeon_kexec_prepare;
878 #ifdef CONFIG_SMP
879 _crash_smp_send_stop = octeon_crash_smp_send_stop;
880 #endif
881 #endif
882
883 octeon_user_io_init();
884 register_smp_ops(&octeon_smp_ops);
885 }
886
887 /* Exclude a single page from the regions obtained in plat_mem_setup. */
888 #ifndef CONFIG_CRASH_DUMP
memory_exclude_page(u64 addr,u64 * mem,u64 * size)889 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
890 {
891 if (addr > *mem && addr < *mem + *size) {
892 u64 inc = addr - *mem;
893 add_memory_region(*mem, inc, BOOT_MEM_RAM);
894 *mem += inc;
895 *size -= inc;
896 }
897
898 if (addr == *mem && *size > PAGE_SIZE) {
899 *mem += PAGE_SIZE;
900 *size -= PAGE_SIZE;
901 }
902 }
903 #endif /* CONFIG_CRASH_DUMP */
904
plat_mem_setup(void)905 void __init plat_mem_setup(void)
906 {
907 uint64_t mem_alloc_size;
908 uint64_t total;
909 uint64_t crashk_end;
910 #ifndef CONFIG_CRASH_DUMP
911 int64_t memory;
912 uint64_t kernel_start;
913 uint64_t kernel_size;
914 #endif
915
916 total = 0;
917 crashk_end = 0;
918
919 /*
920 * The Mips memory init uses the first memory location for
921 * some memory vectors. When SPARSEMEM is in use, it doesn't
922 * verify that the size is big enough for the final
923 * vectors. Making the smallest chuck 4MB seems to be enough
924 * to consistently work.
925 */
926 mem_alloc_size = 4 << 20;
927 if (mem_alloc_size > MAX_MEMORY)
928 mem_alloc_size = MAX_MEMORY;
929
930 /* Crashkernel ignores bootmem list. It relies on mem=X@Y option */
931 #ifdef CONFIG_CRASH_DUMP
932 add_memory_region(RESERVE_LOW_MEM, MAX_MEMORY, BOOT_MEM_RAM);
933 total += MAX_MEMORY;
934 #else
935 #ifdef CONFIG_KEXEC
936 if (crashk_size > 0) {
937 add_memory_region(crashk_base, crashk_size, BOOT_MEM_RAM);
938 crashk_end = crashk_base + crashk_size;
939 }
940 #endif
941 /*
942 * When allocating memory, we want incrementing addresses from
943 * bootmem_alloc so the code in add_memory_region can merge
944 * regions next to each other.
945 */
946 cvmx_bootmem_lock();
947 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX)
948 && (total < MAX_MEMORY)) {
949 memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
950 __pa_symbol(&_end), -1,
951 0x100000,
952 CVMX_BOOTMEM_FLAG_NO_LOCKING);
953 if (memory >= 0) {
954 u64 size = mem_alloc_size;
955 #ifdef CONFIG_KEXEC
956 uint64_t end;
957 #endif
958
959 /*
960 * exclude a page at the beginning and end of
961 * the 256MB PCIe 'hole' so the kernel will not
962 * try to allocate multi-page buffers that
963 * span the discontinuity.
964 */
965 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
966 &memory, &size);
967 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
968 CVMX_PCIE_BAR1_PHYS_SIZE,
969 &memory, &size);
970 #ifdef CONFIG_KEXEC
971 end = memory + mem_alloc_size;
972
973 /*
974 * This function automatically merges address regions
975 * next to each other if they are received in
976 * incrementing order
977 */
978 if (memory < crashk_base && end > crashk_end) {
979 /* region is fully in */
980 add_memory_region(memory,
981 crashk_base - memory,
982 BOOT_MEM_RAM);
983 total += crashk_base - memory;
984 add_memory_region(crashk_end,
985 end - crashk_end,
986 BOOT_MEM_RAM);
987 total += end - crashk_end;
988 continue;
989 }
990
991 if (memory >= crashk_base && end <= crashk_end)
992 /*
993 * Entire memory region is within the new
994 * kernel's memory, ignore it.
995 */
996 continue;
997
998 if (memory > crashk_base && memory < crashk_end &&
999 end > crashk_end) {
1000 /*
1001 * Overlap with the beginning of the region,
1002 * reserve the beginning.
1003 */
1004 mem_alloc_size -= crashk_end - memory;
1005 memory = crashk_end;
1006 } else if (memory < crashk_base && end > crashk_base &&
1007 end < crashk_end)
1008 /*
1009 * Overlap with the beginning of the region,
1010 * chop of end.
1011 */
1012 mem_alloc_size -= end - crashk_base;
1013 #endif
1014 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
1015 total += mem_alloc_size;
1016 /* Recovering mem_alloc_size */
1017 mem_alloc_size = 4 << 20;
1018 } else {
1019 break;
1020 }
1021 }
1022 cvmx_bootmem_unlock();
1023 /* Add the memory region for the kernel. */
1024 kernel_start = (unsigned long) _text;
1025 kernel_size = _end - _text;
1026
1027 /* Adjust for physical offset. */
1028 kernel_start &= ~0xffffffff80000000ULL;
1029 add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM);
1030 #endif /* CONFIG_CRASH_DUMP */
1031
1032 #ifdef CONFIG_CAVIUM_RESERVE32
1033 /*
1034 * Now that we've allocated the kernel memory it is safe to
1035 * free the reserved region. We free it here so that builtin
1036 * drivers can use the memory.
1037 */
1038 if (octeon_reserve32_memory)
1039 cvmx_bootmem_free_named("CAVIUM_RESERVE32");
1040 #endif /* CONFIG_CAVIUM_RESERVE32 */
1041
1042 if (total == 0)
1043 panic("Unable to allocate memory from "
1044 "cvmx_bootmem_phy_alloc");
1045 }
1046
1047 /*
1048 * Emit one character to the boot UART. Exported for use by the
1049 * watchdog timer.
1050 */
prom_putchar(char c)1051 int prom_putchar(char c)
1052 {
1053 uint64_t lsrval;
1054
1055 /* Spin until there is room */
1056 do {
1057 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart));
1058 } while ((lsrval & 0x20) == 0);
1059
1060 /* Write the byte */
1061 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
1062 return 1;
1063 }
1064 EXPORT_SYMBOL(prom_putchar);
1065
prom_free_prom_memory(void)1066 void __init prom_free_prom_memory(void)
1067 {
1068 if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) {
1069 /* Check for presence of Core-14449 fix. */
1070 u32 insn;
1071 u32 *foo;
1072
1073 foo = &insn;
1074
1075 asm volatile("# before" : : : "memory");
1076 prefetch(foo);
1077 asm volatile(
1078 ".set push\n\t"
1079 ".set noreorder\n\t"
1080 "bal 1f\n\t"
1081 "nop\n"
1082 "1:\tlw %0,-12($31)\n\t"
1083 ".set pop\n\t"
1084 : "=r" (insn) : : "$31", "memory");
1085
1086 if ((insn >> 26) != 0x33)
1087 panic("No PREF instruction at Core-14449 probe point.");
1088
1089 if (((insn >> 16) & 0x1f) != 28)
1090 panic("OCTEON II DCache prefetch workaround not in place (%04x).\n"
1091 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).",
1092 insn);
1093 }
1094 }
1095
1096 int octeon_prune_device_tree(void);
1097
1098 extern const char __appended_dtb;
1099 extern const char __dtb_octeon_3xxx_begin;
1100 extern const char __dtb_octeon_68xx_begin;
device_tree_init(void)1101 void __init device_tree_init(void)
1102 {
1103 const void *fdt;
1104 bool do_prune;
1105
1106 #ifdef CONFIG_MIPS_ELF_APPENDED_DTB
1107 if (!fdt_check_header(&__appended_dtb)) {
1108 fdt = &__appended_dtb;
1109 do_prune = false;
1110 pr_info("Using appended Device Tree.\n");
1111 } else
1112 #endif
1113 if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) {
1114 fdt = phys_to_virt(octeon_bootinfo->fdt_addr);
1115 if (fdt_check_header(fdt))
1116 panic("Corrupt Device Tree passed to kernel.");
1117 do_prune = false;
1118 pr_info("Using passed Device Tree.\n");
1119 } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
1120 fdt = &__dtb_octeon_68xx_begin;
1121 do_prune = true;
1122 } else {
1123 fdt = &__dtb_octeon_3xxx_begin;
1124 do_prune = true;
1125 }
1126
1127 initial_boot_params = (void *)fdt;
1128
1129 if (do_prune) {
1130 octeon_prune_device_tree();
1131 pr_info("Using internal Device Tree.\n");
1132 }
1133 unflatten_and_copy_device_tree();
1134 }
1135
1136 static int __initdata disable_octeon_edac_p;
1137
disable_octeon_edac(char * str)1138 static int __init disable_octeon_edac(char *str)
1139 {
1140 disable_octeon_edac_p = 1;
1141 return 0;
1142 }
1143 early_param("disable_octeon_edac", disable_octeon_edac);
1144
1145 static char *edac_device_names[] = {
1146 "octeon_l2c_edac",
1147 "octeon_pc_edac",
1148 };
1149
edac_devinit(void)1150 static int __init edac_devinit(void)
1151 {
1152 struct platform_device *dev;
1153 int i, err = 0;
1154 int num_lmc;
1155 char *name;
1156
1157 if (disable_octeon_edac_p)
1158 return 0;
1159
1160 for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) {
1161 name = edac_device_names[i];
1162 dev = platform_device_register_simple(name, -1, NULL, 0);
1163 if (IS_ERR(dev)) {
1164 pr_err("Registration of %s failed!\n", name);
1165 err = PTR_ERR(dev);
1166 }
1167 }
1168
1169 num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 :
1170 (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1);
1171 for (i = 0; i < num_lmc; i++) {
1172 dev = platform_device_register_simple("octeon_lmc_edac",
1173 i, NULL, 0);
1174 if (IS_ERR(dev)) {
1175 pr_err("Registration of octeon_lmc_edac %d failed!\n", i);
1176 err = PTR_ERR(dev);
1177 }
1178 }
1179
1180 return err;
1181 }
1182 device_initcall(edac_devinit);
1183
1184 static void __initdata *octeon_dummy_iospace;
1185
octeon_no_pci_init(void)1186 static int __init octeon_no_pci_init(void)
1187 {
1188 /*
1189 * Initially assume there is no PCI. The PCI/PCIe platform code will
1190 * later re-initialize these to correct values if they are present.
1191 */
1192 octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT);
1193 set_io_port_base((unsigned long)octeon_dummy_iospace);
1194 ioport_resource.start = MAX_RESOURCE;
1195 ioport_resource.end = 0;
1196 return 0;
1197 }
1198 core_initcall(octeon_no_pci_init);
1199
octeon_no_pci_release(void)1200 static int __init octeon_no_pci_release(void)
1201 {
1202 /*
1203 * Release the allocated memory if a real IO space is there.
1204 */
1205 if ((unsigned long)octeon_dummy_iospace != mips_io_port_base)
1206 vfree(octeon_dummy_iospace);
1207 return 0;
1208 }
1209 late_initcall(octeon_no_pci_release);
1210