1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2011 Cavium Networks
7 * Copyright (C) 2008 Wind River Systems
8 */
9
10 #include <linux/delay.h>
11 #include <linux/init.h>
12 #include <linux/irq.h>
13 #include <linux/i2c.h>
14 #include <linux/usb.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/slab.h>
19 #include <linux/platform_device.h>
20 #include <linux/of_platform.h>
21 #include <linux/of_fdt.h>
22 #include <linux/libfdt.h>
23 #include <linux/usb/ehci_pdriver.h>
24 #include <linux/usb/ohci_pdriver.h>
25
26 #include <asm/octeon/octeon.h>
27 #include <asm/octeon/cvmx-rnm-defs.h>
28 #include <asm/octeon/cvmx-helper.h>
29 #include <asm/octeon/cvmx-helper-board.h>
30 #include <asm/octeon/cvmx-uctlx-defs.h>
31
32 /* Octeon Random Number Generator. */
octeon_rng_device_init(void)33 static int __init octeon_rng_device_init(void)
34 {
35 struct platform_device *pd;
36 int ret = 0;
37
38 struct resource rng_resources[] = {
39 {
40 .flags = IORESOURCE_MEM,
41 .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
42 .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
43 }, {
44 .flags = IORESOURCE_MEM,
45 .start = cvmx_build_io_address(8, 0),
46 .end = cvmx_build_io_address(8, 0) + 0x7
47 }
48 };
49
50 pd = platform_device_alloc("octeon_rng", -1);
51 if (!pd) {
52 ret = -ENOMEM;
53 goto out;
54 }
55
56 ret = platform_device_add_resources(pd, rng_resources,
57 ARRAY_SIZE(rng_resources));
58 if (ret)
59 goto fail;
60
61 ret = platform_device_add(pd);
62 if (ret)
63 goto fail;
64
65 return ret;
66 fail:
67 platform_device_put(pd);
68
69 out:
70 return ret;
71 }
72 device_initcall(octeon_rng_device_init);
73
74 #ifdef CONFIG_USB
75
76 static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
77
78 static int octeon2_usb_clock_start_cnt;
79
octeon2_usb_clocks_start(struct device * dev)80 static void octeon2_usb_clocks_start(struct device *dev)
81 {
82 u64 div;
83 union cvmx_uctlx_if_ena if_ena;
84 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
85 union cvmx_uctlx_uphy_ctl_status uphy_ctl_status;
86 union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
87 int i;
88 unsigned long io_clk_64_to_ns;
89 u32 clock_rate = 12000000;
90 bool is_crystal_clock = false;
91
92
93 mutex_lock(&octeon2_usb_clocks_mutex);
94
95 octeon2_usb_clock_start_cnt++;
96 if (octeon2_usb_clock_start_cnt != 1)
97 goto exit;
98
99 io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
100
101 if (dev->of_node) {
102 struct device_node *uctl_node;
103 const char *clock_type;
104
105 uctl_node = of_get_parent(dev->of_node);
106 if (!uctl_node) {
107 dev_err(dev, "No UCTL device node\n");
108 goto exit;
109 }
110 i = of_property_read_u32(uctl_node,
111 "refclk-frequency", &clock_rate);
112 if (i) {
113 dev_err(dev, "No UCTL \"refclk-frequency\"\n");
114 goto exit;
115 }
116 i = of_property_read_string(uctl_node,
117 "refclk-type", &clock_type);
118
119 if (!i && strcmp("crystal", clock_type) == 0)
120 is_crystal_clock = true;
121 }
122
123 /*
124 * Step 1: Wait for voltages stable. That surely happened
125 * before starting the kernel.
126 *
127 * Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
128 */
129 if_ena.u64 = 0;
130 if_ena.s.en = 1;
131 cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
132
133 /* Step 3: Configure the reference clock, PHY, and HCLK */
134 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
135
136 /*
137 * If the UCTL looks like it has already been started, skip
138 * the initialization, otherwise bus errors are obtained.
139 */
140 if (clk_rst_ctl.s.hrst)
141 goto end_clock;
142 /* 3a */
143 clk_rst_ctl.s.p_por = 1;
144 clk_rst_ctl.s.hrst = 0;
145 clk_rst_ctl.s.p_prst = 0;
146 clk_rst_ctl.s.h_clkdiv_rst = 0;
147 clk_rst_ctl.s.o_clkdiv_rst = 0;
148 clk_rst_ctl.s.h_clkdiv_en = 0;
149 clk_rst_ctl.s.o_clkdiv_en = 0;
150 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
151
152 /* 3b */
153 clk_rst_ctl.s.p_refclk_sel = is_crystal_clock ? 0 : 1;
154 switch (clock_rate) {
155 default:
156 pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n",
157 clock_rate);
158 /* Fall through */
159 case 12000000:
160 clk_rst_ctl.s.p_refclk_div = 0;
161 break;
162 case 24000000:
163 clk_rst_ctl.s.p_refclk_div = 1;
164 break;
165 case 48000000:
166 clk_rst_ctl.s.p_refclk_div = 2;
167 break;
168 }
169 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
170
171 /* 3c */
172 div = octeon_get_io_clock_rate() / 130000000ull;
173
174 switch (div) {
175 case 0:
176 div = 1;
177 break;
178 case 1:
179 case 2:
180 case 3:
181 case 4:
182 break;
183 case 5:
184 div = 4;
185 break;
186 case 6:
187 case 7:
188 div = 6;
189 break;
190 case 8:
191 case 9:
192 case 10:
193 case 11:
194 div = 8;
195 break;
196 default:
197 div = 12;
198 break;
199 }
200 clk_rst_ctl.s.h_div = div;
201 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
202 /* Read it back, */
203 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
204 clk_rst_ctl.s.h_clkdiv_en = 1;
205 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
206 /* 3d */
207 clk_rst_ctl.s.h_clkdiv_rst = 1;
208 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
209
210 /* 3e: delay 64 io clocks */
211 ndelay(io_clk_64_to_ns);
212
213 /*
214 * Step 4: Program the power-on reset field in the UCTL
215 * clock-reset-control register.
216 */
217 clk_rst_ctl.s.p_por = 0;
218 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
219
220 /* Step 5: Wait 1 ms for the PHY clock to start. */
221 mdelay(1);
222
223 /*
224 * Step 6: Program the reset input from automatic test
225 * equipment field in the UPHY CSR
226 */
227 uphy_ctl_status.u64 = cvmx_read_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0));
228 uphy_ctl_status.s.ate_reset = 1;
229 cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
230
231 /* Step 7: Wait for at least 10ns. */
232 ndelay(10);
233
234 /* Step 8: Clear the ATE_RESET field in the UPHY CSR. */
235 uphy_ctl_status.s.ate_reset = 0;
236 cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
237
238 /*
239 * Step 9: Wait for at least 20ns for UPHY to output PHY clock
240 * signals and OHCI_CLK48
241 */
242 ndelay(20);
243
244 /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
245 /* 10a */
246 clk_rst_ctl.s.o_clkdiv_rst = 1;
247 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
248
249 /* 10b */
250 clk_rst_ctl.s.o_clkdiv_en = 1;
251 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
252
253 /* 10c */
254 ndelay(io_clk_64_to_ns);
255
256 /*
257 * Step 11: Program the PHY reset field:
258 * UCTL0_CLK_RST_CTL[P_PRST] = 1
259 */
260 clk_rst_ctl.s.p_prst = 1;
261 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
262
263 /* Step 12: Wait 1 uS. */
264 udelay(1);
265
266 /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
267 clk_rst_ctl.s.hrst = 1;
268 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
269
270 end_clock:
271 /* Now we can set some other registers. */
272
273 for (i = 0; i <= 1; i++) {
274 port_ctl_status.u64 =
275 cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
276 /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */
277 port_ctl_status.s.txvreftune = 15;
278 port_ctl_status.s.txrisetune = 1;
279 port_ctl_status.s.txpreemphasistune = 1;
280 cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
281 port_ctl_status.u64);
282 }
283
284 /* Set uSOF cycle period to 60,000 bits. */
285 cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);
286 exit:
287 mutex_unlock(&octeon2_usb_clocks_mutex);
288 }
289
octeon2_usb_clocks_stop(void)290 static void octeon2_usb_clocks_stop(void)
291 {
292 mutex_lock(&octeon2_usb_clocks_mutex);
293 octeon2_usb_clock_start_cnt--;
294 mutex_unlock(&octeon2_usb_clocks_mutex);
295 }
296
octeon_ehci_power_on(struct platform_device * pdev)297 static int octeon_ehci_power_on(struct platform_device *pdev)
298 {
299 octeon2_usb_clocks_start(&pdev->dev);
300 return 0;
301 }
302
octeon_ehci_power_off(struct platform_device * pdev)303 static void octeon_ehci_power_off(struct platform_device *pdev)
304 {
305 octeon2_usb_clocks_stop();
306 }
307
308 static struct usb_ehci_pdata octeon_ehci_pdata = {
309 /* Octeon EHCI matches CPU endianness. */
310 #ifdef __BIG_ENDIAN
311 .big_endian_mmio = 1,
312 #endif
313 .dma_mask_64 = 1,
314 .power_on = octeon_ehci_power_on,
315 .power_off = octeon_ehci_power_off,
316 };
317
octeon_ehci_hw_start(struct device * dev)318 static void __init octeon_ehci_hw_start(struct device *dev)
319 {
320 union cvmx_uctlx_ehci_ctl ehci_ctl;
321
322 octeon2_usb_clocks_start(dev);
323
324 ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));
325 /* Use 64-bit addressing. */
326 ehci_ctl.s.ehci_64b_addr_en = 1;
327 ehci_ctl.s.l2c_addr_msb = 0;
328 #ifdef __BIG_ENDIAN
329 ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
330 ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
331 #else
332 ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
333 ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
334 ehci_ctl.s.inv_reg_a2 = 1;
335 #endif
336 cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
337
338 octeon2_usb_clocks_stop();
339 }
340
octeon_ehci_device_init(void)341 static int __init octeon_ehci_device_init(void)
342 {
343 struct platform_device *pd;
344 struct device_node *ehci_node;
345 int ret = 0;
346
347 ehci_node = of_find_node_by_name(NULL, "ehci");
348 if (!ehci_node)
349 return 0;
350
351 pd = of_find_device_by_node(ehci_node);
352 of_node_put(ehci_node);
353 if (!pd)
354 return 0;
355
356 pd->dev.platform_data = &octeon_ehci_pdata;
357 octeon_ehci_hw_start(&pd->dev);
358
359 return ret;
360 }
361 device_initcall(octeon_ehci_device_init);
362
octeon_ohci_power_on(struct platform_device * pdev)363 static int octeon_ohci_power_on(struct platform_device *pdev)
364 {
365 octeon2_usb_clocks_start(&pdev->dev);
366 return 0;
367 }
368
octeon_ohci_power_off(struct platform_device * pdev)369 static void octeon_ohci_power_off(struct platform_device *pdev)
370 {
371 octeon2_usb_clocks_stop();
372 }
373
374 static struct usb_ohci_pdata octeon_ohci_pdata = {
375 /* Octeon OHCI matches CPU endianness. */
376 #ifdef __BIG_ENDIAN
377 .big_endian_mmio = 1,
378 #endif
379 .power_on = octeon_ohci_power_on,
380 .power_off = octeon_ohci_power_off,
381 };
382
octeon_ohci_hw_start(struct device * dev)383 static void __init octeon_ohci_hw_start(struct device *dev)
384 {
385 union cvmx_uctlx_ohci_ctl ohci_ctl;
386
387 octeon2_usb_clocks_start(dev);
388
389 ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
390 ohci_ctl.s.l2c_addr_msb = 0;
391 #ifdef __BIG_ENDIAN
392 ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
393 ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
394 #else
395 ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
396 ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
397 ohci_ctl.s.inv_reg_a2 = 1;
398 #endif
399 cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
400
401 octeon2_usb_clocks_stop();
402 }
403
octeon_ohci_device_init(void)404 static int __init octeon_ohci_device_init(void)
405 {
406 struct platform_device *pd;
407 struct device_node *ohci_node;
408 int ret = 0;
409
410 ohci_node = of_find_node_by_name(NULL, "ohci");
411 if (!ohci_node)
412 return 0;
413
414 pd = of_find_device_by_node(ohci_node);
415 of_node_put(ohci_node);
416 if (!pd)
417 return 0;
418
419 pd->dev.platform_data = &octeon_ohci_pdata;
420 octeon_ohci_hw_start(&pd->dev);
421
422 return ret;
423 }
424 device_initcall(octeon_ohci_device_init);
425
426 #endif /* CONFIG_USB */
427
428
429 static struct of_device_id __initdata octeon_ids[] = {
430 { .compatible = "simple-bus", },
431 { .compatible = "cavium,octeon-6335-uctl", },
432 { .compatible = "cavium,octeon-5750-usbn", },
433 { .compatible = "cavium,octeon-3860-bootbus", },
434 { .compatible = "cavium,mdio-mux", },
435 { .compatible = "gpio-leds", },
436 {},
437 };
438
octeon_has_88e1145(void)439 static bool __init octeon_has_88e1145(void)
440 {
441 return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
442 !OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
443 !OCTEON_IS_MODEL(OCTEON_CN56XX);
444 }
445
octeon_fdt_set_phy(int eth,int phy_addr)446 static void __init octeon_fdt_set_phy(int eth, int phy_addr)
447 {
448 const __be32 *phy_handle;
449 const __be32 *alt_phy_handle;
450 const __be32 *reg;
451 u32 phandle;
452 int phy;
453 int alt_phy;
454 const char *p;
455 int current_len;
456 char new_name[20];
457
458 phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
459 if (!phy_handle)
460 return;
461
462 phandle = be32_to_cpup(phy_handle);
463 phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
464
465 alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
466 if (alt_phy_handle) {
467 u32 alt_phandle = be32_to_cpup(alt_phy_handle);
468 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
469 } else {
470 alt_phy = -1;
471 }
472
473 if (phy_addr < 0 || phy < 0) {
474 /* Delete the PHY things */
475 fdt_nop_property(initial_boot_params, eth, "phy-handle");
476 /* This one may fail */
477 fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
478 if (phy >= 0)
479 fdt_nop_node(initial_boot_params, phy);
480 if (alt_phy >= 0)
481 fdt_nop_node(initial_boot_params, alt_phy);
482 return;
483 }
484
485 if (phy_addr >= 256 && alt_phy > 0) {
486 const struct fdt_property *phy_prop;
487 struct fdt_property *alt_prop;
488 fdt32_t phy_handle_name;
489
490 /* Use the alt phy node instead.*/
491 phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
492 phy_handle_name = phy_prop->nameoff;
493 fdt_nop_node(initial_boot_params, phy);
494 fdt_nop_property(initial_boot_params, eth, "phy-handle");
495 alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
496 alt_prop->nameoff = phy_handle_name;
497 phy = alt_phy;
498 }
499
500 phy_addr &= 0xff;
501
502 if (octeon_has_88e1145()) {
503 fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
504 memset(new_name, 0, sizeof(new_name));
505 strcpy(new_name, "marvell,88e1145");
506 p = fdt_getprop(initial_boot_params, phy, "compatible",
507 ¤t_len);
508 if (p && current_len >= strlen(new_name))
509 fdt_setprop_inplace(initial_boot_params, phy,
510 "compatible", new_name, current_len);
511 }
512
513 reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
514 if (phy_addr == be32_to_cpup(reg))
515 return;
516
517 fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
518
519 snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
520
521 p = fdt_get_name(initial_boot_params, phy, ¤t_len);
522 if (p && current_len == strlen(new_name))
523 fdt_set_name(initial_boot_params, phy, new_name);
524 else
525 pr_err("Error: could not rename ethernet phy: <%s>", p);
526 }
527
octeon_fdt_set_mac_addr(int n,u64 * pmac)528 static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
529 {
530 u8 new_mac[6];
531 u64 mac = *pmac;
532 int r;
533
534 new_mac[0] = (mac >> 40) & 0xff;
535 new_mac[1] = (mac >> 32) & 0xff;
536 new_mac[2] = (mac >> 24) & 0xff;
537 new_mac[3] = (mac >> 16) & 0xff;
538 new_mac[4] = (mac >> 8) & 0xff;
539 new_mac[5] = mac & 0xff;
540
541 r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
542 new_mac, sizeof(new_mac));
543
544 if (r) {
545 pr_err("Setting \"local-mac-address\" failed %d", r);
546 return;
547 }
548 *pmac = mac + 1;
549 }
550
octeon_fdt_rm_ethernet(int node)551 static void __init octeon_fdt_rm_ethernet(int node)
552 {
553 const __be32 *phy_handle;
554
555 phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
556 if (phy_handle) {
557 u32 ph = be32_to_cpup(phy_handle);
558 int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
559 if (p >= 0)
560 fdt_nop_node(initial_boot_params, p);
561 }
562 fdt_nop_node(initial_boot_params, node);
563 }
564
octeon_fdt_pip_port(int iface,int i,int p,int max,u64 * pmac)565 static void __init octeon_fdt_pip_port(int iface, int i, int p, int max, u64 *pmac)
566 {
567 char name_buffer[20];
568 int eth;
569 int phy_addr;
570 int ipd_port;
571
572 snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
573 eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
574 if (eth < 0)
575 return;
576 if (p > max) {
577 pr_debug("Deleting port %x:%x\n", i, p);
578 octeon_fdt_rm_ethernet(eth);
579 return;
580 }
581 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
582 ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
583 else
584 ipd_port = 16 * i + p;
585
586 phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
587 octeon_fdt_set_phy(eth, phy_addr);
588 octeon_fdt_set_mac_addr(eth, pmac);
589 }
590
octeon_fdt_pip_iface(int pip,int idx,u64 * pmac)591 static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac)
592 {
593 char name_buffer[20];
594 int iface;
595 int p;
596 int count = 0;
597
598 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
599 iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
600 if (iface < 0)
601 return;
602
603 if (cvmx_helper_interface_enumerate(idx) == 0)
604 count = cvmx_helper_ports_on_interface(idx);
605
606 for (p = 0; p < 16; p++)
607 octeon_fdt_pip_port(iface, idx, p, count - 1, pmac);
608 }
609
octeon_prune_device_tree(void)610 int __init octeon_prune_device_tree(void)
611 {
612 int i, max_port, uart_mask;
613 const char *pip_path;
614 const char *alias_prop;
615 char name_buffer[20];
616 int aliases;
617 u64 mac_addr_base;
618
619 if (fdt_check_header(initial_boot_params))
620 panic("Corrupt Device Tree.");
621
622 aliases = fdt_path_offset(initial_boot_params, "/aliases");
623 if (aliases < 0) {
624 pr_err("Error: No /aliases node in device tree.");
625 return -EINVAL;
626 }
627
628
629 mac_addr_base =
630 ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
631 ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
632 ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
633 ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
634 ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
635 (octeon_bootinfo->mac_addr_base[5] & 0xffull);
636
637 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
638 max_port = 2;
639 else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
640 max_port = 1;
641 else
642 max_port = 0;
643
644 if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
645 max_port = 0;
646
647 for (i = 0; i < 2; i++) {
648 int mgmt;
649 snprintf(name_buffer, sizeof(name_buffer),
650 "mix%d", i);
651 alias_prop = fdt_getprop(initial_boot_params, aliases,
652 name_buffer, NULL);
653 if (alias_prop) {
654 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
655 if (mgmt < 0)
656 continue;
657 if (i >= max_port) {
658 pr_debug("Deleting mix%d\n", i);
659 octeon_fdt_rm_ethernet(mgmt);
660 fdt_nop_property(initial_boot_params, aliases,
661 name_buffer);
662 } else {
663 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
664 octeon_fdt_set_phy(mgmt, phy_addr);
665 octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
666 }
667 }
668 }
669
670 pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
671 if (pip_path) {
672 int pip = fdt_path_offset(initial_boot_params, pip_path);
673 if (pip >= 0)
674 for (i = 0; i <= 4; i++)
675 octeon_fdt_pip_iface(pip, i, &mac_addr_base);
676 }
677
678 /* I2C */
679 if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
680 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
681 OCTEON_IS_MODEL(OCTEON_CN68XX) ||
682 OCTEON_IS_MODEL(OCTEON_CN56XX))
683 max_port = 2;
684 else
685 max_port = 1;
686
687 for (i = 0; i < 2; i++) {
688 int i2c;
689 snprintf(name_buffer, sizeof(name_buffer),
690 "twsi%d", i);
691 alias_prop = fdt_getprop(initial_boot_params, aliases,
692 name_buffer, NULL);
693
694 if (alias_prop) {
695 i2c = fdt_path_offset(initial_boot_params, alias_prop);
696 if (i2c < 0)
697 continue;
698 if (i >= max_port) {
699 pr_debug("Deleting twsi%d\n", i);
700 fdt_nop_node(initial_boot_params, i2c);
701 fdt_nop_property(initial_boot_params, aliases,
702 name_buffer);
703 }
704 }
705 }
706
707 /* SMI/MDIO */
708 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
709 max_port = 4;
710 else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
711 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
712 OCTEON_IS_MODEL(OCTEON_CN56XX))
713 max_port = 2;
714 else
715 max_port = 1;
716
717 for (i = 0; i < 2; i++) {
718 int i2c;
719 snprintf(name_buffer, sizeof(name_buffer),
720 "smi%d", i);
721 alias_prop = fdt_getprop(initial_boot_params, aliases,
722 name_buffer, NULL);
723
724 if (alias_prop) {
725 i2c = fdt_path_offset(initial_boot_params, alias_prop);
726 if (i2c < 0)
727 continue;
728 if (i >= max_port) {
729 pr_debug("Deleting smi%d\n", i);
730 fdt_nop_node(initial_boot_params, i2c);
731 fdt_nop_property(initial_boot_params, aliases,
732 name_buffer);
733 }
734 }
735 }
736
737 /* Serial */
738 uart_mask = 3;
739
740 /* Right now CN52XX is the only chip with a third uart */
741 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
742 uart_mask |= 4; /* uart2 */
743
744 for (i = 0; i < 3; i++) {
745 int uart;
746 snprintf(name_buffer, sizeof(name_buffer),
747 "uart%d", i);
748 alias_prop = fdt_getprop(initial_boot_params, aliases,
749 name_buffer, NULL);
750
751 if (alias_prop) {
752 uart = fdt_path_offset(initial_boot_params, alias_prop);
753 if (uart_mask & (1 << i)) {
754 __be32 f;
755
756 f = cpu_to_be32(octeon_get_io_clock_rate());
757 fdt_setprop_inplace(initial_boot_params,
758 uart, "clock-frequency",
759 &f, sizeof(f));
760 continue;
761 }
762 pr_debug("Deleting uart%d\n", i);
763 fdt_nop_node(initial_boot_params, uart);
764 fdt_nop_property(initial_boot_params, aliases,
765 name_buffer);
766 }
767 }
768
769 /* Compact Flash */
770 alias_prop = fdt_getprop(initial_boot_params, aliases,
771 "cf0", NULL);
772 if (alias_prop) {
773 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
774 unsigned long base_ptr, region_base, region_size;
775 unsigned long region1_base = 0;
776 unsigned long region1_size = 0;
777 int cs, bootbus;
778 bool is_16bit = false;
779 bool is_true_ide = false;
780 __be32 new_reg[6];
781 __be32 *ranges;
782 int len;
783
784 int cf = fdt_path_offset(initial_boot_params, alias_prop);
785 base_ptr = 0;
786 if (octeon_bootinfo->major_version == 1
787 && octeon_bootinfo->minor_version >= 1) {
788 if (octeon_bootinfo->compact_flash_common_base_addr)
789 base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
790 } else {
791 base_ptr = 0x1d000800;
792 }
793
794 if (!base_ptr)
795 goto no_cf;
796
797 /* Find CS0 region. */
798 for (cs = 0; cs < 8; cs++) {
799 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
800 region_base = mio_boot_reg_cfg.s.base << 16;
801 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
802 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
803 && base_ptr < region_base + region_size) {
804 is_16bit = mio_boot_reg_cfg.s.width;
805 break;
806 }
807 }
808 if (cs >= 7) {
809 /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
810 goto no_cf;
811 }
812
813 if (!(base_ptr & 0xfffful)) {
814 /*
815 * Boot loader signals availability of DMA (true_ide
816 * mode) by setting low order bits of base_ptr to
817 * zero.
818 */
819
820 /* Asume that CS1 immediately follows. */
821 mio_boot_reg_cfg.u64 =
822 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
823 region1_base = mio_boot_reg_cfg.s.base << 16;
824 region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
825 if (!mio_boot_reg_cfg.s.en)
826 goto no_cf;
827 is_true_ide = true;
828
829 } else {
830 fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
831 fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
832 if (!is_16bit) {
833 __be32 width = cpu_to_be32(8);
834 fdt_setprop_inplace(initial_boot_params, cf,
835 "cavium,bus-width", &width, sizeof(width));
836 }
837 }
838 new_reg[0] = cpu_to_be32(cs);
839 new_reg[1] = cpu_to_be32(0);
840 new_reg[2] = cpu_to_be32(0x10000);
841 new_reg[3] = cpu_to_be32(cs + 1);
842 new_reg[4] = cpu_to_be32(0);
843 new_reg[5] = cpu_to_be32(0x10000);
844 fdt_setprop_inplace(initial_boot_params, cf,
845 "reg", new_reg, sizeof(new_reg));
846
847 bootbus = fdt_parent_offset(initial_boot_params, cf);
848 if (bootbus < 0)
849 goto no_cf;
850 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
851 if (!ranges || len < (5 * 8 * sizeof(__be32)))
852 goto no_cf;
853
854 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
855 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
856 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
857 if (is_true_ide) {
858 cs++;
859 ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
860 ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
861 ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
862 }
863 goto end_cf;
864 no_cf:
865 fdt_nop_node(initial_boot_params, cf);
866
867 end_cf:
868 ;
869 }
870
871 /* 8 char LED */
872 alias_prop = fdt_getprop(initial_boot_params, aliases,
873 "led0", NULL);
874 if (alias_prop) {
875 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
876 unsigned long base_ptr, region_base, region_size;
877 int cs, bootbus;
878 __be32 new_reg[6];
879 __be32 *ranges;
880 int len;
881 int led = fdt_path_offset(initial_boot_params, alias_prop);
882
883 base_ptr = octeon_bootinfo->led_display_base_addr;
884 if (base_ptr == 0)
885 goto no_led;
886 /* Find CS0 region. */
887 for (cs = 0; cs < 8; cs++) {
888 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
889 region_base = mio_boot_reg_cfg.s.base << 16;
890 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
891 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
892 && base_ptr < region_base + region_size)
893 break;
894 }
895
896 if (cs > 7)
897 goto no_led;
898
899 new_reg[0] = cpu_to_be32(cs);
900 new_reg[1] = cpu_to_be32(0x20);
901 new_reg[2] = cpu_to_be32(0x20);
902 new_reg[3] = cpu_to_be32(cs);
903 new_reg[4] = cpu_to_be32(0);
904 new_reg[5] = cpu_to_be32(0x20);
905 fdt_setprop_inplace(initial_boot_params, led,
906 "reg", new_reg, sizeof(new_reg));
907
908 bootbus = fdt_parent_offset(initial_boot_params, led);
909 if (bootbus < 0)
910 goto no_led;
911 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
912 if (!ranges || len < (5 * 8 * sizeof(__be32)))
913 goto no_led;
914
915 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
916 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
917 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
918 goto end_led;
919
920 no_led:
921 fdt_nop_node(initial_boot_params, led);
922 end_led:
923 ;
924 }
925
926 /* OHCI/UHCI USB */
927 alias_prop = fdt_getprop(initial_boot_params, aliases,
928 "uctl", NULL);
929 if (alias_prop) {
930 int uctl = fdt_path_offset(initial_boot_params, alias_prop);
931
932 if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
933 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
934 pr_debug("Deleting uctl\n");
935 fdt_nop_node(initial_boot_params, uctl);
936 fdt_nop_property(initial_boot_params, aliases, "uctl");
937 } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
938 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
939 /* Missing "refclk-type" defaults to crystal. */
940 fdt_nop_property(initial_boot_params, uctl, "refclk-type");
941 }
942 }
943
944 /* DWC2 USB */
945 alias_prop = fdt_getprop(initial_boot_params, aliases,
946 "usbn", NULL);
947 if (alias_prop) {
948 int usbn = fdt_path_offset(initial_boot_params, alias_prop);
949
950 if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 ||
951 !octeon_has_feature(OCTEON_FEATURE_USB))) {
952 pr_debug("Deleting usbn\n");
953 fdt_nop_node(initial_boot_params, usbn);
954 fdt_nop_property(initial_boot_params, aliases, "usbn");
955 } else {
956 __be32 new_f[1];
957 enum cvmx_helper_board_usb_clock_types c;
958 c = __cvmx_helper_board_usb_get_clock_type();
959 switch (c) {
960 case USB_CLOCK_TYPE_REF_48:
961 new_f[0] = cpu_to_be32(48000000);
962 fdt_setprop_inplace(initial_boot_params, usbn,
963 "refclk-frequency", new_f, sizeof(new_f));
964 /* Fall through ...*/
965 case USB_CLOCK_TYPE_REF_12:
966 /* Missing "refclk-type" defaults to external. */
967 fdt_nop_property(initial_boot_params, usbn, "refclk-type");
968 break;
969 default:
970 break;
971 }
972 }
973 }
974
975 if (octeon_bootinfo->board_type != CVMX_BOARD_TYPE_CUST_DSR1000N) {
976 int dsr1000n_leds = fdt_path_offset(initial_boot_params,
977 "/dsr1000n-leds");
978 if (dsr1000n_leds >= 0)
979 fdt_nop_node(initial_boot_params, dsr1000n_leds);
980 }
981
982 return 0;
983 }
984
octeon_publish_devices(void)985 static int __init octeon_publish_devices(void)
986 {
987 return of_platform_bus_probe(NULL, octeon_ids, NULL);
988 }
989 device_initcall(octeon_publish_devices);
990
991 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
992 MODULE_LICENSE("GPL");
993 MODULE_DESCRIPTION("Platform driver for Octeon SOC");
994